bugzilla-daemon [Fri, 15 May 2020 14:16:22 +0000 (14:16 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Fri, 15 May 2020 14:16:04 +0000 (14:16 +0000)]
[libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
bugzilla-daemon [Fri, 15 May 2020 14:15:25 +0000 (14:15 +0000)]
[libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
bugzilla-daemon [Fri, 15 May 2020 14:13:18 +0000 (14:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 15 May 2020 14:01:37 +0000 (14:01 +0000)]
[libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
bugzilla-daemon [Fri, 15 May 2020 14:01:16 +0000 (14:01 +0000)]
[libre-riscv-dev] [Bug 312] New: Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
bugzilla-daemon [Fri, 15 May 2020 14:00:10 +0000 (14:00 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 15 May 2020 13:51:27 +0000 (13:51 +0000)]
[libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline
Luke Kenneth Casson Leighton [Fri, 15 May 2020 13:44:44 +0000 (14:44 +0100)]
[libre-riscv-dev] marketnext online call, earlier today
bugzilla-daemon [Fri, 15 May 2020 13:18:05 +0000 (13:18 +0000)]
[libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline
Luke Kenneth Casson Leighton [Fri, 15 May 2020 12:05:58 +0000 (13:05 +0100)]
[libre-riscv-dev] daily kan-ban update 15may2020
bugzilla-daemon [Fri, 15 May 2020 11:43:58 +0000 (11:43 +0000)]
[libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline
bugzilla-daemon [Fri, 15 May 2020 11:34:29 +0000 (11:34 +0000)]
[libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline
bugzilla-daemon [Fri, 15 May 2020 11:30:51 +0000 (11:30 +0000)]
[libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline
bugzilla-daemon [Fri, 15 May 2020 11:30:10 +0000 (11:30 +0000)]
[libre-riscv-dev] [Bug 311] New: countzero function for Logic Pipeline
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:19:02 +0000 (12:19 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Fri, 15 May 2020 10:55:06 +0000 (11:55 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Fri, 15 May 2020 09:13:06 +0000 (10:13 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Fri, 15 May 2020 09:09:58 +0000 (10:09 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Tobias Platen [Fri, 15 May 2020 09:07:31 +0000 (11:07 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Fri, 15 May 2020 08:28:09 +0000 (09:28 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Yehowshua [Thu, 14 May 2020 23:16:20 +0000 (19:16 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Thu, 14 May 2020 22:52:31 +0000 (23:52 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Thu, 14 May 2020 22:42:24 +0000 (23:42 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Cole Poirier [Thu, 14 May 2020 22:29:20 +0000 (15:29 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Michael Nolan [Thu, 14 May 2020 22:00:09 +0000 (18:00 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Cole Poirier [Thu, 14 May 2020 21:54:37 +0000 (14:54 -0700)]
Re: [libre-riscv-dev] quick write-up about microwatt and Libre-SOC HDL
Cole Poirier [Thu, 14 May 2020 21:48:42 +0000 (14:48 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Thu, 14 May 2020 21:44:16 +0000 (22:44 +0100)]
[libre-riscv-dev] quick write-up about microwatt and Libre-SOC HDL
Luke Kenneth Casson Leighton [Thu, 14 May 2020 21:08:57 +0000 (22:08 +0100)]
[libre-riscv-dev] virtual coffee openpower, in 50 minutes
bugzilla-daemon [Thu, 14 May 2020 19:48:50 +0000 (19:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 19:27:52 +0000 (19:27 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 19:21:03 +0000 (19:21 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 19:10:19 +0000 (19:10 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 19:06:50 +0000 (19:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Thu, 14 May 2020 18:55:41 +0000 (19:55 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 18:42:58 +0000 (18:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Jacob Lifshay [Thu, 14 May 2020 18:28:24 +0000 (11:28 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 17:29:15 +0000 (17:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 17:14:34 +0000 (17:14 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:54:25 +0000 (16:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:44:16 +0000 (17:44 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 16:35:21 +0000 (16:35 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:21:38 +0000 (16:21 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:17:37 +0000 (16:17 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Tobias Platen [Thu, 14 May 2020 15:49:35 +0000 (17:49 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 15:34:27 +0000 (15:34 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:59:21 +0000 (14:59 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
bugzilla-daemon [Thu, 14 May 2020 14:48:35 +0000 (14:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:47:48 +0000 (14:47 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
Luke Kenneth Casson Leighton [Thu, 14 May 2020 14:43:33 +0000 (15:43 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 14:37:25 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:37:25 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
bugzilla-daemon [Thu, 14 May 2020 14:37:09 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 310] New: Function Units to cover multiple tasks
Michael Nolan [Thu, 14 May 2020 14:23:37 +0000 (10:23 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Thu, 14 May 2020 10:54:07 +0000 (11:54 +0100)]
[libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 00:20:45 +0000 (00:20 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 22:20:16 +0000 (23:20 +0100)]
[libre-riscv-dev] popcount and parity
Luke Kenneth Casson Leighton [Wed, 13 May 2020 22:02:47 +0000 (23:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 21:54:27 +0000 (21:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 19:54:06 +0000 (20:54 +0100)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
Jacob Lifshay [Wed, 13 May 2020 19:02:41 +0000 (12:02 -0700)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 18:57:54 +0000 (18:57 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Michael Nolan [Wed, 13 May 2020 18:51:48 +0000 (14:51 -0400)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 18:48:32 +0000 (18:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 18:46:13 +0000 (18:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:41:14 +0000 (19:41 +0100)]
Re: [libre-riscv-dev] note on memory operation requirements for linux
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:18:06 +0000 (19:18 +0100)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
Cole Poirier [Wed, 13 May 2020 18:07:07 +0000 (11:07 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 17:58:39 +0000 (17:58 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Jacob Lifshay [Wed, 13 May 2020 17:49:55 +0000 (10:49 -0700)]
[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 17:29:36 +0000 (17:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 17:27:26 +0000 (17:27 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
bugzilla-daemon [Wed, 13 May 2020 17:22:53 +0000 (17:22 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 16:46:39 +0000 (16:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 16:44:23 +0000 (16:44 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
bugzilla-daemon [Wed, 13 May 2020 16:21:23 +0000 (16:21 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
Luke Kenneth Casson Leighton [Wed, 13 May 2020 15:03:21 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Tobias Platen [Wed, 13 May 2020 14:43:41 +0000 (16:43 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Luke Kenneth Casson Leighton [Wed, 13 May 2020 14:33:53 +0000 (15:33 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Tobias Platen [Wed, 13 May 2020 13:56:47 +0000 (15:56 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 12:57:37 +0000 (12:57 +0000)]
[libre-riscv-dev] [Bug 309] New: investigate OpenTITAN
Luke Kenneth Casson Leighton [Wed, 13 May 2020 10:28:25 +0000 (11:28 +0100)]
[libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 09:38:44 +0000 (09:38 +0000)]
[libre-riscv-dev] [Bug 238] POWER Compressed Formal Standard writeup
bugzilla-daemon [Wed, 13 May 2020 09:38:44 +0000 (09:38 +0000)]
[libre-riscv-dev] [Bug 308] POWER variable-length encoding scheme needed
bugzilla-daemon [Wed, 13 May 2020 09:37:52 +0000 (09:37 +0000)]
[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed
bugzilla-daemon [Wed, 13 May 2020 09:19:25 +0000 (09:19 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Benjamin Herrenschmidt [Wed, 13 May 2020 01:41:00 +0000 (11:41 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Wed, 13 May 2020 09:11:44 +0000 (10:11 +0100)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Wed, 13 May 2020 08:17:20 +0000 (09:17 +0100)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Luke Kenneth Casson Leighton [Wed, 13 May 2020 08:09:08 +0000 (09:09 +0100)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Lauri Kasanen [Wed, 13 May 2020 06:29:53 +0000 (09:29 +0300)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Jacob Lifshay [Wed, 13 May 2020 02:56:45 +0000 (19:56 -0700)]
[libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Jacob Lifshay [Wed, 13 May 2020 02:27:26 +0000 (19:27 -0700)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
bugzilla-daemon [Wed, 13 May 2020 02:00:18 +0000 (02:00 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Hugh Blemings [Wed, 13 May 2020 01:22:01 +0000 (11:22 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
bugzilla-daemon [Wed, 13 May 2020 01:19:01 +0000 (01:19 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Wed, 13 May 2020 01:05:04 +0000 (01:05 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 00:16:35 +0000 (00:16 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Wed, 13 May 2020 00:15:00 +0000 (00:15 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
projects / libre-riscv-dev.git / log