Eddie Hung [Thu, 22 Aug 2019 02:18:40 +0000 (19:18 -0700)]
Reuse var
Eddie Hung [Thu, 22 Aug 2019 02:18:27 +0000 (19:18 -0700)]
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit
7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.
Eddie Hung [Thu, 22 Aug 2019 02:18:05 +0000 (19:18 -0700)]
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
Eddie Hung [Thu, 22 Aug 2019 01:43:17 +0000 (18:43 -0700)]
Trim shiftx_width when upper bits are 1'bx
Eddie Hung [Thu, 22 Aug 2019 00:36:38 +0000 (17:36 -0700)]
Add comment
Eddie Hung [Thu, 22 Aug 2019 00:34:40 +0000 (17:34 -0700)]
Add variable length support to xilinx_srl
Eddie Hung [Wed, 21 Aug 2019 22:46:58 +0000 (15:46 -0700)]
Rename pattern to fixed
Eddie Hung [Wed, 21 Aug 2019 22:44:07 +0000 (15:44 -0700)]
attribute -> attr
Eddie Hung [Wed, 21 Aug 2019 22:41:46 +0000 (15:41 -0700)]
Use Cell::has_keep_attribute()
Eddie Hung [Wed, 21 Aug 2019 22:37:55 +0000 (15:37 -0700)]
abc9 to perform new 'map_ffs' before 'map_luts'
Eddie Hung [Wed, 21 Aug 2019 22:35:29 +0000 (15:35 -0700)]
xilinx_srl to support FDRE and FDRE_1
Eddie Hung [Wed, 21 Aug 2019 21:42:11 +0000 (14:42 -0700)]
Fix polarity of EN_POL
Eddie Hung [Wed, 21 Aug 2019 21:35:40 +0000 (14:35 -0700)]
Add CLKPOL == 0
Eddie Hung [Wed, 21 Aug 2019 21:26:24 +0000 (14:26 -0700)]
Reject if not minlen from inside pattern matcher
Eddie Hung [Wed, 21 Aug 2019 20:47:47 +0000 (13:47 -0700)]
Get wire via SigBit
Eddie Hung [Wed, 21 Aug 2019 20:42:03 +0000 (13:42 -0700)]
Respect \keep on cells or wires
Eddie Hung [Wed, 21 Aug 2019 20:37:45 +0000 (13:37 -0700)]
Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
Eddie Hung [Wed, 21 Aug 2019 20:36:01 +0000 (13:36 -0700)]
mem2reg to preserve user attributes and src
Eddie Hung [Wed, 21 Aug 2019 20:05:10 +0000 (13:05 -0700)]
Add init support
Eddie Hung [Wed, 21 Aug 2019 19:54:11 +0000 (12:54 -0700)]
Fix spacing
Eddie Hung [Wed, 21 Aug 2019 19:50:49 +0000 (12:50 -0700)]
Initial progress on xilinx_srl
Clifford Wolf [Wed, 21 Aug 2019 07:12:56 +0000 (09:12 +0200)]
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
techmap -max_iter to apply to each module individually
Eddie Hung [Wed, 21 Aug 2019 03:37:52 +0000 (20:37 -0700)]
Missing newline
Eddie Hung [Wed, 21 Aug 2019 03:18:51 +0000 (20:18 -0700)]
Fix copy-paste typo
Eddie Hung [Wed, 21 Aug 2019 03:05:51 +0000 (20:05 -0700)]
Grammar
Eddie Hung [Wed, 21 Aug 2019 03:05:16 +0000 (20:05 -0700)]
Add test
Eddie Hung [Wed, 21 Aug 2019 02:48:16 +0000 (19:48 -0700)]
techmap -max_iter to apply to each module individually
Eddie Hung [Tue, 20 Aug 2019 19:55:26 +0000 (12:55 -0700)]
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
Eddie Hung [Tue, 20 Aug 2019 18:59:31 +0000 (11:59 -0700)]
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
Eddie Hung [Tue, 20 Aug 2019 18:57:52 +0000 (11:57 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Clifford Wolf [Tue, 20 Aug 2019 09:39:42 +0000 (11:39 +0200)]
Merge pull request #1298 from YosysHQ/clifford/pmgen
Improvements in pmgen
Clifford Wolf [Tue, 20 Aug 2019 09:39:23 +0000 (11:39 +0200)]
Merge branch 'master' into clifford/pmgen
Clifford Wolf [Tue, 20 Aug 2019 09:38:21 +0000 (11:38 +0200)]
Add test case for real parameters
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 20 Aug 2019 09:37:26 +0000 (11:37 +0200)]
Merge pull request #1308 from jakobwenzel/real_params
Handle real values when deriving ast modules
whitequark [Tue, 20 Aug 2019 00:45:41 +0000 (00:45 +0000)]
Merge pull request #1309 from whitequark/proc_clean-fix-1268
proc_clean: fix order of switch insertion
Eddie Hung [Mon, 19 Aug 2019 17:42:00 +0000 (10:42 -0700)]
Fix typo
Eddie Hung [Mon, 19 Aug 2019 17:41:18 +0000 (10:41 -0700)]
Fix typo
Eddie Hung [Mon, 19 Aug 2019 17:11:47 +0000 (10:11 -0700)]
ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
Eddie Hung [Mon, 19 Aug 2019 17:00:53 +0000 (10:00 -0700)]
Clarify with 'only'
Eddie Hung [Mon, 19 Aug 2019 16:59:57 +0000 (09:59 -0700)]
Update doc
Eddie Hung [Mon, 19 Aug 2019 16:56:17 +0000 (09:56 -0700)]
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
whitequark [Mon, 19 Aug 2019 16:44:23 +0000 (16:44 +0000)]
proc_clean: fix order of switch insertion.
Fixes #1268.
Jakob Wenzel [Mon, 19 Aug 2019 12:17:36 +0000 (14:17 +0200)]
handle real values when deriving ast modules
Clifford Wolf [Mon, 19 Aug 2019 11:09:12 +0000 (13:09 +0200)]
Merge pull request #1306 from mmicko/gitignore_fix
Ignore all generated headers for pmgen pass
Clifford Wolf [Mon, 19 Aug 2019 11:04:57 +0000 (13:04 +0200)]
Add *.sv to tests/simple_abc9/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 19 Aug 2019 11:04:06 +0000 (13:04 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Clifford Wolf [Mon, 19 Aug 2019 10:58:09 +0000 (12:58 +0200)]
Merge pull request #1305 from YosysHQ/clifford/testfast
Speed up "make test" and related cleanups
Eddie Hung [Mon, 19 Aug 2019 04:29:15 +0000 (21:29 -0700)]
Merge remote-tracking branch 'origin/master' into clifford/testfast
Eddie Hung [Mon, 19 Aug 2019 04:28:45 +0000 (21:28 -0700)]
Removal of more `stat` calls from tests
Miodrag Milanovic [Sun, 18 Aug 2019 08:49:17 +0000 (10:49 +0200)]
Ignore all generated headers for pmgen pass
whitequark [Sun, 18 Aug 2019 08:04:26 +0000 (08:04 +0000)]
Merge pull request #1290 from YosysHQ/eddie/pr1266_again
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
whitequark [Sun, 18 Aug 2019 08:04:10 +0000 (08:04 +0000)]
Merge branch 'master' into eddie/pr1266_again
Clifford Wolf [Sat, 17 Aug 2019 13:07:16 +0000 (15:07 +0200)]
Merge pull request #1283 from YosysHQ/clifford/fix1255
Fix various NDEBUG compiler warnings
Clifford Wolf [Sat, 17 Aug 2019 13:03:46 +0000 (15:03 +0200)]
Merge pull request #1303 from YosysHQ/bogdanvuk/opt_share
Implement opt_share from @bogdanvuk
Clifford Wolf [Sat, 17 Aug 2019 13:01:31 +0000 (15:01 +0200)]
Merge pull request #1300 from YosysHQ/eddie/cleanup2
Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
Clifford Wolf [Sat, 17 Aug 2019 12:47:02 +0000 (14:47 +0200)]
Fix erroneous ifndef-NDEBUG in verific.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 17 Aug 2019 12:37:07 +0000 (14:37 +0200)]
Speed up "make test" and related cleanups
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 17 Aug 2019 12:05:10 +0000 (14:05 +0200)]
Add test for pmtest_test "reduce" demo pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 17 Aug 2019 11:54:18 +0000 (13:54 +0200)]
Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 17 Aug 2019 11:53:55 +0000 (13:53 +0200)]
Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 17 Aug 2019 09:29:37 +0000 (11:29 +0200)]
Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 16 Aug 2019 23:38:49 +0000 (16:38 -0700)]
Use ID()
Eddie Hung [Fri, 16 Aug 2019 23:07:29 +0000 (16:07 -0700)]
Add doc for abc_* attributes
Eddie Hung [Fri, 16 Aug 2019 22:56:57 +0000 (15:56 -0700)]
Update abc_* attr in ecp5 and ice40
Eddie Hung [Fri, 16 Aug 2019 22:41:17 +0000 (15:41 -0700)]
Compute abc_scc_break and move CI/CO outside of each abc9
Eddie Hung [Fri, 16 Aug 2019 22:40:53 +0000 (15:40 -0700)]
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
Eddie Hung [Fri, 16 Aug 2019 21:07:09 +0000 (14:07 -0700)]
Merge pull request #1250 from bwidawsk/master
techlibs/intel: Clean up Makefile
Eddie Hung [Fri, 16 Aug 2019 21:01:55 +0000 (14:01 -0700)]
Use ID() macro
Eddie Hung [Fri, 16 Aug 2019 20:47:51 +0000 (13:47 -0700)]
Add 'opt_share' to CHANGELOG
Eddie Hung [Fri, 16 Aug 2019 20:47:37 +0000 (13:47 -0700)]
Add 'opt_share' to 'opt -full'
Eddie Hung [Fri, 16 Aug 2019 20:40:29 +0000 (13:40 -0700)]
Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
Eddie Hung [Fri, 16 Aug 2019 20:35:39 +0000 (13:35 -0700)]
Remove unused variable
Eddie Hung [Fri, 16 Aug 2019 20:00:12 +0000 (13:00 -0700)]
Add help() call
Eddie Hung [Fri, 16 Aug 2019 19:37:11 +0000 (19:37 +0000)]
Move namespace alias
Eddie Hung [Fri, 16 Aug 2019 19:36:45 +0000 (19:36 +0000)]
Remove `using namespace RTLIL;`
Clifford Wolf [Fri, 16 Aug 2019 12:35:13 +0000 (14:35 +0200)]
Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 16 Aug 2019 12:26:58 +0000 (14:26 +0200)]
Merge pull request #1302 from mmicko/dfflibmap_regression
DFFLIBMAP pass regression fix
Clifford Wolf [Fri, 16 Aug 2019 12:22:46 +0000 (14:22 +0200)]
Do not use Verific in tests/various/write_gzip.ys
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 16 Aug 2019 12:16:35 +0000 (14:16 +0200)]
Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 16 Aug 2019 11:47:50 +0000 (13:47 +0200)]
Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 16 Aug 2019 11:26:36 +0000 (13:26 +0200)]
Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanovic [Fri, 16 Aug 2019 11:21:11 +0000 (13:21 +0200)]
Regression in abc9
Miodrag Milanovic [Fri, 16 Aug 2019 08:22:04 +0000 (10:22 +0200)]
Just needed IDs to be IdString
Clifford Wolf [Fri, 16 Aug 2019 09:47:51 +0000 (11:47 +0200)]
Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 16 Aug 2019 08:36:11 +0000 (10:36 +0200)]
Add missing NMUX to "abc -g" handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 15 Aug 2019 23:20:54 +0000 (16:20 -0700)]
Try this for gcc-4.8?
Eddie Hung [Thu, 15 Aug 2019 21:54:41 +0000 (14:54 -0700)]
Fix spacing
Eddie Hung [Thu, 15 Aug 2019 21:51:12 +0000 (14:51 -0700)]
Use ID::keep more liberally too
Eddie Hung [Thu, 15 Aug 2019 21:50:10 +0000 (14:50 -0700)]
Use more ID::{A,B,Y,blackbox,whitebox}
Clifford Wolf [Thu, 15 Aug 2019 21:02:37 +0000 (23:02 +0200)]
Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 15 Aug 2019 20:56:32 +0000 (22:56 +0200)]
Merge pull request #1299 from YosysHQ/eddie/cleanup2
More cleanup, more use of ID() inside passes/techmap
Clifford Wolf [Thu, 15 Aug 2019 20:48:13 +0000 (22:48 +0200)]
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 15 Aug 2019 20:47:59 +0000 (22:47 +0200)]
Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 15 Aug 2019 20:44:38 +0000 (22:44 +0200)]
Merge branch 'master' into clifford/fix1255
Eddie Hung [Thu, 15 Aug 2019 18:25:42 +0000 (11:25 -0700)]
Fix
Eddie Hung [Thu, 15 Aug 2019 17:26:24 +0000 (10:26 -0700)]
Change signature of parse_blif to take IdString
Eddie Hung [Thu, 15 Aug 2019 17:25:54 +0000 (10:25 -0700)]
ID(\\.*) -> ID(.*)
Eddie Hung [Thu, 15 Aug 2019 17:24:35 +0000 (10:24 -0700)]
Convert a few more to ID
Eddie Hung [Thu, 15 Aug 2019 17:19:29 +0000 (10:19 -0700)]
Transform all "\\*" identifiers into ID()
Eddie Hung [Thu, 15 Aug 2019 17:05:08 +0000 (10:05 -0700)]
Transform "$.*" to ID("$.*") in passes/techmap