python: Improve how templated SimObject classes are handled.

When setting up a SimObject's Param structure, gem5 will autogenerate
a header file which attempts to declare the SimObject's C++ type. It
has had at least some level of sophistication there where it would
pull off the namespaces ahead of the class name and handle them
properly, but it didn't know how to handle templates.

This change improves that handling in two ways. First, it adds a new
magical SimObject attribute called 'cxx_template_params' which is used
to specify what the template parameters are as a list. For instance, if
your SimObject was a template which took an integer constant as its
first parameter and a type as its second, this attribute could look
like the following:

cxx_template_params = [ 'int FOO', 'class Bar' ]

Importantly, if there are any default values for these template
parameters, they should *not* be included here, they should be
specified where the class is later defined.

The second new mechanism is to add an internal CxxClass in the
SimObject.cxx_param_decl method. This class accepts the class signature
in the cxx_class attribute and the cxx_template_params and does two
things. First, it strips off namespaces like in the old implementation.
Second, it extracts and processes any template arguments attached to
the class. If these are constants (as determined by the contents of
cxx_template_params), then they are stored verbatim. If they're types,
then they're recursively expanded into a CxxClass and stored that way.
Note that these are the *values* of the template arguments, where as
cxx_template_params lists the *types* and *names* of those arguments.
In our earlier example, if cxx_class was:

cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>'

Then CxxClass would extract the namespace 'CoolClasses', the class
name 'ClassName', the argument '12', and the argument 'Fruit::Apple'.
That second argument would be expanded into a CxxClass with the
namespace 'Fruit' and the class name 'Apple'.

Importantly here, because there were no default arguments given in
cxx_template_params, all "hidden" arguments which would fall through
to their defaults need to be fully specified in cxx_class.

The CxxClass has a method called declare() which uses the information
extracted earlier to output all of the "stuff" necessary for declaring
the given class, including opening any containing namespaces and
putting template<...> ahead of the actual class declaration with the
template parameters specified.

If any of the template arguments are themselves CxxClass instances,
then they'll be recursively declared immediately before the current
class is.

An alternative solution to this problem might be to include the header
file which actually defines the cxx_class type to avoid having to
come up with a declaration. Unfortunately this doesn't work since it
can set up include loops where the SimObject C++ header file includes
the param header to get access to the Param type, but that includes
the C++ header to get access to the SimObject type.

This also makes it harder for SimObjects to refer to each other, since
they rely on the declaration in the params header files when declaring
a member pointer to that type in their own Param structures.

Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: fix disable_partial logic for fast binary

Partial linking should be disabled on darwin; however, the script
fails to do so when force_lto is set, which results in gem5 building
with fast option fails on macOS. This fix changes disable_partial
logic, which should be True once it's True.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: changed shebang on gem5img.py to python2.7

Change-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: tautological comparison of byteOrder

Error:
build/X86/mem/cache/prefetch/indirect_memory.cc:56:24:
error: result of comparison of constant -1 with expression
of type 'const ByteOrder' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
    fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n");
             ~~~~~~~~~ ^  ~~
build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if'
        if ((cond)) {                                           \
             ^~~~
1 error generated.

Fix:
cast of constant (-1) used in comparison

Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Removed circular include ref

If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.

Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the Indirect Memory Prefetcher

Reference:
    Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas.
    2015. IMP: indirect memory prefetcher. In Proceedings of the 48th
    International Symposium on Microarchitecture (MICRO-48). ACM,
    New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807

Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Move the Port base class into sim.

The Port class is going to be officially used for more than just memory
system connections.

Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Make EtherInt inherit from Port.

This way a common function can return EtherInt (and master and slave
ports).

Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Track the MemObject owner in MasterPort and SlavePort.

These types are much more tied to MemObjects and the gem5 memory
protocol than the Port or BaseMasterPort and BaseSlavePort classes.

Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

python: Simplify connectPorts() around EtherObject/EtherDevice.

EtherDevice now inherits EtherObject and shares the same getEthPort
virtual function, so there's no need to treat them separately any more.

Change-Id: Ia6c147fd97fece4a281c296521a7b095f793d32e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17030
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Make the EtherDevice class inherit EtherObject.

This avoids having to define two parallel versions of the getEthPort
function, and the complex dynamic_cast macrame in connectPorts().

Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Turn EtherObject into an interface class.

This class used to drive from SimObject so that it could be derived
from to get both the interface and SimObject while still using single
inheritance.

With this change, EtherObject is now just an interface class with only
one pure virtual function which can be inherited alongside SimObject.
This makes it more flexible so that it can be used in places where you
might want a different inheritance hierarchy, for instance to inherit
from MemObject.

Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Fix write hit latency calculation order

Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.

Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Teach cxxMethod how to set return_value_policy.

This is passed through to the underlying call to PyBindMethod.

Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Teach PyBindMethod how to set return_value_policy.

Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Refactor of Physical Register implementation

The implementation of the PhyRegId class is shared between multiple
cpu models. The o3/misc.hh should only be included in o3 models.

This patch removes the dependencies between different model
implementations, allowing to add new O3-like CPU model.

Change-Id: Ibb812517043befe75c48fab3ce9605a0d272870b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Fix unknown params and proxy multiplication

One of the recent changes made params not visible anymore:
    NameError: global name 'params' is not defined
This is fixed by adding the proper import statement.

However, the second error makes the multiplication values be assigned
to other proxies (that are not even used on the multiplication). A
workaround is added to prevent this from happening by extending "*=".

Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: cleanup of gicv3 CPU interface code and fixes

Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Don't use isdir in AddLocalRPATH.

isdir isn't a nice way to check if an FS.Base is a File or a Dir as was
initially assumed, it literally checks if a path can be stat-ed and is
reported as a directory by stat. This means that if a directory is
going to be created as part of the build, the result of that test will
change depending on whether that part of the build has happened
successfully before.

A better check which behaves as originally intended is to check whether
the Node is an instance of the SCons.Node.FS.Dir class.

Change-Id: Id041917d50b768a8205769c0a05320f92b09993c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17128
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add size to array unserialization error message

Add both acquired and expected size information to array
unserialization error message.

Change-Id: Ic0a493c5a7860066eb992e9e91e7a4746b197579
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16542
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: cleanup of gicv3 code

Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Removed default arg from get() in prefetch/base.hh

commit b0d1643 caused building against NULL to break due to
NULLIsa::GuestByteOrder not being defined.

Removal of default argument in src/mem/cache/prefetch/base.hh fixes
this.

Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0
Signed-off-by: Ryan Gambord
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-hsail: changed gen.py shebang from python(3) to python2.7

gen.py includes code_formatter from m5.util. code_formatter uses the
python2 __metaclass__ attribute, which is ignored by python3, causing
the code_formatter.pattern attribute to be unset.

This prevented scons from building against HSAIL_X86

Signed-off-by: Ryan Gambord
<gambordr@oregonstate.edu>

Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-arm: Fixing implicit fallthrough build errors

2c242d6 introduced implicit-fallthrough errors when building against
ARM.

Added "default: return new Unknown(machInst);" to offending switch
statements; please verify this is the corret behavior

Signed-off-by: Ryan Gambord
Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"

Reverting patch due to polymorphism limitations.

This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.

Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added extra information to PrefetchInfo

Added additional information to the PrefetchInfo data structure
- Whether the event is triggered by a cache miss
- Whether the event is a write or a read
- Size of the data accessed
- Data accessed by the request

Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add header delay to handleFill whenReady

A prefetch response will have a header delay, which was not being
taken into account.

Change-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow tag-only accesses on latency calculation

Some accesses only need to search for a tag in the tag array, with
no need to touch the data array. This is the case for CleanEvicts,
evicts that don't find a corresponding block entry (since a write
cannot be done in parallel with tag lookup), and maintenance
operations.

Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add lookup latency to access' whenReady

When dealing with writebacks, as soon as the packet metadata arrives
there will be a tag lookup, done sequentially because a write can't
be done in parallel. While the tag lookup is being done, the payload
will arrive. When both the payload are present and the tag is correct
block entry is determined the fill happens.

Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix recvTimingReq doWritebacks tick

Before being sent to the writebuffer, the evicted blocks
must be selected for replacement, and therefore the
access latency must be applied. The forward latency is
then applied on top of that delay.

Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use header delay on latency calculation

Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.

Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove old todo about latency in hit function

The header and payload delay have already been accounted and
zeroed previous to calling this function. The probe is not
allowed to modify the packet, therefore no extra delays are
added, and it is safe to remove the todo note.

Change-Id: I8ddf7e189fbe609cdec34364f3c013427930daf7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14875
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

util, tlm: Fix a memory error in the SCMasterPort class.

In the b_transport method of the SCMasterPort class, there is a check
which determines whether the packet being sent to gem5 should be
deleted once the call to sendAtomic returns. This was deleting the
packet if extension was *not* nullptr.

This check should delete the packet if the extension *is* nullptr. The
reasoning is that the extension will equal nullptr if there was no
gem5 packet in an extension and a new one needed to be allocated. If
there was an extension, ie if extension is not nullptr, then that's
where the packet came from which therefore doesn't belong to us. In
that case, we need to leave it alone and let its owner clean it up.

With the check reversed, this method will either leak allocated packets
it should delete, or delete packets it shouldn't that someone else will
likely try to use later.

Change-Id: I61578d910be6e5085b9fc0ddaa82468b1ac68578
Reviewed-on: https://gem5-review.googlesource.com/c/16949
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

tlm: Add some includes to some tlm_utils header files.

These bring in some pieces that those headers use but were only
coincidentally included by something else when they were used.

Change-Id: I5f119260d8f25d914d8545a60834f23f65f82d0c
Reviewed-on: https://gem5-review.googlesource.com/c/16948
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

python: Fix issue when Self proxy resolves to a another proxy

The problem occurs when a proxy is being resolved to another proxy
that hasn't been resolved yet. The problematic case that was
triggering this issues in the VGIC. It was caused by parameters
looking a bit like this:

gic = Param.GicV2(Parent.any)
some_param = Param.Int(Self.gic.some_param)

When 'some_param' was resolved, it found the 'gic' parameter in
Self. However, that parameter hadn't been resolved yet, so the
existing code was setting the proxy evaluation context to the
unresolved Parent.any proxy without first unproxying it.

It seems like this bug depends on the graph traversal order and I have
so far only seen it when compiling gem5 with Python 3.

Change-Id: Iea12cc138765e70bfd6bb776b1efa012364db066
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16004
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads

Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits
which are aliased to the register.

Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16545
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on reads

Reading ICV_IGRPEN<n>_EL1 should return the value of VMCR_EL2.VENG0 and
VMCR_EL2.VENG1 bits.

Change-Id: Ia5d748cf60ba074cccf4c127ac479c5cb881773d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16544
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: implement floating point aarch32 VCVTA family

These instructions round floating point to integer, and were added to
aarch32 as an extension to ARMv7.

Change-Id: I62d1705badc95a4e8954a5ad62b2b6bc9e4ffe00
Reviewed-on: https://gem5-review.googlesource.com/c/16788
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Move systemc disabling checks to SConsopts.

This will ensure that the value of USE_SYSTEMC is consistent throughout
the build. It also has the side effect that USE_SYSTEMC can be forced
to a particular value if you're confident you know what you're doing
and want to override these checks.

Change-Id: I0f2d1153245ff17ce4a828c6b7496cb9ded6bd5b
Reviewed-on: https://gem5-review.googlesource.com/c/16810
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

ruby: Fix garnet's round robin arbitration for vc selection

Garnet utilizes round robin policy to select a VC for
transmission ar Network Interface and Routers. The current logic
for round robin is only fair if all the virtual networks are active
at a given router. If the router or network interface is not
receiving traffic in from any vnet then the priority is always taken
up by the next vnet in numerically (or loops back to 0).

This fix changes the way we perform round robin arbitration. When
a VC is selected in a cycle, the round robin pointer is set to the VC
next to it and is iterated from there on. If any VC does not have a
flit in a given cycle, it will lose its turn until the next round.
At maximum traffic this will model round robin correctly even if
a certain VNET is not active at that unit.

Change-Id: I9bf805221054f9f25bee14b57ff521f4ce4ca980
Reviewed-on: https://gem5-review.googlesource.com/c/16688
Reviewed-by: Jieming Yin <Jieming.Yin@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Sandbox Based Optimal Offset Implementation

Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862
Reviewed-on: https://gem5-review.googlesource.com/c/15095
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Segmentation Fault during O3PipeView execution

During the O3PipeView execution, a potential invalid iterator is used to
Update the instruction storeTick field.

If the store_idx iterator is the first() of the StoreQueue, the
corresponding instruction is removed from the queue, leaving the iterator
invalid and not usable in the TRACING_ON block.

This patch uses the store_inst variable to access (and update) the
instruction tick, instead of the (potential) invalid one.

Change-Id: I671052ef282b9048e5239da8629b89e8afa86bf0
Reviewed-on: https://gem5-review.googlesource.com/c/16322
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix indirect branch history updates

Recent changes to indirect branch predictor interface accesses
non-existent buffers even when indirect predictor is not in use.

Change-Id: I0df9ac4d5f6f3cb63e4d1bd36949c27f7611eef6
Reviewed-on: https://gem5-review.googlesource.com/c/16668
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-cache: Copy over flags to forwarded response

A cache that forwards a request to the memory below does not fill and
forwards the response with the data to cache above. This change
ensures that the flags of the original response are also preserved.

Change-Id: I244b20b073c31b976358816c5b14bba413b8271f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16182
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

configs: Fix Python 3 iterator and exec compatibility issues

Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.

This change doesn't fix import paths since that might require us to
restructure the configs slightly.

Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>

scons: Marshal Python sources using the same Python as gem5

We currently use the Python version used by scons to marshal Python
code. This doesn't work when building gem5 with Python 3 support since
scons typically runs in Python 2.7. Add a custom marshal helper that
links with the same library as gem5 to generate byte code that is
guaranteed to work in gem5's Python interpreter.

Change-Id: I665b0f2078726d4c055d74a3e668a580fc613b59
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16422
Reviewed-by: Gabe Black <gabeblack@google.com>

systemc: Remove _m5.systemc passthroughs from SystemC_Kernel.

These functions are now exposed through m5.systemc and m5.tlm.

Change-Id: I9f519debbe7380ee38594badcc1146e66e15f8a8
Reviewed-on: https://gem5-review.googlesource.com/c/16570
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Update the systemc example to use m5.systemc for sc_main.

Change-Id: I431d3f2c18964bac1a3f19eacfffd49cd6e50fa2
Reviewed-on: https://gem5-review.googlesource.com/c/16569
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Update the sc_main.py config to use m5.systemc.

Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991
Reviewed-on: https://gem5-review.googlesource.com/c/16568
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Get rid of --working-dir in the test's config.py.

This option is no longer used and isn't needed.

Change-Id: Iec1e2799b4f8c9ea258614323d55941b55828d27
Reviewed-on: https://gem5-review.googlesource.com/c/16565
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Start using the m5.systemc module in the test config.py.

Start using sc_main and sc_main_result from the systemc module, and
stop using the versions of those functions which are attached to the
SystemC_Kernel SimObject.

Change-Id: I802898038c80ed36e6a9176211cffb7e0fde2d7e
Reviewed-on: https://gem5-review.googlesource.com/c/16564
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Add m5.systemc and m5.tlm python modules.

These will be how systemc and tlm APIs which are not attached to
SimObjects will be exposed. This avoids having to artificially attach
them to wrapping SimObjects for instance, which is a bit awkward
and non-obvious.

The python code which attaches the systemc and tlm modules to the
m5 modules lives in src/python/m5/__init__.py, but the modules
themselves live in src/systemc/python to keep all the systemc code
grouped together. It might be a little confusing to have a small part
of the glue that adds those modules in a separate place (__init__.py),
but that is, as far as I can tell, unavoidable, and it's better in my
opinion to keep the systemc code grouped together than to put it
alongside the other python code and __init__.py.

Change-Id: Iecb218daec5e15772152b5ad22b51f43b86c3d4b
Reviewed-on: https://gem5-review.googlesource.com/c/16563
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Export the tlm::tlm_global_quantum class to python.

This way the python code can set up the global quantum without having
an sc_main function to do it.

Change-Id: I96df4dea0f1bfe9e3e86d4784bbda8f5b6b74d0b
Reviewed-on: https://gem5-review.googlesource.com/c/16503
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Export the sc_core::sc_time class to python.

This class isn't incredibly useful in python, but it's needed to call
some other functions which are more useful.

Change-Id: I5c23cca0b50f0455423399db8b009bdf86a6ec41
Reviewed-on: https://gem5-review.googlesource.com/c/16502
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: added missing override specifier in BoP

Added missing specifier for various virtual functions.

Change-Id: I41aebb3b76bce6dd3bee21ac0e2b0e52cb90fc80
Reviewed-on: https://gem5-review.googlesource.com/c/16728
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Stop using basestring to test for strings

The base class basestring doesn't exist in Python 3. Use string_types
from six instead.

Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15998
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>

python: Add Python 3 workarounds for long

Python 3 doesn't have a separate long type. Make long an alias for int
where needed to maintain compatibility.

Change-Id: I4c0861302bc3a2fa5226b3041803ef975d29b2fd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15988
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: Update test scripts to work with Python 3

Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: A Best-Offset Prefetcher

Michaud, P. (2015, June). A best-offset prefetcher.
In 2nd Data Prefetching Championship.

Change-Id: I61bb89ca5639356d54aeb04e856d5bf6e8805c22
Reviewed-on: https://gem5-review.googlesource.com/c/14820
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Fix params/proxy import loop

There is a circular dependency between params and proxy at import
time. This causes issues for Python 3. Add the imports to the specific
methods with the dependencies to make the import happen when the
method is executed instead.

Change-Id: I770112fd3c07c395459e204976942bda3dc7236f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15993
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>

scons: Add support for specifying Python version

Add a sticky variable (PYTHON_CONFIG) to select which python-config
version to use. This can, for example, be used to build with Python 3
or with Python 2.7 in a custom location.

Change-Id: I1f4c00d66f85a9c99f50fe4d746b69dd82b60b4b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16003
Reviewed-by: Gabe Black <gabeblack@google.com>

python: Enforce absolute imports for Python 3 compatibility

Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15983
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: conditional use of new RPATH inclusion

On OSX, clang doesn’t support the -z option.
This patch resolve the compiler error produced on MacOS platform.

Change-Id: Idfe69c30fe40add97d16d0f2e25e598b30d26a9d
Reviewed-on: https://gem5-review.googlesource.com/c/16649
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

python: Add fallbacks for packages that have been renamed

Python 3 has restructured some packages. Specifically, __builtin__ has
been renamed to builtins and urlparse has been included in urllib.

Change-Id: I81f8f3942471db1043006a36abbad6e5a49e0a43
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15994
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>

python: Fix param -> int conversion issues

Python 3 doesn't convert params to integers automatically in
range(). Add __index__ to CheckedInt to enable implicit conversions
again. Add explicit conversions where necessary.

Change-Id: I2de6c9906d3bb7616f12ada6728b9e4b1928511c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16000
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Add cache read ports limit to LSQ

This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.

Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13517
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

python: Add missing operators to NumericParamValue

Add missing operators to NumericParamValue and ensure that they are
able to work on the underlying value if the right hand side is a
param.

Change-Id: I2bd86662aee9891bbd89aed7ebe20b827b5528bd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16001
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add a mechanism to iterate all entries of an AssociativeSet

Added functions to obtain an iterator to access all entries of
an AssociativeSet container.

Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

scons: Add a convenience method to set RPATH for local libraries.

When linking in a dynamic library which is in the gem5 build directory,
it's useful to set RPATH so that you don't have to set LD_LIBRARY_PATH
when you run gem5 so that the dynamic linker can find it.

Since it's tricky and not entirely obvious how to set up those paths
correctly, this change adds a small convenience function which does
that for you. It also handles situations where the same dynamic
library may be linked into different binaries in different directories
which each need a different relative RPATH. It does that by letting the
environment for each binary set a construction variable which says
how to get from that particular binary back to the build directory.
This helper method then sets RPATH to start at $ORIGIN (the binary),
to follow that relative path to the variant build directory, and then
the per-library but not per-binary path to the library's directory.

This change also adds the -z origin linker flag which makes the linker
handle $ORIGIN properly.

Change-Id: I45f4d72cd14396a73e0b963cea6a39d9bfb7f984
Reviewed-on: https://gem5-review.googlesource.com/c/16566
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Make the verify.py script work when run from different dirs.

The verify.py script ran scons from the CWD, and that would fail if
there wasn't a SConstruct in that directory, ie if it wasn't from the
source of the checkout.

This change makes verify.py use scons' --directory option to run from
where the SConstruct is, or at least the SConstruct which was checked
out alongside that copy of verify.py. That location can be overridden
using the new -C or --scons-dir options.

Change-Id: I9f033d6dd30e0c2992b7f3102c573b34ea9c49e0
Reviewed-on: https://gem5-review.googlesource.com/c/16562
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

ext: test: Split up the GTEST_CPPFLAGS and CPPFLAGS.

scons seems to get confused in some situations when this is a single
large string and passes it as one big argument to g++ instead of
breaking it up into several arguments.

We need to do the work for it and break it into individual arguments,
like what was already being done with GTEST_LIBS.

Also wrap some overly long lines.

Change-Id: Ib7688a7abced43a9c62994d17b78d358fc0dc000
Reviewed-on: https://gem5-review.googlesource.com/c/16567
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Make sc_(pause|stop) exit to python when not using sc_main.

In those cases, there's no sc_main to return control to. The python
config script is serving more or less the same purpose, so we can
return control to there instead.

Change-Id: I3cf0623ae51d989b883fb8556ebbf44651bbec99
Reviewed-on: https://gem5-review.googlesource.com/c/16445
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Init some values in the scheduler for running without sc_main.

When running without sc_main, sc_start won't be called, and therefore
runToTime and maxTick won't be initialized. To avoid the scheduler
getting confused and behaving erratically, those values should be
initialized to something that makes sense in situations where there's
no sc_main.

Change-Id: I6ddd7db9ecb36d716eb5ef75e1c38bb99a386092
Reviewed-on: https://gem5-review.googlesource.com/c/16443
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Handle exceptions "correctly" even if sc_main hasn't been run.

If sc_main hasn't run, for instance if there isn't an sc_main and gem5
is orchestrating the simulation directly, then exceptions shouldn't be
thrown to the sc_main fiber since it isn't running and may not be able
to run since sc_main may not even exist.

Instead, we need to check whether it makes sense to throw to sc_main,
and if not pass the exception directly to the report handler since
there likely won't be anyone to catch it if we just throw it from the
scheduler or into general purpose gem5.

Since the name throwToScMain is no longer a complete description for
what that function does, this change renames it to throwUp, since it
will now throw exceptions up the stack, either to sc_main or to the
conceptual top level by going directly to the report handler.

Change-Id: Ibdc92c9cf213ec6aa15ad654862057b7bf2e1c8e
Reviewed-on: https://gem5-review.googlesource.com/c/16442
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Added the Slim AMPM Prefetcher

Reference:
    Towards Bandwidth-Efficient Prefetching with Slim AMPM.
    Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Fix Param initialization issue in Python 3

When initializing a param with a SimObject NULL pointer, convert()
checks if the 'ptype' attribute has been created and whether the value
is NULL. In that case, it assumes that the object is being
initizalized as a part of SimObject initialization and defers the
conversion. This check is implemented using hasattr() which in turn is
implemented using the __getattr__ implementation that asserts because
all SimObjects haven't been initialized yet.

Implement the check using a lookup in the object's dictionary instead
to prevent the SimObject lookup.

Change-Id: I7367563c4fb71f6d2be541ebdc0be418e9f73d48
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15990
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Use __name__ instead of func_name for Py3 compat

Change-Id: I62a9685b4bce7e9012bc65309fcafe26135fde6d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15997
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Add __bool__ helpers in addition to __nonzero__

Python 3 uses __bool__ instead of __nonzero__ when performing a
Boolean comparison.

Change-Id: I85185bbe136ecae67346fa23569e24edd7329222
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

config: Make parameter conversion handle integers in other bases.

Python's float() function/type can't handle hexadecimal notation, but
int() can. Since there are also cases where converting to a float and
then back to an int (or long) can cause rounding error, this change
splits toFloat and toInteger apart and makes them call a worker
function which accepts a conversion function which does the work of
converting a numeric string into an actual number.

in the case of toFloat, it still uses the standard float(), and in the
case of toInteger it uses a lambda which wraps int(x, 0).

Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c
Reviewed-on: https://gem5-review.googlesource.com/c/16504
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Call the base class's regStats in X86ISA::TLB

When I try to build x86 architecture and run the se.py sample script
with helloworld example, there is a panic warning stated "Not all stats
have been initialized. You may need to add <ParentClass>::regStats() to
a new SimObject's regStats() function."

I see that in x86 tlb.cc, there is no initialization in regStats() function
that causes memory allocation error in some machine which make gem5 exit
abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and
can solve the problem

Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
Reviewed-on: https://gem5-review.googlesource.com/c/16522
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a mechanism to exit the simulation loop immediately.

There are some cases, specifically when running systemc, that it's
necessary to exit the simulation loop immediately rather than finishing
running events scheduled for the current Tick. When running under
sc_main, sc_stop and sc_pause return control to sc_main which can
happen immediately. When running without sc_main, control needs to
return to the python config script which needs to happen through a
global exit event.

Since sc_pause and sc_stop are supposed to stop simulation without
necessarily letting all the events at the current time run, we need
a way to schedule an exit event with a very high priority (rather than
a very low priority).

This change adds a new exitSimLoopNow function which does that, and
adds a new constructor to the GlobalSimLoopExitEvent which uses that
priority.

Also, a couple of cruft functions from the sim events are removed.

Change-Id: Icfbec17fb10f98084a75740acd839dbf4096fbb3
Reviewed-on: https://gem5-review.googlesource.com/c/16444
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Add ISA* getter in Thread interface

This patch is adding a ISA* getter to the TC interface

Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Reviewed-on: https://gem5-review.googlesource.com/c/16462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-generic: Making base TLB class a MemObject

Allow configuring a TLB hierarchy using ports

Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Reviewed-on: https://gem5-review.googlesource.com/c/14117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Move GICv3 detection at startup time

At the moment the haveGicV3 parameter is used only to signal its
presence when reading the MISCREG_ID_AA64PFR0_EL1 register.  It depends
on the system->getGIC pointing to a GICv3 model.  However this pointer
is set in the System only at init time (after construction), which means
that the haveGICv3CPUInterface will always be false.
This patch is fixing this by moving the parameter initialization at
startup time, together with the cpu interface registration.

Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: LPI support for GICv3. This doesn't include an ITS model.

Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7
Reviewed-on: https://gem5-review.googlesource.com/c/16142
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix enums checkpointing

Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them.  The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.

Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16382
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix fast build broken due to unused variable

This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b
(fast build is striping out assertions)

Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16463
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Make an include in src/systemc/ext use a relative path.

The includes in src/systemc/ext are supposed to use relative paths so
that they can be included in other bodies of code which aren't based
in gem5 and don't share it's -I-s, or potentially even have access to
anything outside of src/systemc/ext.

Change-Id: Icde457329c2c4ab4689221015bfcfe2ff8b051f0
Reviewed-on: https://gem5-review.googlesource.com/c/16262
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Added 8KB and 64KB TAGE-SC-L branch predictor

The original paper of the branch predictor can be found here:
http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf

Change-Id: I684863752407685adaacedebb699205c3559c528
Reviewed-on: https://gem5-review.googlesource.com/c/14855
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: simpoint-profile usable with NonCachingCPUs only

NonCachingCPU is replacing the Atomic+fastmem option.

Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15935
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Remove uses of tuple unpacking in function params

Python 3 doesn't support tuple unpacking in function parameters and
lambdas.

Change-Id: I36c72962e33a9ad37145089687834becccc76adb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15991
Reviewed-by: Gabe Black <gabeblack@google.com>

python: Replace deprecated repr syntax

Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15989
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

python: Switch from using compare to key in list sort

Python 3 has deprecated the use of a comparison function in favour of
a key extraction function.

Change-Id: I4b7eab791ecbdfbf7147f57fdbc7cbe8f1de20dd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15995
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

tests: add cpu tests to the new testing infrastructure

Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15857
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Move test programs paths to related test scripts

This change is needed to make sure that the DownloadedProgram fixture
does not fail, in case the test binaries are not stored in test-progs/
(e.g. in the case of cpu tests)

Change-Id: Icf96f2537b038502e78da560c7ccebc44984b509
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15856
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rutuja Govind Oza <roza@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>