Erfan Azarkhish [Tue, 3 Nov 2015 18:17:57 +0000 (12:17 -0600)]
mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube (HMC).
SerialLink is a simple variation of the Bridge class, with the ability to
account for the latency of packet serialization. Also trySendTiming has been
modified to correctly model bandwidth.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:56 +0000 (12:17 -0600)]
mem: hmc: adds controller
This patch models a simple HMC Controller. It simply schedules the incoming
packets to HMC Serial Links using a round robin mechanism. This patch should
be applied in series with other patches modeling a complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:56 +0000 (12:17 -0600)]
mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It
highly reuses the existing components in gem5's general memory system with some
small modifications. This changeset requires additional patches to model a
complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Palle Lyckegaard [Tue, 3 Nov 2015 18:17:55 +0000 (12:17 -0600)]
sparc: add missing parameter to makeSparcSystem()
makeSparcSystem() in configs/common/FSConfig.py is missing the cmdLine
parameter Without the parameter the simulation fails to start. With the
parameter the simulation starts properly.
Nathanael Premillieu [Thu, 29 Oct 2015 12:48:26 +0000 (08:48 -0400)]
arm: Add secure flag to TableWalker request when needed
Sascha Bischoff [Thu, 29 Oct 2015 12:48:25 +0000 (08:48 -0400)]
dev: Fix segfault in flash device
Fix a bug in which the flash device would write out of bounds and
could either trigger a segfault and corrupt the memory of other
objects. This was caused by using pageSize in the place of
pagesPerBlock when running the garbage collector.
Also, added an assert to flag this condition in the future.
Sascha Bischoff [Thu, 29 Oct 2015 12:48:24 +0000 (08:48 -0400)]
dev: Fix draining for UFSHostDevice and FlashDevice
This patch fixes the drain logic for the UFSHostDevice and the
FlashDevice. In the case of the FlashDevice, the logic for CheckDrain
needed to be reversed, whilst in the case of the UFSHostDevice check
drain was never being called. In both cases the system would never
complete draining if the initial attampt to drain failed.
Victor Garcia [Thu, 29 Oct 2015 12:48:23 +0000 (08:48 -0400)]
kvm, arm: Fix compilation errors due to API changes
The checkpoint changes, along with the SMT patches have changed a
number of APIs. Adapt the ArmKvmCPU accordingly.
Andreas Hansson [Thu, 29 Oct 2015 12:48:20 +0000 (08:48 -0400)]
mem: Clarify cache MSHR handling on fill
This patch addresses the upgrading of deferred targets in the MSHR,
and makes it clearer by explicitly calling out what is happening
(deferred targets are promoted if we get exclusivity without asking
for it).
Boris Shingarov [Sun, 25 Oct 2015 23:01:52 +0000 (16:01 -0700)]
power: Implement Remote GDB
Andreas Hansson [Fri, 23 Oct 2015 13:51:12 +0000 (09:51 -0400)]
x86: Add missing explicit overrides for X86 devices
Make clang >= 3.5 happy when compiling build/X86/gem5.opt on OSX.
Andreas Hansson [Fri, 23 Oct 2015 13:51:11 +0000 (09:51 -0400)]
arm: Add missing explicit overrides for ARM devices
Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX.
Andreas Hansson [Wed, 14 Oct 2015 17:32:28 +0000 (13:32 -0400)]
mem: Pass snoop retries through the CommMonitor
Allow the monitor to be placed after a snooping port, and do not fail
on snoop retries, but instead pass them on to the slave port.
Nilay Vaish [Wed, 14 Oct 2015 05:29:43 +0000 (00:29 -0500)]
ruby: profiler: provide the number of vnets through ruby system
The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().
Nilay Vaish [Wed, 14 Oct 2015 05:29:39 +0000 (00:29 -0500)]
ruby: remove unused functionalRead() function.
Not required since functional reads cannot rely on messages that are inflight.
Nilay Vaish [Wed, 14 Oct 2015 05:29:38 +0000 (00:29 -0500)]
ruby: garnet: flexible: refactor flit
Andreas Hansson [Mon, 12 Oct 2015 08:08:01 +0000 (04:08 -0400)]
misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.
As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
Andreas Hansson [Mon, 12 Oct 2015 08:07:59 +0000 (04:07 -0400)]
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
Joel Hestness [Sat, 10 Oct 2015 21:45:41 +0000 (16:45 -0500)]
stats: Update for UDelayEvent quiesce change
Joel Hestness [Sat, 10 Oct 2015 21:45:38 +0000 (16:45 -0500)]
sim: Don't quiesce UDelayEvents with 0 latency
ARM uses UDelayEvents to emulate kernel __*udelay functions and speed up
simulation. UDelayEvents call Pseudoinst::quiesceNs to quiesce the system for
a specified delay. Changeset 10341:
0b4d10f53c2d introduced the requirement
that any quiesce process that is started must also be completed by scheduling
an EndQuiesceEvent. This change causes the CPU to hang if an IsQuiesce
instruction is executed, but the corresponding EndQuiesceEvent is not
scheduled.
Changeset 11058:
d0934b57735a introduces a fix for uses of PseudoInst::quiesce*
that would conditionally execute the EndQuiesceEvent. ARM UDelayEvents specify
quiesce period of 0 ns (src/arch/arm/linux/system.cc), so changeset 11058
causes these events to now execute full quiesce processes, greatly increasing
the total instructions executed in kernel delay loops and slowing simulation.
This patch updates the UDelayEvent to conditionally execute
PseudoInst::quiesceNs (**a quiesce operation**) only if the specified
delay is >0 ns. The result is ARM delay loops no longer execute instructions
for quiesce handling, and regression time returns to normal.
Rekai Gonzalez Alberquilla [Fri, 9 Oct 2015 19:50:54 +0000 (14:50 -0500)]
isa: Add parameter to pick different decoder inside ISA
The decoder is responsible for splitting instructions in micro
operations (uops). Given that different micro architectures may split
operations differently, this patch allows to specify which micro
architecture each isa implements, so different cores in the system can
split instructions differently, also decoupling uop splitting
(microArch) from ISA (Arch). This is done making the decodification
calls templates that receive a type 'DecoderFlavour' that maps the
name of the operation to the class that implements it. This way there
is only one selection point (converting the command line enum to the
appropriate DecodeFeatures object). In addition, there is no explicit
code replication: template instantiation hides that, and the compiler
should be able to resolve a number of things at compile-time.
Dylan Johnson [Fri, 9 Oct 2015 19:27:09 +0000 (14:27 -0500)]
sim: Add relative break scheduling
Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
arch: clean up isa_parser error handling
Although some decent error messages were getting generated inside
isa_parser.py, they weren't always getting printed because of the
screwy way we were handling exceptions. (Basically an inner
exception would get hidden by an outer exception, and the more
informative inner error message would not get printed.)
Also line numbers were messed up, since they were taken from the
lexer, which is typically a token (or more) ahead of the grammar
rule that's being matched. Using the 'lineno' attribute that
PLY associates with the grammar production is more accurate.
The new LineTracker class extends lineno to track filenames as
well as line numbers.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
sim: add ExecMacro to Exec* compound debug flags
Really should have been there in the first place, IMO.
Makes debugging x86 execution a lot easier.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
sim: print pid in output header
This information is useful if you have a bunch of simulations running
and want to know which one to kill, but you've neglected to take
advantage of the previous patch and embed the pid in your output path.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
x86: implement rcpps and rcpss SSE insts
These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.
This code was basically developed by copying the code for
sqrtps and sqrtss. The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
x86: implement fild, fucomi, and fucomip x87 insts
fild loads an integer value into the x87 top of stack register.
fucomi/fucomip compare two x87 register values (the latter
also doing a stack pop).
These instructions are used by some versions of GNU libstdc++.
Curtis Dunham [Tue, 6 Oct 2015 23:08:28 +0000 (18:08 -0500)]
ext: fix SST connector
The renamings in changesets
8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and
fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector. This commit repeats those renamings in ext/sst.
Dylan Johnson [Wed, 2 Sep 2015 18:34:19 +0000 (13:34 -0500)]
sim: Add ability to break at specific kernel function
Adds a GDB callable function that sets a breakpoint at
the beginning of a kernel function.
Andreas Sandberg [Mon, 5 Oct 2015 18:13:23 +0000 (13:13 -0500)]
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
Steve Reinhardt [Fri, 2 Oct 2015 05:04:12 +0000 (01:04 -0400)]
stats: update EIO stats for snoop filter changes
Andreas Hansson [Thu, 1 Oct 2015 08:07:15 +0000 (04:07 -0400)]
config: Fix 'learning gem5' configs after SMT push
This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.
Curtis Dunham [Wed, 30 Sep 2015 20:21:55 +0000 (15:21 -0500)]
base: remove Trace::enabled flag
The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is
detected. Having 2 SMT threads share a TLB resulted in these not being
updated as required. This patch adds a thread context identifer to
assist in the invalidation of these variables.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
arm: SMT MPIDR Setting
Changes assignment of the MPIDR for multi-threaded systems only.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu: Add per-thread monitors
Adds per-thread address monitors to support FullSystem SMT.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
cores) caused failures due to the CPU id assignment logic. The comment
about thread assignment (worrying about core 0 not having tid 0) seems
not to be valid given that our configuration scripts initialize them in
order.
This removes that constraint so a heterogenously threaded sytem can work.
Joel Hestness [Tue, 29 Sep 2015 14:28:26 +0000 (09:28 -0500)]
ruby: Fix CacheMemory allocate leak
If a cache entry permission was previously set to NotPresent, but the entry was
not deleted, a following cache allocation can cause the entry to be leaked by
setting the entry pointer to a newly allocated entry. To eliminate this
possibility, check if the new entry is different from the old one, and if so,
delete the old one.
Joel Hestness [Tue, 29 Sep 2015 14:28:26 +0000 (09:28 -0500)]
arch, x86: Delete packet in IntDevice::recvResponse
IntDevice::recvResponse is called from two places in current mainline: (1) the
short circuit path of X86ISA::IntDevice::IntMasterPort::sendMessage for atomic
mode, and (2) the full request->response path to and from the x86 interrupts
device (finally called from MessageMasterPort::recvTimingResp). In the former
case, the packet was deleted correctly, but in the latter case, the packet and
request leak. To fix the leak, move request and packet deletion into IntDevice
inherited class implementations of recvResponse.
Joel Hestness [Tue, 29 Sep 2015 14:28:25 +0000 (09:28 -0500)]
ruby: RubyPort delete snoop requests
In RubyPort::ruby_eviction_callback, prior changes fixed a memory leak caused
by instantiating separate packets for each port that the eviction was forwarded
to. That change, however, left the instantiated request to also leak. Allocate
it on the stack to avoid the leak.
Joel Hestness [Tue, 29 Sep 2015 14:28:25 +0000 (09:28 -0500)]
ruby: Fix memory leak in AbstractController
Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.
Joel Hestness [Tue, 29 Sep 2015 14:25:29 +0000 (09:25 -0500)]
ruby: RubyMemoryControl delete requests
Changes to the RubyMemoryControl removed the dequeue function, which deleted
MemoryNode instances. This results in leaked MemoryNode instances. Correctly
delete these instances.
Joel Hestness [Tue, 29 Sep 2015 14:25:20 +0000 (09:25 -0500)]
syscall_emul: Bandage readlink /proc/self/exe
The recent changeset to readlink() to handle reading the /proc/self/exe link
introduces a number of problems. This patch fixes two:
1) Because readlink() called on /proc/self/exe now uses LiveProcess::progName()
to find the binary path, it will only get the zeroth parameter of the simulated
system command line. However, if a config script also specifies the process'
executable, the executable parameter is used to create the LiveProcess rather
than the zeroth command line parameter. Thus, the zeroth command line parameter
is not necessarily the correct path to the binary executing in the simulated
system. To fix this, add a LiveProcess data member, 'executable', which is
correctly set during instantiation and returned from progName().
2) If a config script allows a user to pass a relative path as the zeroth
simulated system command line parameter or process executable, readlink() will
incorrecly return a relative path when called on '/proc/self/exe'.
/proc/self/exe is always set to a full path, so running benchmarks can fail if
a relative path is returned. To fix this, clean up the handling of
LiveProcess::progName() within readlink() to get the full binary path.
NOTE: This patch still leaves the potential problem that host full path to the
binary bleeds into the simulated system, potentially causing the appearance of
non-deterministic simulated system execution.
Andreas Hansson [Fri, 25 Sep 2015 17:25:34 +0000 (13:25 -0400)]
mem: Add PacketInfo to be used for packet probe points
This patch fixes a use-after-delete issue in the packet probe points
by adding a PacketInfo struct to retain the key fields before passing
the packet onwards. We want to probe the packet after it is
successfully sent, but by that time the fields may be modified, and
the packet may even be deleted.
Amazingly enough the issue has gone undetected for months, and only
recently popped up in our regressions.
Andreas Hansson [Fri, 25 Sep 2015 11:27:03 +0000 (07:27 -0400)]
stats: Update stats to reflect snoop-filter changes
Andreas Hansson [Fri, 25 Sep 2015 11:26:58 +0000 (07:26 -0400)]
mem: Add check for block status on WriteLineReq fill
More checks to help with understanding of functionality.
Andreas Hansson [Fri, 25 Sep 2015 11:26:58 +0000 (07:26 -0400)]
mem: Fix WriteLineReq fill behaviour
This patch fixes issues in the interactions between deferred snoops
and WriteLineReq. More specifically, the patch addresses an issue
where deferred snoops caused assertion failures when being serviced on
the arrival of an InvalidateResp. The response packet was perceived to
be invalidating, when actually it is not for the cache that sent out
the original invalidation request.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Comment clean-up for the snoop filter
Merely fixing up some style issues and adding more comments.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Avoid adding and then removing empty snoop-filter items
This patch tidies up how we access the snoop filter for snoops, and
avoids adding items only to later remove them.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Only track snooping ports in the snoop filter
This patch changes the tracking of ports in the snoop filter to use
local dense port IDs so that we can have 64 snooping ports (rather
than crossbar slave ports). This is achieved by adding a simple
remapping vector that translates the actal port IDs into the local
slave IDs used in the SnoopMask.
Ultimately this patch allows us to scale to much larger systems
without introducing a hierarchy of crossbars.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add snoop filters to L2 crossbars, and check size
This patch adds a snoop filter to the L2XBar. For now we refrain from
globally adding a snoop filter to the SystemXBar, since the latter is
also used in systems without caches. In scenarios without caches the
snoop filter will not see any writeback/clean evicts from the CPU
ports, despite the fact that they are snooping. To avoid inadvertent
use of the snoop filter in these cases we leave it out for now.
A size check is added to the snoop filter, merely to ensure it does
not grow beyond the total capacity of the caches above it. The size
has to be set manually, and a value of 8 MByte is choosen as suitably
high default.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Store snoop filter lookup result to avoid second lookup
This patch introduces a private member storing the iterator from the
lookupRequest call, such that it can be re-used when the request
eventually finishes. The method previously called updateRequest is
renamed finishRequest to make it more clear that the two functions
must be called together.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add snoops for CleanEvicts and Writebacks in atomic mode
This patch mirrors the logic in timing mode which sends up snoops to
check for cached copies before sending CleanEvicts and Writebacks down
the memory hierarchy. In case there is a copy in a cache above,
discard CleanEvicts and set the BLOCK_CACHED flag in Writebacks so
that writebacks do not reset the cache residency bit in the snoop
filter below.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add CleanEvict and Writeback support to snoop filters
This patch adds the functionality to properly track CleanEvicts and
Writebacks in the snoop filter. Previously there were no CleanEvicts, and
Writebacks did not send up snoops to ensure there were no copies in
caches above. Hence a writeback could never erase an entry from the
snoop filter.
When a CleanEvict message reaches a snoop filter, it confirms that the
BLOCK_CACHED flag is not set and resets the bits corresponding to the
CleanEvict address and port it arrived on. If none of the other peer
caches have (or have requested) the block, the snoop filter forwards
the CleanEvict to lower levels of memory. In case of a Writeback
message, the snoop filter checks if the BLOCK_CACHED flag is not set
and only then resets the bits corresponding to the Writeback
address. If any of the other peer caches have (or has requested) the
same block, the snoop filter sets the BLOCK_CACHED flag in the
Writeback before forwarding it to lower levels of memory heirarachy.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add check for snooping ports in the snoop filter
This patch prevents the snoop filter from creating items for requests
originating from non-snooping ports. The allocation decision is thus
based both on the cacheability of the line, and the snooping status of
the source port. Ultimately we should check if the source of the
packet is caching, since also the CPU ports are snooping (but not
allocating). Thus, at the moment we rely on the snoop filter being
used together with caches.
The patch also transitions to use the Packet::getBlockAddr in
determining the line address.
Andreas Hansson [Fri, 25 Sep 2015 11:13:54 +0000 (07:13 -0400)]
mem: Make the coherent crossbar account for timing snoops
This patch introduces the concept of a snoop latency. Given the
requirement to snoop and forward packets in zero time (due to the
coherency mechanism), the latency is accounted for later.
On a snoop, we establish the latency, and later add it to the header
delay of the packet. To allow multiple caches to contribute to the
snoop latency, we use a separate variable in the packet, and then take
the maximum before adding it to the header delay.
Andreas Hansson [Fri, 25 Sep 2015 10:45:52 +0000 (06:45 -0400)]
mem: Do not include snoop-filter latency in crossbar occupancy
This patch ensures that the snoop-filter latency only contributes to
the packet latency, and not to the crossbar throughput/occupancy. In
essence we treat the snoop-filter lookup as pipelined.
Andreas Hansson [Fri, 25 Sep 2015 10:45:50 +0000 (06:45 -0400)]
util: Fix minor issues in DRAM sweep scripts
This patch fixes a few issues in the sweep scripts, bringing them
up-to-date with the latest memory configs and options.
Nilay Vaish [Thu, 24 Sep 2015 13:41:24 +0000 (08:41 -0500)]
ruby: simple network: refactor code
Drops an unused variable and marks three variables as const.
Nilay Vaish [Wed, 23 Sep 2015 16:23:11 +0000 (11:23 -0500)]
ruby: garnet: refactor code in network links
Nilay Vaish [Wed, 23 Sep 2015 16:23:10 +0000 (11:23 -0500)]
ruby: bloom filters: refactor code
Nilay Vaish [Wed, 23 Sep 2015 16:23:10 +0000 (11:23 -0500)]
ruby: abstract controller: mark some variables as const
Wendy Elsasser [Tue, 22 Sep 2015 18:17:53 +0000 (13:17 -0500)]
mem: Add initial HBM configurations
Created the following HBM configurations:
1) HBM gen1 (x128/CH), 2Gb die, 4H stack, 1Gbps, 8 channels
2) HBM gen2 (x64/PC), 8Gb die, 4H stack, 1Gbps, 16 pseudo-channels
The configuration values are based on:
- The HBM gen1 public JEDEC spec
- Publically released data from MemCon presentations
- Timing extrapolated from existing LPDDR configurations
Will adjust once specs become available.
Nilay Vaish [Fri, 18 Sep 2015 18:27:48 +0000 (13:27 -0500)]
ruby: garnet: mark some variables as const
Nilay Vaish [Fri, 18 Sep 2015 18:27:47 +0000 (13:27 -0500)]
ruby: print addresses in hex
Changeset
4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
Nilay Vaish [Fri, 18 Sep 2015 18:27:47 +0000 (13:27 -0500)]
ruby: slicc: derive DataMember class from Var instead of PairContainer
The DataMember class in Type.py was being derived from PairContainer. A
separate Var object was also created for the DataMember. This meant some
duplication of across the members of these two classes (Var and DataMember).
This patch changes DataMember from Var instead. There is no obvious reason to
derive from PairContainer which can only hold pairs, something that Var class
already supports. The only thing that DataMember has over Var is init_code,
which is being retained. This change would later on help in having pointers
in DataMembers.
Tony Gutierrez [Thu, 17 Sep 2015 18:00:33 +0000 (14:00 -0400)]
ruby: update WireBuffer API to match that of MessageBuffer
this patch updates the WireBuffer API to mirror the changes in revision 11111
Nilay Vaish [Thu, 17 Sep 2015 03:17:54 +0000 (22:17 -0500)]
stats: updates due to changes to MOESI_hammer
Lena Olson [Thu, 17 Sep 2015 01:18:40 +0000 (20:18 -0500)]
ruby: Add missing block deallocations in MOESI_hammer
Some blocks in MOESI hammer were not getting deallocated when they were set to
an idle state (e.g. by invalidate or other_getx/s messages). While
functionally correct, this caused some bad effects on performance, such as
blocks in I in the L1s getting sent to the L2 upon eviction, in turn evicting
valid blocks. Also, if a valid block was in LRU, that block could be evicted
rather than a block in I. This patch adds in the missing deallocations.
Committed by: Nilay Vaish<nilay@cs.wisc.edu>
Joe Gross [Wed, 16 Sep 2015 17:10:42 +0000 (13:10 -0400)]
ruby: fix message buffer init order
The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.
This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.
Nilay Vaish [Wed, 16 Sep 2015 16:59:57 +0000 (11:59 -0500)]
stats: slight changes to MOESI_CMP_token.
Due slight change to latency for the reissue table.
Nilay Vaish [Wed, 16 Sep 2015 16:59:56 +0000 (11:59 -0500)]
ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.
I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.
In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
Nilay Vaish [Wed, 16 Sep 2015 16:59:55 +0000 (11:59 -0500)]
ruby: remove unused function removeRequest()
Nilay Vaish [Wed, 16 Sep 2015 16:59:55 +0000 (11:59 -0500)]
ruby: sequencer: remove commented out function printProgress()
David Hashe [Wed, 16 Sep 2015 16:03:03 +0000 (12:03 -0400)]
ruby: rename System.{hh,cc} to RubySystem.{hh,cc}
The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.
Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.
In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.
However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.
The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
--HG--
rename : src/mem/ruby/system/System.cc => src/mem/ruby/system/RubySystem.cc
rename : src/mem/ruby/system/System.hh => src/mem/ruby/system/RubySystem.hh
Anthony Gutierrez [Wed, 16 Sep 2015 16:01:39 +0000 (12:01 -0400)]
slicc: export uint64_t instead of uint64
Jason Lowe-Power [Wed, 16 Sep 2015 14:35:36 +0000 (09:35 -0500)]
stats: files for regression tests for Learning gem5 scripts
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jason Lowe-Power [Wed, 16 Sep 2015 14:35:36 +0000 (09:35 -0500)]
tests: Add tests for the Learning gem5 scripts
These tests will ensure that Learning gem5 scripts are always up to date with
the changes in the mainline of gem5.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jason Lowe-Power [Wed, 16 Sep 2015 14:35:36 +0000 (09:35 -0500)]
config: Add configs scripts used in Learning gem5
Added a new directory in configs (learning_gem5) to hold the scripts that are
used in the book. See http://lowepower.com/jason/learning_gem5/ for a working
copy. For now, only the scripts in Part 1: Getting started with gem5
have been added. A separate patch adds tests for these scripts.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 15 Sep 2015 13:14:09 +0000 (08:14 -0500)]
stats: updates due to recent changesets including
d0934b57735a
Palle Lyckegaard [Tue, 15 Sep 2015 13:14:07 +0000 (08:14 -0500)]
sparc: writing to tick_cmpr should not cause a panic
This register is writable according to UA2005
Tried to boot NetBSD which starts the kernel by writing to the tick_cmpr
register. Without the patch gem5 crashes with a panic. With the patch NetBSD
starts to boot normally (although sun4v support in NetBSD is not complete yet)
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Dongxue Zhang [Tue, 15 Sep 2015 13:14:07 +0000 (08:14 -0500)]
dev: IDE Disk: Handle bad IDE image size
Handle bad IDE disk image size 0. When image size is 0, gem5 will cause an
exception with log "Floating point exception (core dumped)".
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Abdul Mutaal Ahmad [Tue, 15 Sep 2015 13:14:07 +0000 (08:14 -0500)]
misc: Bugfix for Freezing Terminal in SystemC Simulation
If the terminal was used in the SystemC or TLM simulations the simulation gets
in a deadlock state. This is because of the Event queue gets locked while
servicing the async events leading to event queue deadlock. This was solved by
locking the queue at the beginning of service of async events.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Abdul Mutaal Ahmad [Tue, 15 Sep 2015 13:14:07 +0000 (08:14 -0500)]
misc: Bugfix in TLM integration regarding CleanEvict Command
The CleanEvict command was not considered in /util/tlm/sc_port.cc this could
lead to a simulator crash. This issue is solved by ignoring this special
command type.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andrew Lukefahr [Tue, 15 Sep 2015 13:14:07 +0000 (08:14 -0500)]
cpu: pred: Local Predictor Reset in Tournament Predictor
When a branch gets squashed, it's speculative branch predictor state should get
rolled back in squash(). However, only the globalHistory state was being
rolled back. This patch adds (at least some) support for rolling back the
local predictor state also.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Hongil Yoon [Tue, 15 Sep 2015 13:14:06 +0000 (08:14 -0500)]
cpu, o3: consider split requests for LSQ checksnoop operations
This patch enables instructions in LSQ to track two physical addresses for
corresponding two split requests. Later, the information is used in
checksnoop() to search for/invalidate the corresponding LD instructions.
The current implementation has kept track of only the physical address that is
referenced by the first split request. Thus, for checksnoop(), the line
accessed by the second request has not been considered, causing potential
correctness issues.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Mon, 14 Sep 2015 15:14:50 +0000 (10:14 -0500)]
ruby: topology: refactor code.
Nilay Vaish [Mon, 14 Sep 2015 15:04:55 +0000 (10:04 -0500)]
ruby: slicc: remove member buffer_expr from Var class
This was added by changeset
51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.
Nilay Vaish [Sat, 12 Sep 2015 21:23:47 +0000 (16:23 -0500)]
Nilay Vaish [Sat, 12 Sep 2015 21:16:17 +0000 (16:16 -0500)]
ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer(). This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.
Nilay Vaish [Sat, 12 Sep 2015 21:16:03 +0000 (16:16 -0500)]
ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:
a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.
b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.
Andreas Sandberg [Fri, 11 Sep 2015 14:56:09 +0000 (15:56 +0100)]
dev: Add an underrun statistic to the HDLCD controller
Add a stat that counts buffer underruns in the HDLCD controller. The
stat counts at most one underrun per frame since the controller aborts
the current frame if it underruns.
Andreas Sandberg [Fri, 11 Sep 2015 14:55:46 +0000 (15:55 +0100)]
dev, arm: Rewrite the HDLCD controller
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:
* Broken/missing interrupt support (VSync, underrun, DMA end)
* Fragile resolution changes (changing resolutions used
to cause assertion errors).
* Support for resolutions with a width that isn't divisible by 32.
* The pixel clock can now be set dynamically.
This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
Nilay Vaish [Wed, 9 Sep 2015 00:32:04 +0000 (19:32 -0500)]
ruby: slicc: remove nextLineHack from Type.py
Nilay Vaish [Mon, 7 Sep 2015 04:11:11 +0000 (23:11 -0500)]
config: allow ruby to be used with Minor CPU
Nilay Vaish [Sat, 5 Sep 2015 14:35:39 +0000 (09:35 -0500)]
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
Nilay Vaish [Sat, 5 Sep 2015 14:35:31 +0000 (09:35 -0500)]
ruby: adds set and way indices to AbstractCacheEntry