powerpc: Restore bootstrap for Darwin.

Darwin has signed chars and the fields in the insn_data
struct are const char, which leads to the fail.

gcc/ChangeLog:

* config/rs6000/rs6000-call.c (mma_init_builtins): Cast
the insn_data n_operands value to unsigned.

fortran: Fix ICE when 'if' clause used with 'target parallel' (PR95869)

2020-06-25  Tobias Burnus  <tobias@codesourcery.com>
    Kwok Cheung Yeung  <kcy@codesourery.com>

gcc/fortran/

PR fortran/95869
* trans-openmp.c (gfc_trans_omp_target): Use correct scoping block.

gcc/testsuite/

PR fortran/95869
* gfortran.dg/gomp/combined-if.f90 (test_target_parallel): Re-enable.
* gfortran.dg/gomp/pr95869.f90: New.

fortran: Apply if clause to all sub-constructs in combined OpenMP constructs

The unmodified 'if' clause should be applied to all the sub-constructs that
accept an 'if' clause in a combined OpenMP construct, and not just to the
'parallel' sub-construct.

2020-06-25  Kwok Cheung Yeung  <kcy@codesourcery.com>

gcc/fortran/

* trans-openmp.c (gfc_split_omp_clauses): Add if clause
to target and simd sub-constructs.

gcc/testsuite/

* gfortran.dg/gomp/combined-if.f90: New.

Reviewed-by: Jakub Jelinek <jakub@redhat.com>

Always use SLP vector defs to determine insertion place

With the last vectorizable_shift patch we can now always use the
SLP vector defs to determine the vectorized stmt insertion place,
paving the way for a "verifier" for pending restructuring and
BB vectorization of reductions and other live stmts.

2020-06-25  Richard Biener  <rguenther@suse.de>

* tree-vect-slp.c (vect_schedule_slp_instance): Always use
vector defs to determine insertion place.

x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT

CLWB isn't supported on Ice Lake client.  But Ice Lake server and Tiger
Lake support it.  Move PTA_CLWB to PTA_ICELAKE_SERVER and PTA_TIGERLAKE.

PR target/95874
* config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
(PTA_ICELAKE_SERVER): Add PTA_CLWB.
(PTA_TIGERLAKE): Add PTA_CLWB.

tree-optimization/95866 - avoid using scalar ops for vectorized shift

This avoids using the original scalar SSA operand when vectorizing
a shift with a vectorized shift operand where we know all vector
components have the same value and thus we can use a vector by
scalar shift.  Using the scalar SSA operand causes a possibly
long chain of scalar computation to be retained so it's better
to simply extract lane zero from the available vectorized shift
operand.

2020-06-25  Richard Biener  <rguenther@suse.de>

PR tree-optimization/95866
* tree-vect-stmts.c (vectorizable_shift): Reject incompatible
vectorized shift operands.  For scalar shifts use lane zero
of a vectorized shift operand.

* gcc.dg/vect/bb-slp-pr95866.c: New testcase.

gcov-tool: fix merge operation for summary

libgcc/ChangeLog:

* libgcov-driver.c (merge_summary): Remove function as its name
is misleading and doing something different.
(dump_one_gcov): Add ATTRIBUTE_UNUSED for 2 args. Take read summary
in gcov-tool.
* libgcov-util.c (curr_object_summary): Remove.
(read_gcda_file): Remove unused curr_object_summary.
(gcov_merge): Merge summaries.
* libgcov.h: Add summary argument for gcov_info struct.

VEC_COND_EXPR: clean up first argument

gcc/ChangeLog:

PR tree-optimization/95745
PR middle-end/95830
* gimple-isel.cc (gimple_expand_vec_cond_exprs): Delete dead
SSA_NAMEs used as the first argument of a VEC_COND_EXPR.  Always
return 0.
* tree-vect-generic.c (expand_vector_condition): Remove dead
SSA_NAMEs used as the first argument of a VEC_COND_EXPR.

Daily bump.

[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin

Hi,
  Fix codegen for builtin vec_pack_to_short_fp32.  This includes adding
a define_insn for xvcvsphp, and adding a new define_expand for
convert_4f32_8f16.

2020-06-24  Will Schmidt  <will_schmidt@vnet.ibm.com>

PR target/94954

gcc
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
* config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec.
(convert_4f32_8f16): New define_expand
* config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define
and overload.
* config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New
overloaded builtin entry.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec.
(vsx_xvcvsphp): New define_insn.

gcc/testsuite
* gcc.target/powerpc/builtins-1-p9-runnable.c: Update.

outputs.exp: conditionals for split-dwarf and lto plugin

This patch introduces support for conditionals (and expr) expansions
to file lists in proc outest in outputs.exp.

The conditionals machinery is now used to guard files that are only
created by the LTO plugin, or when not using the LTO plugin.

It is also used to avoid special-casing .dwo files: the condition of
when they're expected is now encoded in the list.

Furthermore, the -g flag, that used to be specified along with
$gsplit_dwarf, is now moved into $gsplit_dwarf, so that we don't
compile with -g if -gsplit-dwarf is not needed.  This avoids having to
deal with .dSYM directories.

Further removing special cases, $aout is now dealt with in a more
general way, using expr to perform variable/string expansion.

for  gcc/testsuite/ChangeLog

PR testsuite/95416
PR testsuite/95577
* gcc.misc-tests/outputs.exp (gsplit_dwarf): Move -g into it.
(outest): Introduce conditionals and string/variable/expr
expansion.  Drop special-casing of $aout and .dwo.
(gspd): New conditional.  Guard all .dwo files with it.
(ltop): New conditional.  Guard files created by the LTO
plugin with it.  Guard files created by fat LTO compilation
with its negation.  Add a few -fno-use-linker-plugin tests
guarded by it.

c++: Handle bad pack expansion in base list. [PR96752]

This fixes PR95672 by adding the missing TYPE_PACK_EXPANSION case in
cxx_incomplete_type_diagnostic in order to avoid ICEs on diagnosing
incomplete template pack expansion cases.

Tested on powerpc64le-unknown-linux-gnu.

gcc/cp/ChangeLog:

PR c++/95672
* typeck2.c (cxx_incomplete_type_diagnostic): Add missing
TYPE_EXPANSION_PACK check for diagnosing incomplete types in
cxx_incomplete_type_diagnostic.

gcc/testsuite/ChangeLog:

PR c++/95672
* g++.dg/template/pr95672.C: New test.

Signed-off-by: Nicholas Krause <xerofoify@gmail.com>

coroutines: Copy attributes to the outlined functions [PR95518,PR95813]

We had omitted the copying of function attributes, we now copy
the used, alignment, section values from the original decal and
the complete set of function attributes.  It is likely that
some function attributes don't really make sense for coroutines,
but that can be disgnosed separately. Also mark the outlined
functions as artificial, since they are; some diagnostic
processing tests this.

gcc/cp/ChangeLog:

PR c++/95518
PR c++/95813
* coroutines.cc (act_des_fn): Copy function
attributes onto the outlined coroutine helpers.

gcc/testsuite/ChangeLog:

PR c++/95518
PR c++/95813
* g++.dg/coroutines/pr95518.C: New test.
* g++.dg/coroutines/pr95813.C: New test.

coroutines: Update tests for get-return-object errors.

We updated the handling of the errors for cases when the
ramp return cannot be constructed from the user's provided
get-return-object method.  This updates the testcases to
cover this.

gcc/testsuite/ChangeLog:

* g++.dg/coroutines/void-gro-non-class-coro.C: Moved to...
* g++.dg/coroutines/coro-bad-gro-01-void-gro-non-class-coro.C: ...here.
* g++.dg/coroutines/coro-bad-gro-00-class-gro-scalar-return.C: New test.

c++: Simplify build_over_call a bit.

It occurred to me that if we're looking up the defining base within the
conversion_path binfo, we could use the result for the conversion as well
instead of doing two separate conversions.

gcc/cp/ChangeLog:

* call.c (build_over_call): Only call build_base_path once.

c++: Fix ICE with using and virtual function. [PR95719]

conversion_path points to the base where we found the using-declaration, not
where the function is actually a member; look up the actual base.  And then
maybe look back to the derived class if the base is primary.

gcc/cp/ChangeLog:

PR c++/95719
* call.c (build_over_call): Look up the overrider in base_binfo.
* class.c (lookup_vfn_in_binfo): Look through BINFO_PRIMARY_P.

gcc/testsuite/ChangeLog:

PR c++/95719
* g++.dg/tree-ssa/final4.C: New test.

simplify-rtx: Simplify rotates by zero

2020-06-24  Roger Sayle  <roger@nextmovesoftware.com>
    Segher Boessenkool  <segher@kernel.crashing.org>

* simplify-rtx.c (simplify_unary_operation_1): Simplify rotates by 0.

simplify-rtx: Parity of parity is parity

2020-06-24  Roger Sayle  <roger@nextmovesoftware.com>

* simplify-rtx.c (simplify_unary_operation_1): Simplify
(parity (parity x)) as (parity x), i.e. PARITY is idempotent.

PR fortran/95827 - Buffer overflows with submodules and coarrays

With submodules and coarrays, name mangling results in long internal
symbols.  Enlarge internal buffer.

gcc/fortran/
PR fortran/95827
* iresolve.c (gfc_get_string): Enlarge internal buffer used in
generating the mangled name.

tree-optimization/95866 - avoid vectorizing uniform SLP subgraphs

This avoids vectorizing SLP subgraphs that just compute uniform
operations on all-same operands.  That fixes the less interesting
(but most embarrasing) part of the testcase in the PR.  On the
way it also fixed a missing matches[0] reset in the last
refactoring touching that place.

2020-06-24  Richard Biener  <rguenther@suse.de>

PR tree-optimization/95866
* tree-vect-slp.c (vect_slp_tree_uniform_p): New.
(vect_build_slp_tree_2): Properly reset matches[0],
ignore uniform constants.

* gcc.target/i386/pr95866-1.c: New testcase.

Make contrib/download_prerequisites work on AIX and OpenBSD

contrib/ChangeLog:

2020-06-11  Ilya Leoshkevich  <iii@linux.ibm.com>

* download_prerequisites: Support AIX and OpenBSD unames.
Pipe `{gzip,bzip2} -d` to `tar -xf -`.

x86: Remove brand ID check for Intel processors

Brand ID was a feature that briefly existed in some Pentium III and
Pentium 4 CPUs.  The CPUs that had non-zero brand ID still have had
valid family/model.  Brand ID just gives a marketing name for the CPU.
Remove the extra code for brand ID check.

gcc/

PR target/95660
* common/config/i386/cpuinfo.h (get_intel_cpu): Remove brand_id.
(cpu_indicator_init): Likewise.
* config/i386/driver-i386.c (host_detect_local_cpu): Updated.

gcc/testsuite/

PR target/95660
* gcc.target/i386/builtin_target.c (check_detailed): Updated.

x86: Add Cooper Lake detection with AVX512BF16

All Sky Lake family processors have the same CPUID model number, 0x55.
The differences are Cascade Lake has AVX512VNNI and Cooper Lake has
AVX512VNNI + AVX512BF16.  Check AVX512BF16 for Cooper Lake.

PR target/95774
* common/config/i386/cpuinfo.h (get_intel_cpu): Add Cooper Lake
detection with AVX512BF16.

x86: Share _isa_names_table and use cpuinfo.h

Both driver-i386.c and libgcc use CPUID to detect the processor name
as well as available ISAs.  To detect the same processor or ISAs, the
same detection logic is duplicated in 2 places.  Sometimes only one place
was up to date or got it right.  Sometimes both places got it wrong.

1. Add common/config/i386/i386-isas.h to define _isa_names_table.
2. Use isa_names_table to auto-generate ISA command-line options.
3. Use isa_names_table to auto-generate __builtin_cpu_supports tests.
4. Use common/config/i386/cpuinfo.h to check available ISAs and detect
newer Intel processors in driver-i386.c and builtin_target.c.
5. Detection of AMD processors and older processors in driver-i386.c is
unchanged.

gcc/

PR target/95843
* common/config/i386/i386-isas.h: New file.  Extracted from
gcc/config/i386/i386-builtins.c.
(_isa_names_table): Add option.
(ISA_NAMES_TABLE_START): New.
(ISA_NAMES_TABLE_END): Likewise.
(ISA_NAMES_TABLE_ENTRY): Likewise.
(isa_names_table): Defined with ISA_NAMES_TABLE_START,
ISA_NAMES_TABLE_END and ISA_NAMES_TABLE_ENTRY.  Add more ISAs
from enum processor_features.
* config/i386/driver-i386.c: Include
"common/config/i386/cpuinfo.h" and
"common/config/i386/i386-isas.h".
(has_feature): New macro.
(host_detect_local_cpu): Call cpu_indicator_init to get CPU
features.  Use has_feature to detect processor features.  Call
Call get_intel_cpu to get the newer Intel CPU name.  Use
isa_names_table to generate command-line options.
* config/i386/i386-builtins.c: Include
"common/config/i386/i386-isas.h".
(_arch_names_table): Removed.
(isa_names_table): Likewise.

gcc/testsuite/

PR target/95843
* gcc.target/i386/builtin_target.c: Include <stdlib.h>,
../../../common/config/i386/i386-cpuinfo.h and
../../../common/config/i386/cpuinfo.h.
(check_amd_cpu_model): Removed.
(check_intel_cpu_model): Likewise,
(CHECK___builtin_cpu_is): New.
(gcc_assert): New.  Defined as assert.
(gcc_unreachable): New.  Defined as abort.
(inline): New.  Defined as empty.
(ISA_NAMES_TABLE_START): Likewise.
(ISA_NAMES_TABLE_END): Likewise.
(ISA_NAMES_TABLE_ENTRY): New.
(check_features): Include
"../../../common/config/i386/i386-isas.h".
(check_detailed): Call cpu_indicator_init.  Always call
check_features.  Call get_amd_cpu instead of check_amd_cpu_model.
Call get_intel_cpu instead of check_intel_cpu_model.

Fix typo in ChangeLog

x86: Move cpuinfo.h from libgcc to common/config/i386

Both x86 backend and libgcc define enum processor_features.  libgcc sets
enum processor_feature and x86 backend checks enum processor_feature.
They are very easy out of sync and it has happened multiple times in the
past.

1. Move cpuinfo.h from libgcc to common/config/i386 so that we can share
the same enum processor_features in x86 backend and libgcc.
2. Change __cpu_features2 to an array to support more processor features.
3. Add more processor features to enum processor_features.

gcc/

PR target/95259
* common/config/i386/cpuinfo.h: New file.
(__processor_model): Moved from libgcc/config/i386/cpuinfo.h.
(__processor_model2): New.
(CHECK___builtin_cpu_is): New.  Defined as empty if not defined.
(has_cpu_feature): New function.
(set_cpu_feature): Likewise.
(get_amd_cpu): Moved from libgcc/config/i386/cpuinfo.c.  Use
CHECK___builtin_cpu_is.  Return AMD CPU name.
(get_intel_cpu): Moved from libgcc/config/i386/cpuinfo.c.  Use
Use CHECK___builtin_cpu_is.  Return Intel CPU name.
(get_available_features): Moved from libgcc/config/i386/cpuinfo.c.
Also check FEATURE_3DNOW, FEATURE_3DNOWP, FEATURE_ADX,
FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT, FEATURE_CLWB,
FEATURE_CLZERO, FEATURE_CMPXCHG16B, FEATURE_CMPXCHG8B,
FEATURE_ENQCMD, FEATURE_F16C, FEATURE_FSGSBASE, FEATURE_FXSAVE,
FEATURE_HLE, FEATURE_IBT, FEATURE_LAHF_LM, FEATURE_LM,
FEATURE_LWP, FEATURE_LZCNT, FEATURE_MOVBE, FEATURE_MOVDIR64B,
FEATURE_MOVDIRI, FEATURE_MWAITX, FEATURE_OSXSAVE,
FEATURE_PCONFIG, FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW,
FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED,
FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA,
FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES,
FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC,
FEATURE_XSAVEOPT and FEATURE_XSAVES
(cpu_indicator_init): Moved from libgcc/config/i386/cpuinfo.c.
Also update cpu_model2.
* common/config/i386/i386-cpuinfo.h (processor_vendor): Add
Add VENDOR_CENTAUR, VENDOR_CYRIX and VENDOR_NSC.
(processor_features): Moved from gcc/config/i386/i386-builtins.c.
Renamed F_XXX to FEATURE_XXX.  Add FEATURE_3DNOW, FEATURE_3DNOWP,
FEATURE_ADX, FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT,
FEATURE_CLWB, FEATURE_CLZERO, FEATURE_CMPXCHG16B,
FEATURE_CMPXCHG8B, FEATURE_ENQCMD, FEATURE_F16C,
FEATURE_FSGSBASE, FEATURE_FXSAVE, FEATURE_HLE, FEATURE_IBT,
FEATURE_LAHF_LM, FEATURE_LM, FEATURE_LWP, FEATURE_LZCNT,
FEATURE_MOVBE, FEATURE_MOVDIR64B, FEATURE_MOVDIRI,
FEATURE_MWAITX, FEATURE_OSXSAVE, FEATURE_PCONFIG,
FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW,
FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED,
FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA,
FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES,
FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC,
FEATURE_XSAVEOPT, FEATURE_XSAVES and CPU_FEATURE_MAX.
(SIZE_OF_CPU_FEATURES): New.
* config/i386/i386-builtins.c (processor_features): Removed.
(isa_names_table): Replace F_XXX with FEATURE_XXX.
(fold_builtin_cpu): Change __cpu_features2 to an array.

libgcc/

PR target/95259
* config/i386/cpuinfo.c: Don't include "cpuinfo.h".  Include
"common/config/i386/i386-cpuinfo.h" and
"common/config/i386/cpuinfo.h".
(__cpu_features2): Changed to array.
(get_amd_cpu): Removed.
(get_intel_cpu): Likewise.
(get_available_features): Likewise.
(__cpu_indicator_init): Call cpu_indicator_init.
* config/i386/cpuinfo.h: Removed.

libstdc++: Fix std::from_chars to ignore leading zeros in base 2

The parser for binary numbers returned an error if the entire string
contains more digits than the result type. Leading zeros should be
ignored.

libstdc++-v3/ChangeLog:

* include/std/charconv (__from_chars_binary): Ignore leading zeros.
* testsuite/20_util/from_chars/1.cc: Check "0x1" for all bases,
not just 10 and 16.
* testsuite/20_util/from_chars/3.cc: New test.

libstdc++: Fix warnings with -Wsystem-headers

libstdc++-v3/ChangeLog:

* include/bits/stl_algobase.h (__find_if): Add FALLTHRU markers.
* include/std/charconv (__detail::__to_chars): Avoid
-Wsign-compare warning.

libstdc++: Fix std::to_chars buffer overflow (PR 95851)

The __detail::__to_chars_2 function assumes it won't be called with zero
values. However, when the output buffer is empty the caller doesn't
handle zero values correctly, and calls __to_chars_2 with a zero value,
resulting in an overflow of the empty buffer.

The __detail::__to_chars_i function should just return immediately for
an empty buffer, and otherwise ensure zero values are handled properly.

libstdc++-v3/ChangeLog:

PR libstdc++/95851
* include/std/charconv (__to_chars_i): Check for zero-sized
buffer unconditionally.
* testsuite/20_util/to_chars/95851.cc: New test.

x86: Fold arch_names_table into processor_alias_table

In i386-builtins.c, arch_names_table is used to to map architecture name
string to internal model.  A switch statement is used to map internal
processor name to architecture name string and internal priority.

model and priority are added to processor_alias_table so that a single
entry contains architecture name string, internal processor name,
internal model and internal priority.  6 entries are appended for
i386-builtins.c, which have special architecture name strings: amd,
amdfam10h, amdfam15h, amdfam17h, shanghai and istanbul, and pta_size is
adjusted to exclude them.  Entries which are not used by i386-builtins.c
have internal model 0.  P_PROC_DYNAMIC is added to internal priority to
make entries with dynamic architecture name string or priority.

PR target/95842
* common/config/i386/i386-common.c (processor_alias_table): Add
processor model and priority to each entry.
(pta_size): Updated with -6.
(num_arch_names): New.
* common/config/i386/i386-cpuinfo.h: New file.
* config/i386/i386-builtins.c (feature_priority): Removed.
(processor_model): Likewise.
(_arch_names_table): Likewise.
(arch_names_table): Likewise.
(_isa_names_table): Replace P_ZERO with P_NONE.
(get_builtin_code_for_version): Replace P_ZERO with P_NONE.  Use
processor_alias_table.
(fold_builtin_cpu): Replace arch_names_table with
processor_alias_table.
* config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h".
(pta): Add model and priority.
(num_arch_names): New.

emit SLP vectorized loads earlier

This makes sure to emit SLP vectorized loads where the first scalar
load is.  This makes SLP dependence checking more powerful because
hoisting loads can use TBAA and it increases the freedom for
vector placement when there are constraints from live lanes.

Vectorized shifts block inserting vectorized stmts always after
vectorized defs because it ends up using the original scalar
operand even when the SLP graph indicates the shift operand
is vectorized (and we actually emit and cost those stmts).

vect_slp_analyze_and_verify_node_alignment shows we need alignment
for too many places, this is a temporary solution and my plan
is to have a single meta-info for a dataref group instead
(also getting rid of DR_GROUP_FIRST/NEXT_ELEMENT).

2020-06-24  Richard Biener  <rguenther@suse.de>

* tree-vectorizer.h (vect_find_first_scalar_stmt_in_slp):
Declare.
* tree-vect-data-refs.c (vect_preserves_scalar_order_p):
Simplify for new position of vectorized SLP loads.
(vect_slp_analyze_node_dependences): Adjust for it.
(vect_slp_analyze_and_verify_node_alignment): Compute alignment
for the first stmts dataref.
* tree-vect-slp.c (vect_find_first_scalar_stmt_in_slp): New.
(vect_schedule_slp_instance): Emit loads before the
first scalar stmt.
* tree-vect-stmts.c (vectorizable_load): Do what the comment
says and use vect_find_first_scalar_stmt_in_slp.

tree-optimization/95856 fix vect_stmt_dominates_stmt_p at BB region boundary

The following adjusts vect_stmt_dominates_stmt_p to honor out-of-region
stmts we run into which have UID -1u.

2020-06-24  Richard Biener  <rguenther@suse.de>

PR tree-optimization/95856
* tree-vectorizer.c (vect_stmt_dominates_stmt_p): Honor
region marker -1u.

* gcc.dg/vect/pr95856.c: New testcase.

fold-const: Fix A <= 0 ? A : -A folding [PR95810]

We folded A <= 0 ? A : -A into -ABS (A), which is for signed integral types
incorrect - can invoke on INT_MIN UB twice, once on ABS and once on its
negation.

The following patch fixes it by instead folding it to (type)-ABSU (A).

2020-06-24  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/95810
* fold-const.c (fold_cond_expr_with_comparison): Optimize
A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A).

* gcc.dg/ubsan/pr95810.c: New test.

openmp: Fix two pastos in non-rect loop OpenMP lowering.

2020-06-24  Jakub Jelinek  <jakub@redhat.com>

* omp-low.c (lower_omp_for): Fix two pastos.

options: Properly compare string options.

gcc/ChangeLog:

* optc-save-gen.awk: Compare string options in cl_optimization_compare
by strcmp.

Daily bump.

Allow --with-cpu=power10

Update config.gcc so that we can use --with-cpu=power10.
Also remove "future" from the 64-bit check as Segher suggests.

* config.gcc: Identify power10 as a 64-bit processor and as valid
for --with-cpu and --with-tune.

c++: Improve CTAD for aggregates [PR93976]

P2082R1 adjusted the rules for class template argument deduction for an
aggregate to better handle arrays and pack expansions.

gcc/cp/ChangeLog:

PR c++/93976
Implement C++20 P2082R1, Fixing CTAD for aggregates.
* cp-tree.h (TPARMS_PRIMARY_TEMPLATE): Split out from...
(DECL_PRIMARY_TEMPLATE): ...here.
(builtin_guide_p): Declare.
* decl.c (reshape_init_class): Handle bases of a template.
(reshape_init_r): An array with dependent bound takes a single
initializer.
* pt.c (tsubst_default_argument): Shortcut {}.
(unify_pack_expansion): Allow omitted arguments to trailing pack.
(builtin_guide_p): New.
(collect_ctor_idx_types): Give a trailing pack a {} default
argument.  Handle arrays better.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/class-deduction-aggr3.C: New test.
* g++.dg/cpp2a/class-deduction-aggr4.C: New test.

Make forall statement in testsuite conforming.

The recent patch for dependency checking introduced one failing test
case for pointer assignments in a forall statement.  This test case
was invalid because of an interdependency in a forall statement.
This patch fixes that by removing that dependency.

gcc/testsuite/ChangeLog:

* gfortran.fortran-torture/execute/forall_5.f90: Make forall
statement conforming.

coroutines: Add a cleanup expression for g-r-o when needed [PR95477].

The PR reports that we fail to destroy the object initially created from
the get-return-object call.  Fixed by adding a cleanup when the DTOR is
non-trivial.  In addition, to meet the specific wording that the call to
get_return_object creates the glvalue for the return, we must construct
that in-place in the return object to avoid a second copy/move CTOR.

gcc/cp/ChangeLog:

PR c++/95477
* coroutines.cc (morph_fn_to_coro): Apply a cleanup to
the get return object when the DTOR is non-trivial.

gcc/testsuite/ChangeLog:

PR c++/95477
* g++.dg/coroutines/pr95477.C: New test.
* g++.dg/coroutines/void-gro-non-class-coro.C: New test.

build: Change conditional include and empty.mk to -include in Makefiles

GNU Make supports "-include" keyword to prevent warnings and errors due to
inclusion of non-existent files.  This patch changes gcc/ and libgcc/ to use
"-include" in place of the historical conditional inclusion and use of
empty.mk work-arounds.

gcc/ChangeLog

2020-06-23  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.in (LANG_MAKEFRAGS): Same.
(tmake_file): Use -include.
(xmake_file): Same.

libgcc/ChangeLog

2020-06-23  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.in: Remove uses of empty.mk. Use -include.
* config/avr/t-avr: Use -include.
* empty.mk: Delete.

libgcc/config/avr/libf7/ChangeLog

2020-06-23  David Edelsohn  <dje.gcc@gmail.com>

* t-libf7: Same.

libiberty, include: add bsearch_r

libctf wants a bsearch that takes a void * arg pointer to avoid a
nonportable use of __thread.

bsearch_r is required, not optional, at this point because as far as I
can see this obvious-sounding function is not implemented by anyone's
libc.  We can easily move it to AC_LIBOBJ later if it proves necessary
to do so.

include/
* libiberty.h (bsearch_r): New.
libiberty/
* bsearch_r.c: New file.
* Makefile.in (CFILES): Add bsearch_r.c.
(REQUIRED_OFILES): Add bsearch_r.o.
* functions.texi: Regenerate.

Remove superfluous space

gcc/ada/ChangeLog:
* gcc-interface/utils2.c (build_binary_op): Remove space.

Fix memory corruption with vector and variant record

The problem is that Has_Constrained_Partial_View must be tested on the
base type of the designated type of an allocator.

gcc/ada/ChangeLog:
* gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks.
Call Has_Constrained_Partial_View on base type of designated type.

Emit debug info for integral variables first

This makes it possible for global dynamic types to reference the DIE of
these integral variables.

gcc/ada/ChangeLog:
* gcc-interface/utils.c (gnat_write_global_declarations): Output
integral global variables first and the imported functions later.

Minor tweak to elaborate_expression_1

gcc/ada/ChangeLog:
* gcc-interface/decl.c (elaborate_expression_1): When GNAT encodings
are not used, do not create a variable for debug info purposes if
the expression is itself a user-declared variable.

Streamline implementation of renaming in gigi

The main changes are 1) the bulk of the implementation is put back entirely
in gnat_to_gnu_entity and 2) the handling of lvalues is unified, i.e. it no
longer depends on the Materialize_Entity flag being present on the entity.

gcc/ada/ChangeLog:
* gcc-interface/ada-tree.h (DECL_RENAMED_OBJECT): Delete.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Always use
the stabilized reference directly for renaming and create a variable
pointing to it separately if requested.
* gcc-interface/misc.c (gnat_print_decl): Adjust for deletion.
* gcc-interface/trans.c (Identifier_to_gnu): Likewise.
(gnat_to_gnu) <N_Object_Renaming_Declaration>:
Do not deal with side-effects here.
<N_Exception_Renaming_Declaration>: Likewise.

Minor cleanup in elaborate_expression

gcc/ada/ChangeLog:
* gcc-interface/decl.c (elaborate_expression): Replace calls to
Is_OK_Static_Expression with Compile_Time_Known_Value.

Emit user subtypes with -fgnat-encodings=minimal

This changes the compiler to emit debug info for user-defined subtypes
with -fgnat-encodings=minimal, as they might be needed by the debugger.

gcc/ada/ChangeLog:
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Record_Subtype>: Set
debug type to the base type and only if the subtype is artificial.

Remove unintended checkin

2020-06-23  Michael Meissner  <meissner@linux.ibm.com>

* REVISION: Delete file meant for a private branch.

Minor adjustment in assignment case

gcc/ada/ChangeLog:
* gcc-interface/trans.c (gnat_to_gnu) <N_Assignment_Statement>: Do
not test Is_Bit_Packed_Array in the memset path.

arm: PR target/95646: Do not clobber callee saved registers with CMSE

As reported in bugzilla when the -mcmse option is used while compiling for size
(-Os) with a thumb-1 target the generated code will clear the registers r7-r10.
These however are callee saved and should be preserved accross ABI boundaries.
The reason this happens is because these registers are made "fixed" when
optimising for size with Thumb-1 in a way to make sure they are not used, as
pushing and popping hi-registers requires extra moves to and from LO_REGS.

To fix this, this patch uses 'callee_saved_reg_p', which accounts for this
optimisation, instead of 'call_used_or_fixed_reg_p'. Be aware of
'callee_saved_reg_p''s definition, as it does still take call used registers
into account, which aren't callee_saved in my opinion, so it is a rather
misnoemer, works in our advantage here though as it does exactly what we need.

Regression tested on arm-none-eabi.

Is this OK for trunk? (Will eventually backport to previous versions if stable.)

gcc/ChangeLog:
2020-06-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR target/95646
* config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use
'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'.

gcc/testsuite/ChangeLog:
2020-06-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR target/95646
* gcc.target/arm/pr95646.c: New test.

libstdc++: Adjust std::from_chars negative tests

Also test with an enumeration type. Move the dg-error directives outside
the #if block, because DejaGnu would process them whether or not wchar_t
support is present.

libstdc++-v3/ChangeLog:

* testsuite/20_util/from_chars/1_c++20_neg.cc: Check enumeration
type.
* testsuite/20_util/from_chars/1_neg.cc: Likewise. Move dg-error
directives outside preprocessor condition.

handle dumpbase in offloading, adjust testsuite

Pass dumpbase on to mkoffloads and their offload-target compiler runs,
using different suffixes for different offloading targets.
Obey -save-temps in naming temporary files while at that.

Adjust the testsuite offload dump scanning machinery to look for dump
files named under the new conventions, iterating internally over all
configured offload targets, or recognizing libgomp's testsuite's own
iteration.

for  gcc/ChangeLog

* collect-utils.h (dumppfx): New.
* collect-utils.c (dumppfx): Likewise.
* lto-wrapper.c (run_gcc): Set global dumppfx.
(compile_offload_image): Pass a -dumpbase on to mkoffload.
* config/nvptx/mkoffload.c (ptx_dumpbase): New.
(main): Handle incoming -dumpbase.  Set ptx_dumpbase.  Obey
save_temps.
(compile_native): Pass -dumpbase et al to compiler.
* config/gcn/mkoffload.c (gcn_dumpbase): New.
(main): Handle incoming -dumpbase.  Set gcn_dumpbase.  Obey
save_temps.  Pass -dumpbase et al to offload target compiler.
(compile_native): Pass -dumpbase et al to compiler.

for  gcc/testsuite/ChangeLog

* lib/scanoffload.exp: New.
* lib/scanoffloadrtl.exp: Load it.  Replace ".o" with ""
globally, and use scanoffload's scoff wrapper to fill it in.
* lib/scanoffloadtree.exp: Likewise.

for libgomp/ChangeLog

* testsuite/lib/libgomp.exp: Load gcc lib scanoffload.exp.
* testsuite/lib/libgomp-dg.exp: Drop now-obsolete -save-temps.

libstdc++: Implement P1972R2 changes to std::variant (PR 95832)

G++ implements P1972R2 since r11-1597-0ca22d027ecc and so we no longer
need the P0608R3 special case to prevent narrowing conversions to bool.

Since non-GNU compilers don't necessarily implment P1972R2 yet, this
may cause a regression for those compilers. There is no feature-test
macro we can use to detect it though, so we'll have to live with it.

libstdc++-v3/ChangeLog:

PR libstdc++/95832
* include/std/variant (__detail::__variant::_Build_FUN): Remove
partial specialization to prevent narrowing conversions to bool.
* testsuite/20_util/variant/compile.cc: Test non-narrowing
conversions to bool.
* testsuite/20_util/variant/run.cc: Likewise.

libstdc++: Regenerate makefiles

libstdc++-v3/ChangeLog:

* doc/Makefile.in: Regenerate.
* include/Makefile.in: Regenerate.
* libsupc++/Makefile.in: Regenerate.
* po/Makefile.in: Regenerate.
* python/Makefile.in: Regenerate.
* src/Makefile.in: Regenerate.
* src/c++11/Makefile.in: Regenerate.
* src/c++17/Makefile.in: Regenerate.
* src/c++98/Makefile.in: Regenerate.
* src/filesystem/Makefile.in: Regenerate.
* testsuite/Makefile.in: Regenerate.

Add REVISION

gcc/
2020-06-23  Michael Meissner  <meissner@linux.ibm.com>

* REVISION: New file.

Handle AR_FULL vs. AR_FULL in dependency checking.

Previously, handling of full vs. full references failed to take
AR_FULL vs. AR_FULL into account.  A change in dependency
checking in gcc 10 created a code path that could lead there;
with this patch, this is now correctly handled.

gcc/fortran/ChangeLog:

2020-06-23  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/95812
* dependency.c (ref_same_as_full_array): Handle case of AR_FULL
vs. AR_FULL.

gcc/testsuite/ChangeLog:

2020-06-23  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/95812
* gfortran.dg/dependency_59.f90: New test.

Fortran  :  ICE in gfc_validate_kind PR95586

Report syntax error for invalid letter-spec in IMPLICIT statements
for derived types and not an ICE.

Original patch by Steve Kargl.  Added test cases based on those
provided by G. Steinmetz  in the PR.

2020-06-23  Steven G. Kargl  <kargl@gcc.gnu.org>

gcc/fortran/

PR fortran/95586
* decl.c (gfc_match_implicit): Only perform else branch if
the type spect is not BT_DERIVED.

2020-06-23  Mark Eggleston  <markeggleston@gcc.gnu.org>

gcc/testsuite/

PR fortran/95586
* gfortran.dg/pr95586_1.f90: New test.
* gfortran.dg/pr95586_2.f90: New test.

Daily bump.

build: Use -include instead of conditional include.

Automake and GNU Make both use the endif keyword, which conflicts and
elicits an error for matching if/ifdef and endif.

This patch changes the conditional include to use "-include" to prevent
a warning about a possible empty tmake_file.

libgomp/ChangeLog

2020-06-22  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am: Use -include.
* Makefile.in: Regenerate.

libatomic/ChangeLog

2020-06-22  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am: Use -include.
* Makefile.in: Regenerate.

libstdc++-v3/ChangeLog

2020-06-22  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am: Use -include.
* Makefile.in: Regenerate.

libgfortran/ChangeLog

2020-06-22  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am: Use -include.
* Makefile.in: Regenerate.

rs6000: Testsuite changes to go with the previous commit

The "sanity checker" thinks it knows better than maintainers, and there
is no override.

2020-06-22  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/cfuged-0.c: I protest.
* gcc.target/powerpc/cfuged-1.c: I protest.
* gcc.target/powerpc/clone3.c: I protest.
* gcc.target/powerpc/cntlzdm-0.c: I protest.
* gcc.target/powerpc/cntlzdm-1.c: I protest.
* gcc.target/powerpc/cnttzdm-0.c: I protest.
* gcc.target/powerpc/cnttzdm-1.c: I protest.
* gcc.target/powerpc/cpu-future.c: I protest.
* gcc.target/powerpc/dg-future-0.c: I protest.
* gcc.target/powerpc/dg-future-1.c: I protest.
* gcc.target/powerpc/localentry-1.c: I protest.
* gcc.target/powerpc/localentry-detect-1.c: I protest.
* gcc.target/powerpc/mma-builtin-1.c: I protest.
* gcc.target/powerpc/mma-builtin-2.c: I protest.
* gcc.target/powerpc/mma-builtin-3.c: I protest.
* gcc.target/powerpc/mma-builtin-4.c: I protest.
* gcc.target/powerpc/mma-builtin-5.c: I protest.
* gcc.target/powerpc/mma-builtin-6.c: I protest.
* gcc.target/powerpc/notoc-direct-1.c: I protest.
* gcc.target/powerpc/pcrel-sibcall-1.c: I protest.
* gcc.target/powerpc/pdep-0.c: I protest.
* gcc.target/powerpc/pdep-1.c: I protest.
* gcc.target/powerpc/pextd-0.c: I protest.
* gcc.target/powerpc/pextd-1.c: I protest.
* gcc.target/powerpc/pr93122.c: I protest.
* gcc.target/powerpc/pr94740.c: I protest.
* gcc.target/powerpc/setbceq.c: I protest.
* gcc.target/powerpc/setbcge.c: I protest.
* gcc.target/powerpc/setbcgt.c: I protest.
* gcc.target/powerpc/setbcle.c: I protest.
* gcc.target/powerpc/setbclt.c: I protest.
* gcc.target/powerpc/setbcne.c: I protest.
* gcc.target/powerpc/setnbceq.c: I protest.
* gcc.target/powerpc/setnbcge.c: I protest.
* gcc.target/powerpc/setnbcgt.c: I protest.
* gcc.target/powerpc/setnbcle.c: I protest.
* gcc.target/powerpc/setnbclt.c: I protest.
* gcc.target/powerpc/setnbcne.c: I protest.
* gcc.target/powerpc/vec-cfuged-0.c: I protest.
* gcc.target/powerpc/vec-cfuged-1.c: I protest.
* gcc.target/powerpc/vec-clrl-0.c: I protest.
* gcc.target/powerpc/vec-clrl-1.c: I protest.
* gcc.target/powerpc/vec-clrl-2.c: I protest.
* gcc.target/powerpc/vec-clrl-3.c: I protest.
* gcc.target/powerpc/vec-clrr-0.c: I protest.
* gcc.target/powerpc/vec-clrr-1.c: I protest.
* gcc.target/powerpc/vec-clrr-2.c: I protest.
* gcc.target/powerpc/vec-clrr-3.c: I protest.
* gcc.target/powerpc/vec-cntlzm-0.c: I protest.
* gcc.target/powerpc/vec-cntlzm-1.c: I protest.
* gcc.target/powerpc/vec-cnttzm-0.c: I protest.
* gcc.target/powerpc/vec-cnttzm-1.c: I protest.
* gcc.target/powerpc/vec-extracth-0.c: I protest.
* gcc.target/powerpc/vec-extracth-1.c: I protest.
* gcc.target/powerpc/vec-extracth-2.c: I protest.
* gcc.target/powerpc/vec-extracth-3.c: I protest.
* gcc.target/powerpc/vec-extracth-4.c: I protest.
* gcc.target/powerpc/vec-extracth-5.c: I protest.
* gcc.target/powerpc/vec-extracth-6.c: I protest.
* gcc.target/powerpc/vec-extracth-7.c: I protest.
* gcc.target/powerpc/vec-extracth-be-0.c: I protest.
* gcc.target/powerpc/vec-extracth-be-1.c: I protest.
* gcc.target/powerpc/vec-extracth-be-2.c: I protest.
* gcc.target/powerpc/vec-extracth-be-3.c: I protest.
* gcc.target/powerpc/vec-extractl-0.c: I protest.
* gcc.target/powerpc/vec-extractl-1.c: I protest.
* gcc.target/powerpc/vec-extractl-2.c: I protest.
* gcc.target/powerpc/vec-extractl-3.c: I protest.
* gcc.target/powerpc/vec-extractl-4.c: I protest.
* gcc.target/powerpc/vec-extractl-5.c: I protest.
* gcc.target/powerpc/vec-extractl-6.c: I protest.
* gcc.target/powerpc/vec-extractl-7.c: I protest.
* gcc.target/powerpc/vec-extractl-be-0.c: I protest.
* gcc.target/powerpc/vec-extractl-be-1.c: I protest.
* gcc.target/powerpc/vec-extractl-be-2.c: I protest.
* gcc.target/powerpc/vec-extractl-be-3.c: I protest.
* gcc.target/powerpc/vec-gnb-0.c: I protest.
* gcc.target/powerpc/vec-gnb-1.c: I protest.
* gcc.target/powerpc/vec-gnb-2.c: I protest.
* gcc.target/powerpc/vec-pdep-0.c: I protest.
* gcc.target/powerpc/vec-pdep-1.c: I protest.
* gcc.target/powerpc/vec-pext-0.c: I protest.
* gcc.target/powerpc/vec-pext-1.c: I protest.
* gcc.target/powerpc/vec-stril-0.c: I protest.
* gcc.target/powerpc/vec-stril-1.c: I protest.
* gcc.target/powerpc/vec-stril-10.c: I protest.
* gcc.target/powerpc/vec-stril-11.c: I protest.
* gcc.target/powerpc/vec-stril-12.c: I protest.
* gcc.target/powerpc/vec-stril-13.c: I protest.
* gcc.target/powerpc/vec-stril-14.c: I protest.
* gcc.target/powerpc/vec-stril-15.c: I protest.
* gcc.target/powerpc/vec-stril-16.c: I protest.
* gcc.target/powerpc/vec-stril-17.c: I protest.
* gcc.target/powerpc/vec-stril-18.c: I protest.
* gcc.target/powerpc/vec-stril-19.c: I protest.
* gcc.target/powerpc/vec-stril-2.c: I protest.
* gcc.target/powerpc/vec-stril-20.c: I protest.
* gcc.target/powerpc/vec-stril-21.c: I protest.
* gcc.target/powerpc/vec-stril-22.c: I protest.
* gcc.target/powerpc/vec-stril-23.c: I protest.
* gcc.target/powerpc/vec-stril-3.c: I protest.
* gcc.target/powerpc/vec-stril-4.c: I protest.
* gcc.target/powerpc/vec-stril-5.c: I protest.
* gcc.target/powerpc/vec-stril-6.c: I protest.
* gcc.target/powerpc/vec-stril-7.c: I protest.
* gcc.target/powerpc/vec-stril-8.c: I protest.
* gcc.target/powerpc/vec-stril-9.c: I protest.
* gcc.target/powerpc/vec-stril_p-0.c: I protest.
* gcc.target/powerpc/vec-stril_p-1.c: I protest.
* gcc.target/powerpc/vec-stril_p-10.c: I protest.
* gcc.target/powerpc/vec-stril_p-11.c: I protest.
* gcc.target/powerpc/vec-stril_p-2.c: I protest.
* gcc.target/powerpc/vec-stril_p-3.c: I protest.
* gcc.target/powerpc/vec-stril_p-4.c: I protest.
* gcc.target/powerpc/vec-stril_p-5.c: I protest.
* gcc.target/powerpc/vec-stril_p-6.c: I protest.
* gcc.target/powerpc/vec-stril_p-7.c: I protest.
* gcc.target/powerpc/vec-stril_p-8.c: I protest.
* gcc.target/powerpc/vec-stril_p-9.c: I protest.
* gcc.target/powerpc/vec-strir-0.c: I protest.
* gcc.target/powerpc/vec-strir-1.c: I protest.
* gcc.target/powerpc/vec-strir-10.c: I protest.
* gcc.target/powerpc/vec-strir-11.c: I protest.
* gcc.target/powerpc/vec-strir-12.c: I protest.
* gcc.target/powerpc/vec-strir-13.c: I protest.
* gcc.target/powerpc/vec-strir-14.c: I protest.
* gcc.target/powerpc/vec-strir-15.c: I protest.
* gcc.target/powerpc/vec-strir-16.c: I protest.
* gcc.target/powerpc/vec-strir-17.c: I protest.
* gcc.target/powerpc/vec-strir-18.c: I protest.
* gcc.target/powerpc/vec-strir-19.c: I protest.
* gcc.target/powerpc/vec-strir-2.c: I protest.
* gcc.target/powerpc/vec-strir-20.c: I protest.
* gcc.target/powerpc/vec-strir-21.c: I protest.
* gcc.target/powerpc/vec-strir-22.c: I protest.
* gcc.target/powerpc/vec-strir-23.c: I protest.
* gcc.target/powerpc/vec-strir-3.c: I protest.
* gcc.target/powerpc/vec-strir-4.c: I protest.
* gcc.target/powerpc/vec-strir-5.c: I protest.
* gcc.target/powerpc/vec-strir-6.c: I protest.
* gcc.target/powerpc/vec-strir-7.c: I protest.
* gcc.target/powerpc/vec-strir-8.c: I protest.
* gcc.target/powerpc/vec-strir-9.c: I protest.
* gcc.target/powerpc/vec-strir_p-0.c: I protest.
* gcc.target/powerpc/vec-strir_p-1.c: I protest.
* gcc.target/powerpc/vec-strir_p-10.c: I protest.
* gcc.target/powerpc/vec-strir_p-11.c: I protest.
* gcc.target/powerpc/vec-strir_p-2.c: I protest.
* gcc.target/powerpc/vec-strir_p-3.c: I protest.
* gcc.target/powerpc/vec-strir_p-4.c: I protest.
* gcc.target/powerpc/vec-strir_p-5.c: I protest.
* gcc.target/powerpc/vec-strir_p-6.c: I protest.
* gcc.target/powerpc/vec-strir_p-7.c: I protest.
* gcc.target/powerpc/vec-strir_p-8.c: I protest.
* gcc.target/powerpc/vec-strir_p-9.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-0.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-1.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-10.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-2.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-3.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-4.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-5.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-6.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-7.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-8.c: I protest.
* gcc.target/powerpc/vec-ternarylogic-9.c: I protest.
* gcc.target/powerpc/xxgenpc-runnable.c: I protest.
* lib/target-supports.exp: Stuff.

rs6000: Rename future to power10

This renames the command line options, the internal names, and mentions
in the comments, from "future" to "power10".  Also, the file "future.md"
is renamed.

The predefined user macro _ARCH_PWR_FUTURE is renamed to _ARCH_PWR10.

"Future architecture" is renamed to "ISA 3.1".

2020-06-22  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/ChangeLog:

* config/rs6000/altivec.h: Use _ARCH_PWR10, not _ARCH_PWR_FUTURE.
Update comment for ISA 3.1.
* config/rs6000/altivec.md: Use TARGET_POWER10, not TARGET_FUTURE.
* config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10
on AIX, and -mpower10 elsewhere.
* config/rs6000/future.md: Delete.
* config/rs6000/linux64.h: Update comments.  Use TARGET_POWER10, not
TARGET_FUTURE.
* config/rs6000/power10.md: New file.
* config/rs6000/ppc-auxv.h: Use PPC_PLATFORM_POWER10, not
PPC_PLATFORM_FUTURE.
* config/rs6000/rs6000-builtin.def: Update comments.  Use BU_P10V_*
names instead of BU_FUTURE_V_* names.  Use RS6000_BTM_P10 instead of
RS6000_BTM_FUTURE.  Use P10_BUILTIN_* instead of FUTURE_BUILTIN_*.
Use BU_P10_* instead of BU_FUTURE_*.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
_ARCH_PWR10 instead of _ARCH_PWR_FUTURE.
(altivec_resolve_overloaded_builtin): Use P10_BUILTIN_VEC_XXEVAL, not
FUTURE_BUILTIN_VEC_XXEVAL.
* config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*.
Update compiler messages.
* config/rs6000/rs6000-cpus.def: Update comments.  Use ISA_3_1_*, not
ISA_FUTURE_*.  Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE.
* config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not
PROCESSOR_FUTURE.
* config/rs6000/rs6000-string.c: Ditto.
* config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10"
instead of "future", reorder it to right after "power9".
* config/rs6000/rs6000.c: Update comments.  Use OPTION_MASK_POWER10,
not OPTION_MASK_FUTURE.  Use TARGET_POWER10, not TARGET_FUTURE.  Use
RS6000_BTM_P10, not RS6000_BTM_FUTURE.  Update compiler messages.
Use PROCESSOR_POWER10, not PROCESSOR_FUTURE.  Use ISA_3_1_MASKS_SERVER,
not ISA_FUTURE_MASKS_SERVER.
(rs6000_opt_masks): Use "power10" instead of "future".
(rs6000_builtin_mask_names): Ditto.
(rs6000_disable_incompatible_switches): Ditto.
* config/rs6000/rs6000.h: Use -mpower10, not -mfuture.  Use
-mcpu=power10, not -mcpu=future.  Use MASK_POWER10, not MASK_FUTURE.
Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE.  Use RS6000_BTM_P10,
not RS6000_BTM_FUTURE.
* config/rs6000/rs6000.md: Use "power10", not "future".  Use
TARGET_POWER10, not TARGET_FUTURE.  Include "power10.md", not
"future.md".
* config/rs6000/rs6000.opt (mfuture): Delete.
(mpower10): New.
* config/rs6000/t-rs6000: Use "power10.md", not "future.md".
* config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE.

Update gcc sv.po.

* sv.po: Update.

recog: Restore builds with Clang

Using parameter packs with function typedefs tripped a Clang bug
in which the packs were not being expanded correctly:

  https://bugs.llvm.org/show_bug.cgi?id=46377

Work around that by going back to the decltype approach, but adding
a cast to void to suppress a warning about unused values.

2020-06-22  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* coretypes.h (first_type): Delete.
* recog.h (insn_gen_fn::operator()): Go back to using a decltype.

arm: Fix the failing mve scalar shift execution tests.

In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings
because of executing them on target hardware which doesn't support MVE instructions. This patch
restricts those tests to execute only on target hardware that support MVE instructions.

2020-06-22  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
* doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item.
(arm_mve_hw): Likewise.

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: Modify.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_mve_hw): Define.

Fortran  : ICE in resolve_fl_procedure PR95708

Now issues an error "Intrinsic procedure 'num_images' not
allowed in PROCEDURE" instead of an ICE.

2020-06-22  Steven G. Kargl  <kargl@gcc.gnu.org>

gcc/fortran/

PR fortran/95708
* intrinsic.c (add_functions): Replace CLASS_INQUIRY with
CLASS_TRANSFORMATIONAL for intrinsic num_images.
(make_generic): Replace ACTUAL_NO with ACTUAL_YES for
intrinsic team_number.
* resolve.c (resolve_fl_procedure): Check pointer ts.u.derived
exists before using it.

2020-06-22  Mark Eggleston  <markeggleston@gcc.gnu.org>

gcc/testsuite/

PR fortran/95708
* gfortran.dg/pr95708.f90: New test.

x86: Skip EXT_REX_SSE_REG_P for vzeroupper optimization

Skip EXT_REX_SSE_REG_P for vzeroupper optimization since upper 16 vector
registers don't trigger SSE <-> AVX transition penalty.

gcc/

PR target/95791
* config/i386/i386.c (ix86_dirflag_mode_needed): Skip
EXT_REX_SSE_REG_P.

gcc/testsuite/

PR target/95791
* gcc.target/i386/pr95791.c: New test.

Fortran  : ICE in gfc_check_reshape PR95585

Issue an error where an array is used before its definition
instead of an ICE.

2020-06-22  Steven G. Kargl  <kargl@gcc.gnu.org>

gcc/fortran/

PR fortran/95585
* check.c (gfc_check_reshape): Add check for a value when
the symbol has an attribute flavor FL_PARAMETER.

2020-06-22  Mark Eggleston  <markeggleston@gcc.gnu.org>

gcc/testsuite/

PR fortran/95585
* gfortran.dg/pr95585.f90: New test.

Fortran  : Missing gcc-internal-format PR42693

Messages in gfc_arith_error contain gcc internal format specifiers
which should be enclosed in G_() in order to be correctly translated.

2020-06-22  Mark Eggleston  <markeggleston@gcc.gnu.org>

gcc/fortran/

PR fortran/42693
* arith.c (gfc_arith_error): Enclose strings in G_() instead
of _().

tree-optimization/95770 - fix SLP vectorized stmt placement compute

This fixes the vectorized stmt placement compute for the case of
external defs.

2020-06-22  Richard Biener  <rguenther@suse.de>

PR tree-optimization/95770
* tree-vect-slp.c (vect_schedule_slp_instance): Also consider
external defs.

* gcc.dg/pr95770.c: New testcase.

amdgcn: Pass vector parameters in memory

gcc/ChangeLog:

* config/gcn/gcn.c (gcn_function_arg): Disallow vector arguments.
(gcn_return_in_memory): Return vectors in memory.

openmp: Compute triangular loop number of iterations at compile time

2020-06-22  Jakub Jelinek  <jakub@redhat.com>

* omp-general.c (omp_extract_for_data): For triangular loops with
all loop invariant expressions constant where the innermost loop is
executed at least once compute number of iterations at compile time.

RISC-V: Normalize arch string in driver time

 - Normalize arch string would help the multi-lib handling, e.g. rv64gc and
   rv64g_c are both valid and same arch, but latter one would confuse
   the detection of multi-lib, earlier normalize can resolve this issue.

gcc/ChangeLog:

* config/riscv/riscv.h (ASM_SPEC): Remove riscv_expand_arch call.
(DRIVER_SELF_SPECS): New.

RISC-V: Fix compilation failed for frflags builtin in C++ mode

  - g++ will complain too few arguments for frflags builtin like bellow
    message:

    error: too few arguments to function 'unsigned int __builtin_riscv_frflags(void)'

  - However it's no arguments needed, it because we declare the function
    type with VOID arguments, that seems like require a VOID argument
    in the c++ front-end when GCC tried to resolve the function.

gcc/ChangeLog

* config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New.
(RISCV_FTYPE_ATYPES0): New.
(riscv_builtins): Using RISCV_USI_FTYPE for frflags.
* config/riscv/riscv-ftypes.def: Remove VOID argument.

gcc/testsuite/ChangeLog

* g++.target/riscv/frflags.C: New.

Daily bump.

aix: Add GCC64 configuration and FAT target libraries.

This patch adds the ability to configure GCC on AIX to build as a
64 bit application and to build target libraries "FAT" libraries in both
32 bit and 64 bit mode.

The patch adds makefile fragment hooks to target libraries that allows
them to include target-specific rules.  The target specific rules for
AIX place both 32 bit and 64 bit objects and shared objects
in archives at the top-level, not multilib subdirectories.  The
multilibs are built in subdirectories, but must be combined during the
last parts of the target library build process.  Because of the way
that GCC bootstrap works, the libraries must be combined during the
multiple stages of GCC bootstrap, not solely when installed in the
final destination, so the libraries are correct at the end of
each target library build stage, not solely an install recipe.

gcc/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* config.gcc: Use t-aix64, biarch64 and default64 for cpu_is_64bit.
* config/rs6000/aix72.h (ASM_SPEC): Remove aix64 option.
(ASM_SPEC32): New.
(ASM_SPEC64): New.
(ASM_CPU_SPEC): Remove vsx and altivec options.
(CPP_SPEC_COMMON): Rename from CPP_SPEC.
(CPP_SPEC32): New.
(CPP_SPEC64): New.
(CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON..
(TARGET_DEFAULT): Only define if not BIARCH.
(LIB_SPEC_COMMON): Rename from LIB_SPEC.
(LIB_SPEC32): New.
(LIB_SPEC64): New.
(LINK_SPEC_COMMON): Rename from LINK_SPEC.
(LINK_SPEC32): New.
(LINK_SPEC64): New.
(STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase.
(ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P.
(CPP_SPEC): Same.
(CPLUSPLUS_CPP_SPEC): Same.
(LIB_SPEC): Same.
(LINK_SPEC): Same.
(SUBTARGET_EXTRA_SPECS): Add new 32/64 specs.
* config/rs6000/defaultaix64.h: New file.
* config/rs6000/t-aix64: New file.

libgcc/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* config.host (extra_parts): Add crtcxa_64 and crtdbase_64.
* config/rs6000/t-aix-cxa: Explicitly compile 32 bit with -maix32
and 64 bit with -maix64.
* config/rs6000/t-slibgcc-aix: Remove extra @multilib_dir@ level.
Build and install AIX-style FAT libraries.

libgomp/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.

libstdc++-v3/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host (aix*): Define tmake_file.
* config/os/aix/t-aix: New file.

libatomic/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.

libgfortran/ChangeLog

2020-06-21  David Edelsohn  <dje.gcc@gmail.com>

* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host: Add system configury stanza. Define tmake_file.
* config/t-aix: New file.

rs6000: Add MMA built-in function definitions and test cases.

Add the Matrix-Multiply Assist (MMA) built-ins.  The MMA accumulators are
INOUT operands for most MMA instructions, but they are also very expensive
to move around.  For this reason, we have implemented a built-in API where
the accumulators are passed using pass-by-reference/pointers, so the user
won't use one accumulator as input and another as output, which wouldentail
a lot of copies.  However, using pointers gives us poor code generation
when we expand the built-ins at normal expand time.  We therefore expand
the MMA built-ins early into gimple, converting the pass-by-reference calls
to an internal built-in that uses pass-by-value calling convention, where
we can enforce the input and output accumulators are the same.  This gives
us much better code generation.

2020-06-20  Peter Bergner  <bergner@linux.ibm.com>

gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): New.
* config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3,
BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA
built-in functions.
(ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR,
PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN,
PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP,
PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN,
PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN,
PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP,
PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4,
PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP,
XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2,
XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER,
XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN,
XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S,
XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP,
XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins.
* config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P.
Allow zero constants.
(print_operand) <case 'A'>: New output modifier.
(rs6000_split_multireg_move): Add support for inserting accumulator
priming and depriming instructions.  Add support for splitting an
assemble accumulator pattern.
* config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin,
rs6000_gimple_fold_mma_builtin): New functions.
(RS6000_BUILTIN_M): New macro.
(def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes.
(bdesc_mma): Add new MMA built-in support.
(htm_expand_builtin): Use RS6000_BTC_OPND_MASK.
(rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and
RS6000_BTM_MMA.
(rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute.
(rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p
and rs6000_gimple_fold_mma_builtin.
(rs6000_expand_builtin): Call mma_expand_builtin.
Use RS6000_BTC_OPND_MASK.
(rs6000_init_builtins): Adjust comment.  Call mma_init_builtins.
(htm_init_builtins): Use RS6000_BTC_OPND_MASK.
(builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and
VSX_BUILTIN_XVCVBF16SP.
* config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY,
RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR,
RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines.
(RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST,
RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values.
* config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant.
(UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2,
UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP,
UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP,
UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN,
UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN,
UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER,
UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP,
UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP,
UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN,
UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN,
UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2,
UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S,
UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8,
UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4,
UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP,
UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN,
UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN,
UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN,
UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP,
UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP,
UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER,
UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN,
UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP,
UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8,
UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP,
UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New.
(MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8,
MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4,
MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4,
MMA_AVVI4I4I4): New define_int_iterator.
(acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2,
avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4,
avvi4i4i4): New define_int_attr.
(*movpxi): Add zero constant alternative.
(mma_assemble_pair, mma_assemble_acc): New define_expand.
(*mma_assemble_acc): New define_insn_and_split.
(mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn.
* config/rs6000/rs6000.md (define_attr "type"): New type mma.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New.
(UNSPEC_VSX_XVCVSPBF16): Likewise.
(XVCVBF16): New define_int_iterator.
(xvcvbf16): New define_int_attr.
(vsx_<xvcvbf16>): New define_insn.
* doc/extend.texi: Document the mma built-ins.

rs6000: Add base support and types for defining MMA built-ins.

Add the new -mmma option as well as the initial MMA support, which includes
the target specific __vector_pair and __vector_quad types, the POImode and
PXImode partial integer modes they are mapped to, and their associated
move patterns.  Support for the restrictions on the registers these modes
can be assigned to as also been added.

2020-06-20  Peter Bergner  <bergner@linux.ibm.com>
    Michael Meissner  <meissner@linux.ibm.com>

gcc/
* config/rs6000/mma.md: New file.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__MMA__ for mma.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support
for __vector_pair and __vector_quad types.
* config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add
OPTION_MASK_MMA.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-modes.def (OI, XI): New integer modes.
(POI, PXI): New partial integer modes.
* config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define.
(rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
Add support for POImode being allowed in VSX registers and PXImode
being allowed in FP registers.
(rs6000_modes_tieable_p): Adjust comment.
Add support for POImode and PXImode.
(rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode
XImode, PXImode, V2SImode, V2SFmode and CCFPmode..
(rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P.
Set up appropriate addr_masks for vector pair and vector quad addresses.
(rs6000_init_hard_regno_mode_ok): Add support for vector pair and
vector quad registers.  Setup reload handlers for POImode and PXImode.
(rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA.
(rs6000_option_override_internal): Error if -mmma is specified
without -mcpu=future.
(rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P.
(quad_address_p): Change size test to less than 16 bytes.
(reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair
and vector quad instructions.
(avoiding_indexed_address_p): Likewise.
(rs6000_emit_move): Disallow POImode and PXImode moves involving
constants.
(rs6000_preferred_reload_class): Prefer VSX registers for POImode
and FP registers for PXImode.
(rs6000_split_multireg_move): Support splitting POImode and PXImode
move instructions.
(rs6000_mangle_type): Adjust comment.  Add support for mangling
__vector_pair and __vector_quad types.
(rs6000_opt_masks): Add entry for mma.
(rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_function_value): Use VECTOR_ALIGNMENT_P.
(address_to_insn_form): Likewise.
(reg_to_non_prefixed): Likewise.
(rs6000_invalid_conversion): New function.
* config/rs6000/rs6000.h (MASK_MMA): Define.
(BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled.
(VECTOR_ALIGNMENT_P): New helper macro.
(ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P.
(RS6000_BTM_MMA): Define.
(RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and
RS6000_BTI_vector_quad.
(vector_pair_type_node): New.
(vector_quad_type_node): New.
* config/rs6000/rs6000.md: Include mma.md.
(define_mode_iterator RELOAD): Add POI and PXI.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md.
* config/rs6000/rs6000.opt (-mmma): New.
* doc/invoke.texi: Document -mmma.

Daily bump.

coroutines: Update handling and failure for g-r-o-o-a-f [PR95505]

The actual issue is that (in the testcase) std::nothrow is not
available.  So update the handling of the get-return-on-alloc-fail
to include the possibility that std::nothrow might not be
available.

gcc/cp/ChangeLog:

PR c++/95505
* coroutines.cc (morph_fn_to_coro): Update handling of
get-return-object-on-allocation-fail and diagnose missing
std::nothrow.

gcc/testsuite/ChangeLog:

PR c++/95505
* g++.dg/coroutines/pr95505.C: New test.

c++: Refinements to "more constrained".

P2113 from the last C++ meeting clarified that we only compare constraints
on functions or function templates that have equivalent template parameters
and function parameters.

I'm not currently implementing the complicated handling of reversed
comparison operators here; thinking about it now, it seems like a lot of
complexity to support a very weird usage.  If I write two similar comparison
operators to be distinguished by their constraints, why would I write one
reversed?  If they're two unrelated operators, they're very unlikely to be
similar enough for the complexity to help.  I've started a discussion on the
committee reflector about changing these rules.

This change breaks some greedy_ops tests in libstdc++ that were relying on
comparing constraints on unrelated templates, which seems pretty clearly
wrong, so I'm removing those tests for now.

gcc/cp/ChangeLog:

* call.c (joust): Only compare constraints for non-template
candidates with matching parameters.
* pt.c (tsubst_pack_expansion): Fix getting a type parameter
pack.
(more_specialized_fn): Only compare constraints for candidates with
matching parameters.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-return-req1.C: Expect error.
* g++.dg/cpp2a/concepts-p2113a.C: New test.
* g++.dg/cpp2a/concepts-p2113b.C: New test.

libstdc++-v3/ChangeLog:

* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc:
Remove greedy_ops tests.
* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc:
Remove greedy_ops tests.

PR fortran/95707 - ICE in finish_equivalences, at fortran/trans-common.c:1319

With submodules and equivalence declarations, name mangling may result in
long internal symbols overflowing internal buffers.  We now check that
we do not exceed the enlarged buffer sizes.

gcc/fortran/
PR fortran/95707
* gfortran.h (gfc_common_head): Enlarge buffer.
* trans-common.c (gfc_sym_mangled_common_id): Enlarge temporary
buffers, and add check on length on mangled name to prevent
overflow.

PR fortran/95688 - ICE in gfc_get_string, at fortran/iresolve.c:70

With submodules, name mangling of character pointer declarations produces long
internal symbols that overflowed a static internal buffer.  Adjust the buffer
size.

gcc/fortran/
PR fortran/95688
* iresolve.c (gfc_get_string): Enlarge static buffer size.

PR fortran/95687 - ICE in get_unique_hashed_string, at fortran/class.c:508

With submodules and PDTs, name mangling of interfaces may result in long
internal symbols overflowing a previously static internal buffer.  We now
set the buffer size dynamically.

gcc/fortran/
PR fortran/95687
* class.c (get_unique_type_string): Return a string with dynamic
length.
(get_unique_hashed_string, gfc_hash_value): Use dynamic result
from get_unique_type_string instead of static buffer.

PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015

With submodules, name mangling of interfaces may result in long internal
symbols overflowing an internal buffer.  We now check that we do not
exceed the enlarged buffer size.

gcc/fortran/
PR fortran/95689
* interface.c (check_sym_interfaces): Enlarge temporary buffer,
and add check on length on mangled name to prevent overflow.

PR fortran/95587 - ICE in gfc_target_encode_expr, at fortran/target-memory.c:362

EQUIVALENCE objects are subject to constraints listed in the Fortran 2018
standard, section 8.10.1.1.  These constraints are to be checked
also for CLASS variables.

gcc/fortran/
PR fortran/95587
* match.c (gfc_match_equivalence): Check constraints on
EQUIVALENCE objects also for CLASS variables.

Record and restore postorder information in breaking alias sccs.

gcc/
PR tree-optimization/95638
* tree-loop-distribution.c (pg_edge_callback_data): New field.
(loop_distribution::break_alias_scc_partitions): Record and restore
postorder information.  Fix memory leak.

gcc/testsuite/
PR tree-optimization/95638
* g++.dg/tree-ssa/pr95638.C: New test.

Daily bump.

testsuite: popcount[45]ll require lp64

popcount[45]ll require __builtin_popcountll, but the test can succeed
without libcall through expand_doubleword_popcount.  However the Tree-SSA
optiization requires recognition of POPCOUNT.  This patch limits the test
to lp64 for the targets that fall through the cracks and were not
caught by the dg-require-effective-target popcountll.

gcc/testsuite/ChangeLog

2020-06-19  David Edelsohn  <dje.gcc@gmail.com>

* gcc.dg/tree-ssa/popcount4ll.c: Add target lp64.
* gcc.dg/tree-ssa/popcount5ll.c: Same.

libstdc++: Fix some -Wsystem-headers warnings (PR 95765)

PR libstdc++/95765
* include/bits/stl_algobase.h (__size_to_integer(float))
(__size_to_integer(double), __size_to_integer(long double))
(__size_to_integer(__float128)): Cast return type explicitly.
* include/bits/stl_uninitialized.h (__uninitialized_default_1<true>):
Remove unused typedef.

c++: Allow defaulted comparison outside class.

Implementing P2085, another refinement to the operator<=> specification from
the Prague meeting.  It was deemed desirable to be able to have a non-inline
defaulted definition of a comparison operator just like you can with other
defaulted functions.

gcc/cp/ChangeLog:

* method.c (early_check_defaulted_comparison): Allow defaulting
comparison outside class.  Complain if non-member operator isn't a
friend.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/spaceship-friend1.C: New test.
* g++.dg/cpp2a/spaceship-err4.C: Adjust diagnostic.

rs6000: apply -mbig option to vec-extract[hl] testcases conditionally.

gcc/testsuite/ChangeLog

2020-06-19  David Edelsohn  <dje.gcc@gmail.com>

* gcc.target/powerpc/vec-extracth-be-0.c: Apply -mbig
conditionally for powerpc64le*-*-*.
* gcc.target/powerpc/vec-extracth-be-1.c: Same.
* gcc.target/powerpc/vec-extracth-be-2.c: Same.
* gcc.target/powerpc/vec-extracth-be-3.c: Same.
* gcc.target/powerpc/vec-extractl-be-0.c: Same.
* gcc.target/powerpc/vec-extractl-be-1.c: Same.
* gcc.target/powerpc/vec-extractl-be-2.c: Same.
* gcc.target/powerpc/vec-extractl-be-3.c: Same.

amdgcn: Silence compile warnings

gcc/ChangeLog:

* config/gcn/gcn.c (gcn_related_vector_mode): Add ARG_UNUSED.
(output_file_start): Use const 'char *'.

Fix PR94880: Failure to recognize andn pattern

Pattern "(x | y) - y" can be optimized to simple "(x & ~y)" andn
pattern.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

PR tree-optimization/94880
* match.pd (A | B) - B -> (A & ~B): New simplification.

gcc/testsuite/ChangeLog:

PR tree-optimization/94880
* gcc.dg/tree-ssa/pr94880.c: New Test.

Handle SLP_TREE_LANE_PERMUTATION in scalar costing

This properly handles a lane permutation in scalar costing.
For the current only use this doesn't matter much but with
permutes that change the number of lanes it will eventually
ICE.

2020-06-19  Richard Biener  <rguenther@suse.de>

* tree-vect-slp.c (vect_bb_slp_scalar_cost): Adjust
for lane permutations.

libstdc++: Remove redundant std:: qualification

* include/bits/stl_pair.h (_Index_tuple): Remove redundant
namespace qualification.
(pair::pair(tuple<>&, tuple<>&, _Index_tuple, _Index_tuple)):
Likewise.
* include/std/tuple (_Head_base, _Tuple_impl, tuple_size)
(tuple_element, __get_helper, get, __make_tuple_impl)
(__make_1st_indices, __tuple_concater)
(pair::pair(tuple<>&, tuple<>&, _Index_tuple, _Index_tuple)):
Likewise.
* include/std/utility (tuple_element, __is_tuple_like_impl)
(tuple_size, __pair_get, get): Likewise.

libstdc++: Define all std::function members inline

* include/bits/std_function.h (function): Define all member
functions inline.

libstdc++: std::includes performance tweak

A small tweak to the implementation of __includes, which in my
application saves 20% of the running time. I noticed it because using
range-v3 was giving unexpected performance gains.

Some of the gain comes from pulling the 2 calls ++__first1 out of the
condition so there is just one call. And most of the gain comes from
replacing the resulting

if (__comp(__first1, __first2))
  ;
else
  ++__first2;

with

if (!__comp(__first1, __first2))
  ++__first2;

I was very surprised that the code ended up being so different for such
a change, and I still don't really understand where the extra time is
going...

Anyway, while I blame the compiler for not generating very good code
with the current implementation, I believe the change can be seen as a
simplification.

libstdc++-v3/ChangeLog:

* include/bits/stl_algo.h (__includes): Simplify the code.

tree-optimization/95761 - fix vector insertion place compute

I missed that indeed SLP permutation code generation can end up
refering to a non-last vectorized stmt in the last SLP_TREE_VEC_STMTS
element as optimization.  So walk them all.

2020-06-19  Richard Biener  <rguenther@suse.de>

PR tree-optimization/95761
* tree-vect-slp.c (vect_schedule_slp_instance): Walk all
vectorized stmts for finding the last one.

* gcc.dg/torture/pr95761.c: New testcase.