Korey Sewell [Sat, 12 Feb 2011 15:14:32 +0000 (10:14 -0500)]
inorder: remove unused file
inst_buffer file isn't used , so remove it
Korey Sewell [Sat, 12 Feb 2011 15:14:26 +0000 (10:14 -0500)]
inorder: remove unused isa ops
pass/fail ops were used for testing but arent part of isa
Ali Saidi [Sat, 12 Feb 2011 00:29:36 +0000 (18:29 -0600)]
Stats: Update the statistics for vnc patch.
Ali Saidi [Sat, 12 Feb 2011 00:29:36 +0000 (18:29 -0600)]
VNC/ARM: Use VNC server and add support to boot into X11
Ali Saidi [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
VNC: Add VNC server to M5
Ali Saidi [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
Serialization: Allow serialization of stl lists
Giacomo Gabrielli [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
O3: Fix pipeline restart when a table walk completes in the fetch stage.
When a table walk is initiated by the fetch stage, the CPU can
potentially move to the idle state and never wake up.
The fetch stage must call cpu->wakeCPU() when a translation completes
(in finishTranslation()).
Giacomo Gabrielli [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
O3: Fix a few bugs in the TableWalker object.
Uncacheable requests were set as such only in atomic mode.
currState->delayed is checked in place of currState->timing for resetting
currState in atomic mode.
Ali Saidi [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.
This change fixes an issue where a DTLB fault occurs and redirects fetch to
handle the fault and the ITLB requires a walk which delays translation. In this
case the status of the cpu isn't updated appropriately, and an additional
instruction fetch occurs. Eventually this hits an assert as multiple instruction
fetches are occuring in the system and when the second one returns the
processor is in the wrong state.
Some asserts below are removed because it was always true (typo) and the state
after the initiateAcc() the processor could be in any valid state when a
d-side fault occurs.
Giacomo Gabrielli [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
O3: Enhance data address translation by supporting hardware page table walkers.
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs,
when a TLB miss occurs, initiateTranslation() can return with NoFault but with
the translation unfinished.
Instructions experiencing a delayed translation due to a hardware page table
walk are deferred until the translation completes and kept into the IQ. In
order to keep track of them, the IQ has been augmented with a queue of the
outstanding delayed memory instructions. When their translation completes,
instructions are re-executed (only their initiateAccess() was already
executed; their DTB translation is now skipped). The IEW stage has been
modified to support such a 2-pass execution.
Ali Saidi [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
ARM: Fix timer calculations.
The timer calculations were a bit off so time would run faster than
it otherwise should
Ali Saidi [Sat, 12 Feb 2011 00:29:35 +0000 (18:29 -0600)]
Timesync: Make sure timesync event is setup after curTick is unserialized
Setup initial timesync event in initState or loadState so that curTick has
been updated to the new value, otherwise the event is scheduled in the past.
Ali Saidi [Thu, 10 Feb 2011 04:27:37 +0000 (22:27 -0600)]
Ext: Add X11 keysym header files to ext directory.
Brad Beckmann [Thu, 10 Feb 2011 00:02:09 +0000 (16:02 -0800)]
ruby: removed duplicate make response call
Brad Beckmann [Wed, 9 Feb 2011 02:07:54 +0000 (18:07 -0800)]
regess: protocol regression tester updates
Brad Beckmann [Tue, 8 Feb 2011 23:53:33 +0000 (15:53 -0800)]
memtest: due to contention increase, increased deadlock threshold
Brad Beckmann [Tue, 8 Feb 2011 23:52:44 +0000 (15:52 -0800)]
config: fixed minor bug connecting dma devices to ruby
Nilay Vaish [Tue, 8 Feb 2011 13:47:02 +0000 (07:47 -0600)]
MESI CMP: Unset TBE pointer in L2 cache controller
The TBE pointer in the MESI CMP implementation was not being set to NULL
when the TBE is deallocated. This resulted in segmentation fault on testing
the protocol when the ProtocolTrace was switched on.
Gabe Black [Tue, 8 Feb 2011 03:23:13 +0000 (19:23 -0800)]
Stats: Re update stats.
Gabe Black [Tue, 8 Feb 2011 03:23:11 +0000 (19:23 -0800)]
Stats: Back out broken update.
Tim Harris [Mon, 7 Feb 2011 23:18:52 +0000 (15:18 -0800)]
X86: Obey the wp bit of CR0.
If cr0.wp ("write protect" bit) is clear then do not generate page faults when
writing to write-protected pages in kernel mode.
Tim Harris [Mon, 7 Feb 2011 23:16:27 +0000 (15:16 -0800)]
X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.
During SYSCALL_64, use dataSize=8 when handling new rip (ref
http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit
address)
Tim Harris [Mon, 7 Feb 2011 23:12:59 +0000 (15:12 -0800)]
X86: Fix JMP_FAR_I to unpack a far pointer correctly.
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.
Tim Harris [Mon, 7 Feb 2011 23:05:28 +0000 (15:05 -0800)]
X86: Read the LDT/GDT at CPL0 when executing an iret.
During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).
Nilay Vaish [Mon, 7 Feb 2011 18:42:23 +0000 (12:42 -0600)]
Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where there as
an error in configuration of the model. These have been replaced with fatal().
Korey Sewell [Mon, 7 Feb 2011 17:19:46 +0000 (12:19 -0500)]
ruby: add stdio header in SRAM.hh
missing header file caused RUBY_FS to not compile
Gabe Black [Mon, 7 Feb 2011 09:23:16 +0000 (01:23 -0800)]
X86: Add stats for the new x86 fs regressions.
Gabe Black [Mon, 7 Feb 2011 09:23:02 +0000 (01:23 -0800)]
X86: Add scripts to support X86 FS configurations in the regressions.
Gabe Black [Mon, 7 Feb 2011 09:22:15 +0000 (01:22 -0800)]
X86, Config: Move the setting of work count options to a separate function.
This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.
Gabe Black [Mon, 7 Feb 2011 09:21:21 +0000 (01:21 -0800)]
X86: Fix compiling vtophys.cc
Brad Beckmann [Mon, 7 Feb 2011 06:14:23 +0000 (22:14 -0800)]
regress: Regression Tester output updates
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
ruby: support to stallAndWait the mandatory queue
By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).
--HG--
rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
ruby: minor fix to deadlock panic message
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
boot: script that creates a checkpoint after Linux boot up
Joel Hestness [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
garnet: Split network power in ruby.stats
Split out dynamic and static power numbers for printing to ruby.stats
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
MOESI_hammer: fixed dir bug counting received acks
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
ruby: numa bit fix for sparse memory
Tushar Krishna [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
MOESI_CMP_token: removed unused message fields
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
mem: Added support for Null data packet
The packet now identifies whether static or dynamic data has been allocated and
is used by Ruby to determine whehter to copy the data pointer into the ruby
request. Subsequently, Ruby can be told not to update phys memory when
receiving packets.
Brad Beckmann [Mon, 7 Feb 2011 06:14:19 +0000 (22:14 -0800)]
m5: added work completed monitoring support
Brad Beckmann [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
dev: fixed bugs to extend interrupt capability beyond 15 cores
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
x86: Timing support for pagetable walker
Move page table walker state to its own object type, and make the
walker instantiate state for each outstanding walk. By storing the
states in a queue, the walker is able to handle multiple outstanding
timing requests. Note that functional walks use separate state
elements.
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
TimingSimpleCPU: split data sender state fix
In sendSplitData, keep a pointer to the senderState that may be updated after
the call to handle*Packet. This way, if the receiver updates the packet
senderState, it can still be accessed in sendSplitData.
Brad Beckmann [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
ruby: Fix RubyPort to properly handle retrys
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
Ruby: Fix to return cache block size to CPU for split data transfers
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
Ruby: Add support for locked memory accesses in X86_FS
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
Ruby: Update the Ruby request type names for LL/SC
Brad Beckmann [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
ruby: Assert for x86 misaligned access
This patch ensures only aligned access are passed to ruby and includes a fix
to the DPRINTF address print.
Brad Beckmann [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
ruby: x86 fs config support
Brad Beckmann [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
MOESI_hammer: Added full-bit directory support
Joel Hestness [Mon, 7 Feb 2011 06:14:18 +0000 (22:14 -0800)]
x86: Add checkpointing capability to devices
Add checkpointing capability to the Intel 8254 timer, CMOS, I8042,
PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker
devices
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
x86: Add checkpointing capability to arch components
Add checkpointing capability to the x86 interrupt device and the TLBs
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
x86: implements vtophys
Calls walker to look up virt. to phys. page mapping
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
IntDev: packet latency fix
The x86 local apic now includes a separate latency parameter for interrupts.
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
MessagePort: implement the virtual recvTiming function to avoid double pkt delete
Double packet delete problem is due to an interrupt device deleting a packet that the SimpleTimingPort also deletes. Since MessagePort descends from SimpleTimingPort, simply reimplement the failing code from SimpleTimingPort: recvTiming.
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
MOESI_hammer: trigge queue fix.
Joel Hestness [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters for
McPAT
Tushar Krishna [Mon, 7 Feb 2011 06:14:17 +0000 (22:14 -0800)]
garnet: added orion2.0 for network power calculation
Tushar Krishna [Mon, 7 Feb 2011 06:14:16 +0000 (22:14 -0800)]
garnet: separate data and ctrl VCs
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC,
while data VCs have > 1 buffers per VC. This is for correct power estimations.
Brad Beckmann [Mon, 7 Feb 2011 06:14:16 +0000 (22:14 -0800)]
x86: set IsCondControl flag for the appropriate microops
Gabe Black [Sat, 5 Feb 2011 08:16:09 +0000 (00:16 -0800)]
X86: Add o3 regressions in SE mode.
Exclude bzip2 for now. It works, it just takes too long to run.
Gabe Black [Fri, 4 Feb 2011 11:47:23 +0000 (03:47 -0800)]
X86: Update ruby stats for stupd change.
Gabe Black [Fri, 4 Feb 2011 06:07:34 +0000 (22:07 -0800)]
Fault: Forgot to refresh to grab these header guard updates.
Korey Sewell [Fri, 4 Feb 2011 05:09:22 +0000 (00:09 -0500)]
imported patch regression_updates
Korey Sewell [Fri, 4 Feb 2011 05:09:20 +0000 (00:09 -0500)]
inorder: fault handling
Maintain all information about an instruction's fault in the DynInst object rather
than any cpu-request object. Also, if there is a fault during the execution stage
then just save the fault inside the instruction and trap once the instruction
tries to graduate
Korey Sewell [Fri, 4 Feb 2011 05:09:19 +0000 (00:09 -0500)]
inorder: pcstate and delay slots bug
not taken delay slots were not being advanced correctly to pc+8, so for those ISAs
we 'advance()' the pcstate one more time for the desired effect
Korey Sewell [Fri, 4 Feb 2011 05:08:22 +0000 (00:08 -0500)]
inorder: add a fetch buffer to fetch unit
Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient
(architecturally and in simulation) to continually fetch at the granularity of the
wordsize. As expected, the number of fetch memory requests drops dramatically
Korey Sewell [Fri, 4 Feb 2011 05:08:21 +0000 (00:08 -0500)]
inorder: overload find-req fn
no need to have separate function name findSplitRequest, just overload the function
Korey Sewell [Fri, 4 Feb 2011 05:08:20 +0000 (00:08 -0500)]
inorder: implement separate fetch unit
instead of having one cache-unit class be responsible for both data and code
accesses, separate code that is just for fetch in it's own derived class off the
original base class. This makes the code easier to manage as well as handle
future cases of special fetch handling
Korey Sewell [Fri, 4 Feb 2011 05:08:19 +0000 (00:08 -0500)]
inorder: cache port blocking
set the request to false when the cache port blocks so we dont deadlock.
also, comment out the outstanding address list sanity check for now.
Korey Sewell [Fri, 4 Feb 2011 05:08:18 +0000 (00:08 -0500)]
inorder: stage width as a python parameter
allow the user to specify how many instructions a pipeline stage can process
on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through
the python interface rather than compile the code after changing the *.cc file.
(we always had the parameter there, but still used the static 'ThePipeline::StageWidth'
instead)
-
Since StageWidth is now dynamically defined, change the interstage communication
structure to use a vector and get rid of array and array handling index (toNextStageIndex)
since we can just make calls to the list for the same information
Korey Sewell [Fri, 4 Feb 2011 05:08:17 +0000 (00:08 -0500)]
inorder: multi-issue branch resolution
Only execute (resolve) one branch per cycle because handling more than one is
a little more complicated
Korey Sewell [Fri, 4 Feb 2011 05:08:16 +0000 (00:08 -0500)]
inorder: pipe. stage inst. buffering
use skidbuffer as only location for instructions between stages. before,
we had the insts queue from the prior stage and the skidbuffer for the
current stage, but that gets confusing and this consolidation helps
when handling squash cases
Korey Sewell [Fri, 4 Feb 2011 05:08:15 +0000 (00:08 -0500)]
inorder: change skidBuffer to list instead of queue
manage insertion and deletion like a queue but will need
access to internal elements for future changes
Currently, skidbuffer manages any instruction that was
in a stage but could not complete processing, however
we will want to manage all blocked instructions (from prev stage
and from cur. stage) in just one buffer.
Korey Sewell [Fri, 4 Feb 2011 05:08:13 +0000 (00:08 -0500)]
inorder: activity tracking bug
Previous code was marking CPU activity on almost every cycle due to a bug in
tracking the status of pipeline stages. This disables the CPU from sleeping
on long latency stalls and increases simulation time
Gabe Black [Fri, 4 Feb 2011 05:47:58 +0000 (21:47 -0800)]
Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
--HG--
rename : src/sim/fault.hh => src/sim/fault_fwd.hh
Gabe Black [Fri, 4 Feb 2011 04:56:27 +0000 (20:56 -0800)]
Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
Gabe Black [Fri, 4 Feb 2011 04:23:00 +0000 (20:23 -0800)]
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
Gabe Black [Thu, 3 Feb 2011 07:34:14 +0000 (23:34 -0800)]
O3: Fix a style bug in O3.
Gabe Black [Thu, 3 Feb 2011 03:57:12 +0000 (19:57 -0800)]
X86: Get rid of the stupd microop.
Gabe Black [Thu, 3 Feb 2011 03:56:49 +0000 (19:56 -0800)]
Stats: Update the x86 stats to reflect changing stupd to a store and update.
Gabe Black [Thu, 3 Feb 2011 03:56:38 +0000 (19:56 -0800)]
X86: Replace the stupd microop with a store/update sequence.
Gabe Black [Thu, 3 Feb 2011 02:17:16 +0000 (18:17 -0800)]
X86: Build O3 by default in SE.
Gabe Black [Thu, 3 Feb 2011 02:05:03 +0000 (18:05 -0800)]
Time: Add serialization functions to the Time class.
Gabe Black [Thu, 3 Feb 2011 02:03:58 +0000 (18:03 -0800)]
X86: Change how the default disk image gets set up.
The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.
Gabe Black [Wed, 2 Feb 2011 02:28:41 +0000 (18:28 -0800)]
X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
Gabe Black [Mon, 31 Jan 2011 21:13:00 +0000 (13:13 -0800)]
Fault: Move the definition of NoFault from faults.hh to fault.hh.
Moving the definition of NoFault into fault.hh doesn't bring any new
dependencies with it, and allows some files to include just fault.hh which has
less baggage. NoFault will still be available to everything that includes
faults.hh because it includes fault.hh.
Nathan Binkert [Sun, 23 Jan 2011 05:48:06 +0000 (21:48 -0800)]
refcnt: Change things around so that we handle constness correctly.
To use a non const pointer:
typedef RefCountingPtr<Foo> FooPtr;
To use a const pointer:
typedef RefCountingPtr<const Foo> ConstFooPtr;
Gabe Black [Sat, 22 Jan 2011 01:51:22 +0000 (17:51 -0800)]
SConstruct: Fix the librt check in SConstruct.
Steve Reinhardt [Fri, 21 Jan 2011 06:13:33 +0000 (22:13 -0800)]
checkpointing: fix bug from curTick accessor conversion.
Regex replacement of curTick with curTick() accidentally
changed checkpoint key string for serialization but not
for unserialization.
Gabe Black [Thu, 20 Jan 2011 00:22:23 +0000 (16:22 -0800)]
TimeSync: Use the new setTick and getTick functions.
Gabe Black [Thu, 20 Jan 2011 00:22:15 +0000 (16:22 -0800)]
Time: Add setTick and getTick functions to the Time class.
Gabe Black [Wed, 19 Jan 2011 19:48:00 +0000 (11:48 -0800)]
Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.
This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.
A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
Ali Saidi [Tue, 18 Jan 2011 22:30:06 +0000 (16:30 -0600)]
ARM/O3: Add regressions for ARM w/ O3 CPU.
Ali Saidi [Tue, 18 Jan 2011 22:30:06 +0000 (16:30 -0600)]
Stats: Update stats for previous set of patches.
Matt Horsnell [Tue, 18 Jan 2011 22:30:05 +0000 (16:30 -0600)]
O3: Fix itstate prediction and recovery.
Any change of control flow now resets the itstate to 0 mask and 0 condition,
except where the control flow alteration write into the cpsr register. These
case, for example return from an iterrupt, require the predecoder to recover
the itstate.
As there is a window of opportunity between the return from an interrupt
changing the control flow at the head of the pipe and the commit of the update
to the CPSR, the predecoder needs to be able to grab the ITstate early. This
is now handled by setting the forcedItState inside a PCstate for the control
flow altering instruction.
That instruction will have the correct mask/cond, but will not have a valid
itstate until advancePC is called (note this happens to advance the execution).
When the new PCstate is copy constructed it gets the itstate cond/mask, and
upon advancing the PC the itstate becomes valid.
Subsequent advancing invalidates the state and zeroes the cond/mask. This is
handled in isolation for the ARM ISA and should have no impact on other ISAs.
Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.
Matt Horsnell [Tue, 18 Jan 2011 22:30:05 +0000 (16:30 -0600)]
O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.
Matt Horsnell [Tue, 18 Jan 2011 22:30:05 +0000 (16:30 -0600)]
O3: Don't test misprediction on load instructions until executed.
Ali Saidi [Tue, 18 Jan 2011 22:30:05 +0000 (16:30 -0600)]
O3: Keep around the last committed instruction and use for squashing.
Without this change 0 is always used for the youngest sequence number if
a squash occured and the ROB was empty (E.g. an instruction is marked
serializeAfter or a fetch stall prevents other instructions from issuing).
Using 0 there is a race to rename where an instruction that committed the
same cycle as the squashing instruction can have it's renamed state undone
by the squash using sequence number 0.
Ali Saidi [Tue, 18 Jan 2011 22:30:05 +0000 (16:30 -0600)]
O3: Don't try to scoreboard misc registers.
I'm not positive this is the correct fix, but it's working right now.
Either we need to do something like this, prevent the misc reg from being renamed at all,
or there something else going on. We need to find the root cause as to why
this is only a problem sometimes.