Xiretza [Fri, 19 Jun 2020 09:46:06 +0000 (11:46 +0200)]
Add missing [[noreturn]] to log_file_error()
Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173, resulting in warnings in
frontends/ast/simplify.cc:
frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
whitequark [Fri, 19 Jun 2020 06:15:33 +0000 (06:15 +0000)]
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
whitequark [Fri, 19 Jun 2020 06:09:42 +0000 (06:09 +0000)]
Merge pull request #2174 from whitequark/fix-github-linguist
Fix GitHub misidentifying *.v files as Coq
whitequark [Fri, 19 Jun 2020 06:08:18 +0000 (06:08 +0000)]
Fix GitHub misidentifying *.v files as Coq.
whitequark [Fri, 19 Jun 2020 03:52:29 +0000 (03:52 +0000)]
Merge pull request #2171 from whitequark/cxxrtl-accessors
cxxrtl: add .get() and .set() accessors on value<> and wire<>
whitequark [Thu, 18 Jun 2020 21:51:30 +0000 (21:51 +0000)]
cxxrtl: add .get() and .set() accessors on value<> and wire<>.
For several reasons:
* They're more convenient than accessing .data.
* They accommodate variably-sized types like size_t transparently.
* They statically ensure that no out of range conversions happen.
For now these are only provided for unsigned integers, but eventually
they should be provided for signed integers too. (Annoyingly this
affects conversions to/from `char` at the moment.)
Fixes #2127.
whitequark [Fri, 19 Jun 2020 01:13:19 +0000 (01:13 +0000)]
Merge pull request #2170 from boqwxp/cutpoint-efficiency
cutpoint: Improve efficiency by iterating over module ports instead of module wires
whitequark [Fri, 19 Jun 2020 01:05:59 +0000 (01:05 +0000)]
Use C++11 [[noreturn]] attribute.
whitequark [Thu, 18 Jun 2020 23:34:52 +0000 (23:34 +0000)]
Use C++11 final/override keywords.
Alberto Gonzalez [Thu, 18 Jun 2020 17:42:36 +0000 (17:42 +0000)]
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
N. Engelhardt [Thu, 18 Jun 2020 17:16:55 +0000 (19:16 +0200)]
Merge pull request #2153 from boqwxp/splitnets-cleanup
splitnets: Cleanup and efficiency improvements
whitequark [Thu, 18 Jun 2020 16:57:51 +0000 (16:57 +0000)]
Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug
cxxrtl: don't compute vital values in log_assert()
whitequark [Thu, 18 Jun 2020 16:57:24 +0000 (16:57 +0000)]
Merge pull request #2142 from whitequark/splitnets-hdlname
splitnets: propagate (*hdlname*) and disambiguate via start_offset
Miodrag Milanović [Thu, 18 Jun 2020 10:44:21 +0000 (12:44 +0200)]
Merge pull request #2164 from madebr/msvc
Get yosys building on Visual Studio
whitequark [Wed, 17 Jun 2020 19:27:47 +0000 (19:27 +0000)]
cxxrtl: don't compute vital values in log_assert().
This breaks NDEBUG builds.
Fixes #2166.
Anonymous Maarten [Wed, 17 Jun 2020 11:53:57 +0000 (13:53 +0200)]
msvc does not support designated initializers in structs
Anonymous Maarten [Wed, 17 Jun 2020 11:52:45 +0000 (13:52 +0200)]
MSVC does not understand __builtin_unreachable
Anonymous Maarten [Wed, 17 Jun 2020 11:51:02 +0000 (13:51 +0200)]
MSVC cannot omit operand in conditional
Anonymous Maarten [Wed, 17 Jun 2020 13:08:55 +0000 (15:08 +0200)]
MSVC defines TRANSPARENT too
whitequark [Wed, 17 Jun 2020 06:07:41 +0000 (06:07 +0000)]
Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo
cxxrtl: restrict the debug info of a blackbox to its ports.
whitequark [Wed, 17 Jun 2020 06:06:58 +0000 (06:06 +0000)]
Merge pull request #2160 from whitequark/cxxrtl-fix-warning
cxxrtl: avoid unused variable warning for transparent $memrd ports
Jean-François Nguyen [Tue, 16 Jun 2020 13:28:35 +0000 (15:28 +0200)]
cxxrtl: restrict the debug info of a blackbox to its ports.
N. Engelhardt [Tue, 16 Jun 2020 10:31:34 +0000 (12:31 +0200)]
Merge pull request #2156 from XarkLabs/master
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
whitequark [Mon, 15 Jun 2020 06:08:17 +0000 (06:08 +0000)]
Merge pull request #2159 from MerryMage/cxxrtl-mul
cxxrtl: Implement chunk-wise multiplication
whitequark [Sun, 14 Jun 2020 05:42:52 +0000 (05:42 +0000)]
cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.
MerryMage [Sun, 14 Jun 2020 14:52:43 +0000 (15:52 +0100)]
cxxrtl: Implement chunk-wise multiplication
whitequark [Mon, 15 Jun 2020 01:37:05 +0000 (01:37 +0000)]
Merge pull request #2158 from miek/sshr-sign-extension
cxxrtl: fix sshr sign-extension.
Mike Walters [Sun, 14 Jun 2020 13:42:20 +0000 (14:42 +0100)]
cxxrtl: fix sshr sign-extension.
Xark [Sun, 14 Jun 2020 07:45:22 +0000 (00:45 -0700)]
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
whitequark [Sat, 13 Jun 2020 23:28:18 +0000 (23:28 +0000)]
Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11
kernel: guard include of signal.h more precisely
whitequark [Sat, 13 Jun 2020 22:37:04 +0000 (22:37 +0000)]
kernel: guard include of signal.h more precisely.
Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
whitequark [Sat, 13 Jun 2020 22:18:35 +0000 (22:18 +0000)]
Merge pull request #2151 from whitequark/cxxrtl-fix-rzext
cxxrtl: fix rzext()
Alberto Gonzalez [Sat, 13 Jun 2020 05:47:55 +0000 (05:47 +0000)]
splitnets: Clean up pseudo-private member usage
Alberto Gonzalez [Sat, 13 Jun 2020 05:26:30 +0000 (05:26 +0000)]
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
whitequark [Sat, 13 Jun 2020 04:23:22 +0000 (04:23 +0000)]
Merge pull request #2145 from whitequark/cxxrtl-splitnets
cxxrtl: handle multipart signals
whitequark [Sat, 13 Jun 2020 04:17:49 +0000 (04:17 +0000)]
Merge pull request #2152 from whitequark/cxxrtl-always-inline
cxxrtl: always inline internal cells and slice/concat operations
whitequark [Sat, 13 Jun 2020 01:50:53 +0000 (01:50 +0000)]
cxxrtl: always inline internal cells and slice/concat operations.
This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.
whitequark [Sat, 13 Jun 2020 00:49:44 +0000 (00:49 +0000)]
cxxrtl: fix rzext().
This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
whitequark [Fri, 12 Jun 2020 08:50:57 +0000 (08:50 +0000)]
Merge pull request #2150 from whitequark/cxxrtl-elide-pmux
cxxrtl: elide $pmux cells
whitequark [Fri, 12 Jun 2020 02:40:30 +0000 (02:40 +0000)]
cxxrtl: elide $pmux cells.
On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
whitequark [Fri, 12 Jun 2020 01:59:35 +0000 (01:59 +0000)]
Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs
cxxrtl: unbuffer output wires of toplevel module
whitequark [Fri, 12 Jun 2020 00:35:18 +0000 (00:35 +0000)]
cxxrtl: annotate port direction as comments.
whitequark [Fri, 12 Jun 2020 00:05:05 +0000 (00:05 +0000)]
cxxrtl: unbuffer output wires of toplevel module.
Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.
This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
whitequark [Thu, 11 Jun 2020 22:21:30 +0000 (22:21 +0000)]
cxxrtl: simplify unbuffering of input wires.
This also fixes an edge case with (*keep*) input ports.
whitequark [Thu, 11 Jun 2020 13:31:16 +0000 (13:31 +0000)]
cxxrtl: handle multipart signals.
This avoids losing design visibility when using the `splitnets` pass.
Dan Ravensloft [Thu, 11 Jun 2020 17:06:39 +0000 (18:06 +0100)]
intel_alm: fix DFFE matching
whitequark [Thu, 11 Jun 2020 12:42:37 +0000 (12:42 +0000)]
cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.
whitequark [Wed, 10 Jun 2020 19:59:08 +0000 (19:59 +0000)]
splitnets: propagate (*hdlname*) and disambiguate via start_offset.
This allows reliably coalescing the split wires later.
whitequark [Wed, 10 Jun 2020 17:10:15 +0000 (17:10 +0000)]
Merge pull request #2141 from whitequark/cxxrtl-cxx11
cxxrtl: various compiler compatibility fixes
whitequark [Wed, 10 Jun 2020 16:09:27 +0000 (16:09 +0000)]
Merge pull request #2140 from whitequark/cxxrtl-aliases
cxxrtl: disambiguate values/wires and their aliases in debug info
whitequark [Wed, 10 Jun 2020 15:49:28 +0000 (15:49 +0000)]
cxxrtl: restore C++11 compatibility.
This is necessary to be able to build CXXRTL models via yosys-config.
whitequark [Wed, 10 Jun 2020 15:57:01 +0000 (15:57 +0000)]
cxxrtl: fix a few gcc warnings.
whitequark [Wed, 10 Jun 2020 15:48:40 +0000 (15:48 +0000)]
Fix formatting. NFC.
whitequark [Wed, 10 Jun 2020 14:39:45 +0000 (14:39 +0000)]
cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
whitequark [Wed, 10 Jun 2020 11:51:04 +0000 (11:51 +0000)]
Merge pull request #2134 from whitequark/cxxrtl-opt-debug
cxxrtl: introduce -Og optimization level
clairexen [Wed, 10 Jun 2020 10:44:23 +0000 (12:44 +0200)]
Merge pull request #2131 from YosysHQ/claire/preserveffs
Do not optimize away FFs in "prep" and Verific front-end
clairexen [Wed, 10 Jun 2020 10:42:43 +0000 (12:42 +0200)]
Merge pull request #2139 from YosysHQ/verific_missing_memory
verific - detect missing memory to prevent crash.
Miodrag Milanovic [Wed, 10 Jun 2020 09:27:44 +0000 (11:27 +0200)]
verific - detect missing memory to prevent crash.
whitequark [Tue, 9 Jun 2020 21:50:09 +0000 (21:50 +0000)]
cxxrtl: allow unbuffering without localizing.
Although logically two separate steps, these were treated as one for
historic reasons. Splitting the two makes it possible to have designs
that are only 2× slower than fastest possible (and are without extra
delta cycles) that allow probing all public wires.
whitequark [Tue, 9 Jun 2020 20:55:40 +0000 (20:55 +0000)]
cxxrtl: order -On levels as localize, elide instead of the reverse.
Historically, elision was implemented before localization, so levels
with elision are lower than corresponding levels with localization.
This is unfortunate for two reasons:
1. Elision is a logical subset of localization, since it equals to
not giving a name to a temporary.
2. "Localize" currently actually means "unbuffer and localize",
and it would be useful to split those steps (at least for
public wires) for improved design visibility.
Claire Wolf [Tue, 9 Jun 2020 17:14:36 +0000 (19:14 +0200)]
Fix tests/opt/opt_rmdff
This only passed before because "prep" was also running opt_rmdff
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Tue, 9 Jun 2020 19:49:43 +0000 (21:49 +0200)]
Drive-by modernization in sat.cc
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
whitequark [Tue, 9 Jun 2020 20:18:07 +0000 (20:18 +0000)]
cxxrtl: factor out -noproc/-noflatten from -O.
Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.
clairexen [Tue, 9 Jun 2020 16:27:59 +0000 (18:27 +0200)]
Merge pull request #2112 from YosysHQ/claire/fix2040
Add latch detection for use_case_method in part-select write
Claire Wolf [Tue, 9 Jun 2020 13:54:14 +0000 (15:54 +0200)]
Do not optimize away FFs in "prep" and Verific fron-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
whitequark [Tue, 9 Jun 2020 12:41:02 +0000 (12:41 +0000)]
Merge pull request #2128 from whitequark/flatten-processes
flatten: accept processes
whitequark [Tue, 9 Jun 2020 11:59:17 +0000 (11:59 +0000)]
Merge pull request #2130 from whitequark/cxxrtl-fix-split_by
cxxrtl: fix two buggy split_by functions
whitequark [Tue, 9 Jun 2020 11:05:35 +0000 (11:05 +0000)]
cxxrtl: fix two buggy split_by functions.
whitequark [Tue, 9 Jun 2020 09:56:23 +0000 (09:56 +0000)]
flatten: accept processes.
whitequark [Tue, 9 Jun 2020 09:55:48 +0000 (09:55 +0000)]
RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.
whitequark [Tue, 9 Jun 2020 09:54:09 +0000 (09:54 +0000)]
Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
cxxrtl: ignore cell input signedness when it is irrelevant
whitequark [Tue, 9 Jun 2020 07:52:27 +0000 (07:52 +0000)]
Merge pull request #2125 from whitequark/cxxrtl-fix-namespace
cxxrtl: add missing namespace
whitequark [Tue, 9 Jun 2020 07:26:13 +0000 (07:26 +0000)]
cxxrtl: ignore cell input signedness when it is irrelevant.
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
whitequark [Tue, 9 Jun 2020 06:26:17 +0000 (06:26 +0000)]
cxxrtl: add missing namespace.
Fixes #2124.
whitequark [Tue, 9 Jun 2020 06:26:02 +0000 (06:26 +0000)]
Merge pull request #2107 from whitequark/flatten-hdlname
flatten: preserve original object names
whitequark [Mon, 8 Jun 2020 19:50:09 +0000 (19:50 +0000)]
cxxrtl: fix format of hdlnames.
The CXXRTL code that handled the `hdlname` attribute implemented
outdated semantics.
whitequark [Thu, 4 Jun 2020 10:46:54 +0000 (10:46 +0000)]
flatten: preserve original object names via hdlname attribute.
whitequark [Mon, 8 Jun 2020 19:18:11 +0000 (19:18 +0000)]
flatten: only prepend $flatten once per wire.
whitequark [Mon, 8 Jun 2020 19:02:48 +0000 (19:02 +0000)]
RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.
The only difference in behavior is that this removes the attribute
when the pool becomes empty.
whitequark [Mon, 8 Jun 2020 20:19:18 +0000 (20:19 +0000)]
Merge pull request #2120 from whitequark/flatten-hygiene
flatten: make hygienic
whitequark [Thu, 4 Jun 2020 10:13:48 +0000 (10:13 +0000)]
flatten: make hygienic.
Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:
module bar();
$dff a();
endmodule
module foo();
bar b();
$dff \b.a ();
endmodule
After this commit, `flatten` avoids every possible case of name
collision.
Fixes #2106.
whitequark [Mon, 8 Jun 2020 18:24:32 +0000 (18:24 +0000)]
Merge pull request #2121 from whitequark/cxxrtl-debug-aliases
cxxrtl: improve design visibility
whitequark [Mon, 8 Jun 2020 17:38:11 +0000 (17:38 +0000)]
cxxrtl: don't check immutable values for changes in VCD writer.
This commit changes the VCD writer such that for all signals that
have `debug_item.type == VALUE && debug_item.next == nullptr`, it
would only sample the value once.
Commit
f2d7a187 added more debug information by including constant
wires, and decreased the performance of VCD writer proportionally
because the constant wires were still repeatedly sampled; this commit
eliminates the performance hit.
whitequark [Mon, 8 Jun 2020 17:29:08 +0000 (17:29 +0000)]
cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
whitequark [Mon, 8 Jun 2020 16:36:26 +0000 (16:36 +0000)]
cxxrtl: track aliases in VCD writer.
This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.
Commit
9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
whitequark [Mon, 8 Jun 2020 16:22:30 +0000 (16:22 +0000)]
cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
clairexen [Mon, 8 Jun 2020 13:55:52 +0000 (15:55 +0200)]
Merge pull request #2085 from rswarbrick/select
Silence warning in select.cc and pass some more args by ref
clairexen [Mon, 8 Jun 2020 13:48:11 +0000 (15:48 +0200)]
Merge pull request #2089 from rswarbrick/modports
Simplify a modport check in hierarchy.cc
clairexen [Mon, 8 Jun 2020 13:27:15 +0000 (15:27 +0200)]
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
clairexen [Mon, 8 Jun 2020 13:22:09 +0000 (15:22 +0200)]
Merge pull request #2117 from PeterCrozier/struct_array
Support packed arrays in struct/union.
clairexen [Mon, 8 Jun 2020 13:18:32 +0000 (15:18 +0200)]
Merge pull request #2119 from YosysHQ/mwk/fix-fsm-idstring
fsm_extract: avoid calling log_signal to determine wire name
whitequark [Mon, 8 Jun 2020 12:55:11 +0000 (12:55 +0000)]
cxxrtl: add missing installs of include files.
whitequark [Mon, 8 Jun 2020 04:08:09 +0000 (04:08 +0000)]
cxxrtl: fix typo in comment. NFC.
whitequark [Mon, 8 Jun 2020 03:21:08 +0000 (03:21 +0000)]
cxxrtl: minor debug-related improvements.
Marcelina Kościelnicka [Mon, 8 Jun 2020 01:48:09 +0000 (03:48 +0200)]
fsm_extract: avoid calling log_signal to determine wire name
log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
whitequark [Sun, 7 Jun 2020 20:32:00 +0000 (20:32 +0000)]
Merge pull request #2116 from whitequark/cxxrtl-vcd
cxxrtl: add a VCD writer using debug information
Peter Crozier [Sun, 7 Jun 2020 17:28:45 +0000 (18:28 +0100)]
Support packed arrays in struct/union.
whitequark [Sun, 7 Jun 2020 03:48:40 +0000 (03:48 +0000)]
cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
whitequark [Sun, 7 Jun 2020 03:45:53 +0000 (03:45 +0000)]
cxxrtl: add a C API for writing VCD dumps.
This C API is fully featured.
whitequark [Sat, 6 Jun 2020 21:55:53 +0000 (21:55 +0000)]
cxxrtl: only write VCD values that were actually updated.
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.