git.libre-soc.org Git

PR90374 Zero width format specifiers.

PR libfortran/90374
* io/format.c (parse_format_list): Zero width not allowed with
FMT_D.
* io/write_float.def (build_float_string): Include range of
higher exponent values that require wider width.

Add testcase of PR c++/92542, already fixed.

PR c++/92542
* g++.dg/pr92542.C: New.

[GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline

This patch is adding the following instructions:

ASRL (imm)
LSLL (imm)
LSRL (imm)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
and valid immediate.
(ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
(lshrdi3): Generate thumb2_lsrl for valid immediates.
* config/arm/constraints.md (Pg): New.
* config/arm/predicates.md (long_shift_imm): New.
(arm_reg_or_long_shift_imm): Likewise.
* config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
(thumb2_lsll): Likewise.
(thumb2_lsrl): New.

*** gcc/testsuite/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* gcc.target/arm/armv8_1m-shift-imm_1.c: New test.

[GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline

This patch is adding the following instructions:

ASRL (reg)
LSLL (reg)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
(ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
* config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
register pairs for doubleword quantities for ARMv8.1M-Mainline.
* config/arm/thumb2.md (thumb2_asrl): New.
(thumb2_lsll): Likewise.

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.

Fix up ChangeLog.

arm: Unbreak bootstrap

2020-01-17 Jakub Jelinek <jakub@redhat.com>

* config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
unused variable.

Rename acc_device_gcn to acc_device_radeon

2020-01-17 Andrew Stubbs <ams@codesourcery.com>

libgomp/
* config/accel/openacc.f90 (openacc_kinds): Rename acc_device_gcn to
acc_device_radeon.
(openacc): Likewise.
* openacc.f90 (openacc_kinds): Likewise.
(openacc): Likewise.
* openacc.h (acc_device_t): Likewise.
* openacc_lib.h: Likewise.
* testsuite/lib/libgomp.exp
(check_effective_target_openacc_amdgcn_accel_present): Likewise.
* testsuite/libgomp.oacc-c-c++-common/acc_prof-init-1.c
(cb_compute_construct_end): Likewise.
* testsuite/libgomp.oacc-c-c++-common/acc_prof-kernels-1.c
(cb_enqueue_launch_start): Likewise.
* testsuite/libgomp.oacc-c-c++-common/acc_prof-parallel-1.c
(cb_enter_data_end): Likewise.
(cb_exit_data_start): Likewise.
(cb_exit_data_end): Likewise.
(cb_compute_construct_end): Likewise.
(cb_enqueue_launch_start): Likewise.
(cb_enqueue_launch_end): Likewise.
* testsuite/libgomp.oacc-c-c++-common/asyncwait-nop-1.c
(main): Likewise.

libstdc++: Fix freestanding build PR 92376)

In a freestanding library we don't install the <pstl/pstl_config.h>
header, so don't try to include it unless it exists.

Explicitly declare aligned alloc functions for freestanding, because
<cstdlib> doesn't declare them.

PR libstdc++/92376
* include/bits/c++config: Only do PSTL config when the header is
present, to fix freestanding.
* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Declare allocation
functions if they were detected by configure.

gdbinit.in: make shorthands accept an explicit argument

Make gdb shorthands such as 'pr' accept an argument, in addition to
implictly taking register '$' as the thing to examine.

The 'eval ...' one-liners are used to workaround GDB bug #22466.

* gdbinit.in (help-gcc-hooks): New command.
(pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
documentation.

[AArch64] [Obvious] Correct pattern target requirement

Had mistakenly used a target macro that was not defined and not the
relevant one instead of the macro that should be used.

TARGET_ARMV8_6 is not defined, and also not the macro we want to check.
Instead check TARGET_F64MM.

gcc/ChangeLog:

2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>

* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
the correct target macro.

Fix g++ testsuite failure caused by std::is_pod deprecation

PR testsuite/93227
* g++.dg/cpp0x/std-layout1.C: Use -Wno-deprecated-declarations for
C++20, due to std::is_pod being deprecated.

[AArch64] [SVE] Implement svld1ro intrinsic.

We take no action to ensure the SVE vector size is large enough.  It is
left to the user to check that before compiling this intrinsic or before
running such a program on a machine.

The main difference between ld1ro and ld1rq is in the allowed offsets,
the implementation difference is that ld1ro is implemented using integer
modes since there are no pre-existing vector modes of the relevant size.
Adding new vector modes simply for this intrinsic seems to make the code
less tidy.

Specifications can be found under the "Arm C Language Extensions for
Scalable Vector Extension" title at
https://developer.arm.com/architectures/system-architectures/software-standards/acle

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

* config/aarch64/aarch64-protos.h
(aarch64_sve_ld1ro_operand_p): New.
* config/aarch64/aarch64-sve-builtins-base.cc
(class load_replicate): New.
(class svld1ro_impl): New.
(class svld1rq_impl): Change to inherit from load_replicate.
(svld1ro): New sve intrinsic function base.
* config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
New DEF_SVE_FUNCTION.
* config/aarch64/aarch64-sve-builtins-base.h
(svld1ro): New decl.
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::add_mem_operand): Modify assert to allow
OImode.
* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
pattern.
* config/aarch64/aarch64.c
(aarch64_sve_ld1rq_operand_p): Implement in terms of ...
(aarch64_sve_ld1rq_ld1ro_operand_p): This.
(aarch64_sve_ld1ro_operand_p): New.
* config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
* config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
* config/aarch64/predicates.md
(aarch64_sve_ld1ro_operand_{b,h,w,d}): New.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

* gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: New test.
* gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: New test.

[AArch64] Enable CLI for Armv8.6-A f64mm

This patch is necessary for sve-ld1ro intrinsic I posted in
https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .

I had mistakenly thought this option was already enabled upstream.

This provides the option +f64mm, that turns on the 64 bit floating point
matrix multiply extension.  This extension is only available for
AArch64.  Turning on this extension also turns on the SVE extension.

This extension is optional and only available at Armv8.2-A and onward.

We also add the ACLE defined macro for this extension.

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

* config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
Introduce this ACLE specified predefined macro.
* config/aarch64/aarch64-option-extensions.def (f64mm): New.
(fp): Disabling this disables f64mm.
(simd): Disabling this disables f64mm.
(fp16): Disabling this disables f64mm.
(sve): Disabling this disables f64mm.
* config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
(AARCH64_ISA_F64MM): New.
(TARGET_F64MM): New.
* doc/invoke.texi (f64mm): Document new option.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

* gcc.target/aarch64/pragma_cpp_predefs_2.c: Check for f64mm
predef.

[AArch64] Enable compare branch fusion

Enable the most basic form of compare-branch fusion since various CPUs
support it. This has no measurable effect on cores which don't support
branch fusion, but increases fusion opportunities on cores which do.

gcc/
* config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
(neoversen1_tunings): Likewise.

PR c++/92531 - ICE with noexcept(lambda).

This was failing because uses_template_parms didn't recognize LAMBDA_EXPR as
a kind of expression. Instead of trying to enumerate all the different
varieties of expression and then aborting if what's left isn't
error_mark_node, let's handle error_mark_node and then assume anything else
is an expression.

* pt.c (uses_template_parms): Don't try to enumerate all the
expression cases.

c++: Fix deprecated attribute handling on templates (PR c++/93228)

As the following testcase shows, when deprecated attribute is on a template,
we'd never print the message if any, because the attribute is not
present on the TEMPLATE_DECL with which warn_deprecated_use is called,
but on its DECL_TEMPLATE_RESULT or its type.

2020-01-17 Jakub Jelinek <jakub@redhat.com>

PR c++/93228
* parser.c (cp_parser_template_name): Look up deprecated attribute
in DECL_TEMPLATE_RESULT or its type's attributes.

* g++.dg/cpp1y/attr-deprecated-3.C: New test.

[PR93306] Short-circuit has_include

the preprocessor evaluator has a skip_eval counter, but we weren't
checking it after parsing has_include(foo), but before looking for
foo. Resulting in unnecessary io for 'FALSE_COND && has_include <foo>'

PR preprocessor/93306
* expr.c (parse_has_include): Refactor. Check skip_eval before
looking.

analyzer: fix handling of negative byte offsets (v2) (PR 93281)

Various 32-bit targets show failures in gcc.dg/analyzer/data-model-1.c
with tests of the form:
  __analyzer_eval (q[-2].x == 107024); /* { dg-warning "TRUE" } */
  __analyzer_eval (q[-2].y == 107025); /* { dg-warning "TRUE" } */
where they emit UNKNOWN instead.

The root cause is that gimple has a byte-based twos-complement offset
of -16 expressed like this:
  _55 = q_92 + 4294967280;  (32-bit)
or:
  _55 = q_92 + 18446744073709551600; (64-bit)

Within region_model::convert_byte_offset_to_array_index that unsigned
offset was being divided by the element size to get an offset within
an array.

This happened to work on 64-bit target and host, but not elsewhere;
the offset needs to be converted to a signed type before the division
is meaningful.

This patch does so, fixing the failures.

gcc/analyzer/ChangeLog:
PR analyzer/93281
* region-model.cc
(region_model::convert_byte_offset_to_array_index): Convert to
ssizetype before dividing by byte_size.  Use fold_binary rather
than fold_build2 to avoid needlessly constructing a tree for the
non-const case.

[AArch64] Fix shrinkwrapping interactions with atomics (PR92692)

The separate shrinkwrapping pass may insert stores in the middle
of atomics loops which can cause issues on some implementations.
Avoid this by delaying splitting atomics patterns until after
prolog/epilog generation.

gcc/
PR target/92692
* config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
Add assert to ensure prolog has been emitted.
(aarch64_split_atomic_op): Likewise.
* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
Use epilogue_completed rather than reload_completed.
(aarch64_atomic_exchange<mode>): Likewise.
(aarch64_atomic_<atomic_optab><mode>): Likewise.
(atomic_nand<mode>): Likewise.
(aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.

Add PR number to change log

aarch64: Don't raise FE_INVALID for -__builtin_isgreater [PR93133]

AIUI, the main purpose of REVERSE_CONDITION is to take advantage of
any integer vs. FP information encoded in the CC mode, particularly
when handling LT, LE, GE and GT.  For integer comparisons we can
safely map LT->GE, LE->GT, GE->LT and GT->LE, but for float comparisons
this would usually be invalid without -ffinite-math-only.

The aarch64 definition of REVERSE_CONDITION used
reverse_condition_maybe_unordered for FP comparisons, which had the
effect of converting an unordered-signalling LT, LE, GE or GT into a
quiet UNGE, UNGT, UNLT or UNLE.  And it would do the same in reverse:
convert a quiet UN* into an unordered-signalling comparison.

This would be safe in practice (although a little misleading) if we
always used a compare:CCFP or compare:CCFPE to do the comparison and
then used (gt (reg:CCFP/CCFPE CC_REGNUM) (const_int 0)) etc. to test
the result.  In that case any signal is raised by the compare and the
choice of quiet vs. signalling relations doesn't matter when testing
the result.  The problem is that we also want to use GT directly on
float registers, where any signal is raised by the comparison operation
itself and so must follow the normal rtl rules (GT signalling,
UNLE quiet).

I think the safest fix is to make REVERSIBLE_CC_MODE return false
for FP comparisons.  We can then use the default REVERSE_CONDITION
for integer comparisons and the usual conservatively-correct
reversed_comparison_code_parts behaviour for FP comparisons.
Unfortunately reversed_comparison_code_parts doesn't yet handle
-ffinite-math-only, but that's probably GCC 11 material.

A downside is that:

    int f (float x, float y) { return !(x < y); }

now generates:

        fcmpe   s0, s1
        cset    w0, mi
        eor     w0, w0, 1
        ret

without -ffinite-math-only.  Maybe for GCC 11 we should define rtx
codes for all IEEE comparisons, so that we don't have this kind of
representational gap.

Changing REVERSE_CONDITION itself is pretty easy.  However, the macro
was also used in the ccmp handling, which relied on being able to
reverse all comparisons.  The patch adds new reversed patterns for
cases in which the original condition needs to be kept.

The test is based on gcc.dg/torture/pr91323.c.  It might well fail
on other targets that have similar bugs; please XFAIL as appropriate
if you don't want to fix the target for GCC 10.

2020-01-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
for FP modes.
(REVERSE_CONDITION): Delete.
* config/aarch64/iterators.md (CC_ONLY): New mode iterator.
(CCFP_CCFPE): Likewise.
(e): New mode attribute.
* config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
(@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
(fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
(@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
(@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
(@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
name of generator from gen_ccmpdi to gen_ccmpccdi.
(aarch64_gen_ccmp_next): Use code_for_ccmp.  If we want to reverse
the previous comparison but aren't able to, use the new ccmp_rev
patterns instead.

gimplifier: handle POLY_INT_CST-sized TARGET_EXPRs

If a TARGET_EXPR has poly-int size, the gimplifier would treat it
like a VLA and use gimplify_vla_decl.  gimplify_vla_decl in turn
would use an alloca and expect all references to be gimplified
via the DECL_VALUE_EXPR.  This caused confusion later in
gimplify_var_or_parm_decl_1 when we (correctly) had direct rather
than indirect references.

For completeness, the patch also fixes similar tests in the RETURN_EXPR
handling and OpenMP depend clauses.

2020-01-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
than testing directly for INTEGER_CST.
(gimplify_target_expr, gimplify_omp_depend): Likewise.

gcc/testsuite/
* g++.target/aarch64/sve/acle/general-c++/gimplify_1.C: New test.

PATCH] Fortran: PR93263 -fno-automatic and RECURSIVE

The use of -fno-automatic should not affect the save attribute of a
recursive procedure. The first test case checks unsaved variables
and the second checks saved variables.

vect: Fix ICE in vectorizable_comparison PR93292

The following testcase ICEs on powerpc64le-linux. The problem is that
get_vectype_for_scalar_type returns NULL, and while most places in
tree-vect-stmts.c handle that case, this spot doesn't and punts only
if it is non-NULL, but with different number of elts than expected.

2020-01-17 Jakub Jelinek <jakub@redhat.com>

PR tree-optimization/93292
* tree-vect-stmts.c (vectorizable_comparison): Punt also if
get_vectype_for_scalar_type returns NULL.

* g++.dg/opt/pr93292.C: New test.

testsuite: Unbreak compat.exp testing with alt compiler PR93294

2020-01-17 Jakub Jelinek <jakub@redhat.com>

PR testsuite/93294
* lib/c-compat.exp (compat-use-alt-compiler): Handle
-fdiagnostics-urls=never similarly to -fdiagnostics-color=never.
(compat_setup_dfp): Likewise.

ChangeLog fixes.

contrib/gcc_update: Insert "tformat:" for git log --pretty=tformat:%p:%t:%H

Really old git versions (like 1.6.0) require
"git log --pretty=tformat:%p:%t:%H"
or else we see:

Updating GIT tree
Current branch master is up to date.
fatal: invalid --pretty format: %p:%t:%H
Adjusting file timestamps
Touching gcc/config.in...
Touching gcc/config/arm/arm-tune.md...

...and an empty revision in LAST_UPDATED and gcc/REVISION.
In its absence, for newer git versions, "tformat" is the default
qualifier, documented as such default for at least git-2.11.0.

PR c++/93286 - ICE with __is_constructible and variadic template.

Here we had been recursing in tsubst_copy_and_build if type2 was a TREE_LIST
because that function knew how to deal with pack expansions, and tsubst
didn't. But tsubst_copy_and_build expects to be dealing with expressions,
so we crash when trying to convert_from_reference a type.

* pt.c (tsubst) [TREE_LIST]: Handle pack expansion.
(tsubst_copy_and_build) [TRAIT_EXPR]: Always use tsubst for type2.

Daily bump.

Extern -param=max-predicted-iterations range.

* params.opt (-param=max-predicted-iterations): Increase range from 0.
* predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.

Fix ICE caused by swallowing a token in c_parser_consume_token

This patch fixes ICE on invalid code, specifically files that have
conflict-marker-like signs before EOF.

PR c/92833
gcc/c/
* c-parser.c (c_parser_consume_token): Fix peeked token stack pop
to support 4 available tokens.

gcc/testsuite/
* c-c++-common/pr92833-1.c, c-c++-common/pr92833-2.c,
c-c++-common/pr92833-3.c, c-c++-common/pr92833-4.c: New tests.

Make profile estimation more precise

While analyzing code size regression in SPEC2k GCC binary I noticed that we
perform some inline decisions because we think that number of executions are
very high.
In particular there was inline decision inlining gen_rtx_fmt_ee to find_reloads
believing that it is called 4 billion times.  This turned out to be cummulation
of roundoff errors in propagate_freq which was bit mechanically updated from
original sreals to C++ sreals and later to new probabilities.

This led us to estimate that a loopback edge is reached with probability 2.3
which was capped to 1-1/10000 and since this happened in nested loop it quickly
escalated to large values.

Originally capping to REG_BR_PROB_BASE avoided such problems but now we have
much higher range.

This patch avoids going from probabilites to REG_BR_PROB_BASE so precision is
kept.  In addition it makes the propagation to not estimate more than
param-max-predicted-loop-iterations.  The first change makes the cap to not
be triggered on the gcc build, but it is still better to be safe than sorry.

* ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
dump.
* params.opt: (max-predicted-iterations): Set bounds.
* predict.c (real_almost_one, real_br_prob_base,
real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
(propagate_freq): Add max_cyclic_prob parameter; cap cyclic
probabilities; do not truncate to reg_br_prob_bases.
(estimate_loops_at_level): Pass max_cyclic_prob.
(estimate_loops): Compute max_cyclic_prob.
(estimate_bb_frequencies): Do not initialize real_*; update calculation
of back edge prob.
* profile-count.c (profile_probability::to_sreal): New.
* profile-count.h (class sreal): Move up in file.
(profile_probability::to_sreal): Declare.

PR c++/93280 - ICE with aggregate assignment and DMI.

I recently added an assert to cp-gimplify to catch any
TARGET_EXPR_DIRECT_INIT_P being expanded without a target object, and this
testcase found one.  We started out with a TARGET_EXPR around the
CONSTRUCTOR, which would normally mean that the member initializer would be
used to directly initialize the appropriate member of whatever object the
TARGET_EXPR ends up initializing.  But then gimplify_modify_expr_rhs
stripped the TARGET_EXPR in order to assign directly from the elements of
the CONSTRUCTOR, leaving no object for the TARGET_EXPR_DIRECT_INIT_P to
initialize.  I considered setting CONSTRUCTOR_PLACEHOLDER_BOUNDARY in that
case, which implies TARGET_EXPR_NO_ELIDE, but decided that there's no
particular reason the A initializer needs to initialize a member of a B
rather than a distinct A object, so let's only set TARGET_EXPR_DIRECT_INIT_P
when we're using the DMI in a constructor.

* init.c (get_nsdmi): Set TARGET_EXPR_DIRECT_INIT_P here.
* typeck2.c (digest_nsdmi_init): Not here.

Fix noreorder symbol partitioning reversion.

* lto-partition.c (lto_balanced_map): Remember
best_noreorder_pos and then restore to it
when we revert.

libstdc++: std::ctype fixes for recent versions of NetBSD

This removes support for EOL versions of NetBSD and syncs the
definitions with patches from NetBSD upstream.

The only change here that isn't from upstream is to use _CTYPE_BL for
the isblank class, which is correct but wasn't previously done either in
FSF GCC or the NetBSD packages.

2020-01-16  Kai-Uwe Eckhardt  <kuehro@gmx.de>
    Matthew Bauer  <mjbauer95@gmail.com>
    Jonathan Wakely  <jwakely@redhat.com>

PR bootstrap/64271 (partial)
* config/os/bsd/netbsd/ctype_base.h (ctype_base::mask): Change type
to unsigned short.
(ctype_base::alpha, ctype_base::digit, ctype_base::xdigit)
(ctype_base::print, ctype_base::graph, ctype_base::alnum): Sync
definitions with NetBSD upstream.
(ctype_base::blank): Use _CTYPE_BL.
* config/os/bsd/netbsd/ctype_configure_char.cc (_C_ctype_): Remove
Declaration.
(ctype<char>::classic_table): Use _C_ctype_tab_ instead of _C_ctype_.
(ctype<char>::do_toupper, ctype<char>::do_tolower): Cast char
parameters to unsigned char.
* config/os/bsd/netbsd/ctype_inline.h (ctype<char>::is): Likewise.

[GCC][PATCH][ARM] Add Bfloat16_t scalar type, vector types and machine modes to ARM back-end [2/2]

gcc/ChangeLog:

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* config/arm/arm.c
(arm_invalid_conversion): New function for target hook.
(arm_invalid_unary_op): New function for target hook.
(arm_invalid_binary_op): New function for target hook.

gcc/testsuite/ChangeLog:

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* g++.target/arm/bfloat_cpp_typecheck.C: New test.
* gcc.target/arm/bfloat16_scalar_typecheck.c: New test.
* gcc.target/arm/bfloat16_vector_typecheck_1.c: New test.
* gcc.target/arm/bfloat16_vector_typecheck_2.c: New test.

[GCC][PATCH][ARM] Add Bfloat16_t scalar type, vector types and machine modes to ARM back-end [1/2]

gcc/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

* config.gcc: Add arm_bf16.h.
* config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
(arm_simd_builtin_std_type): Add BFmode.
(arm_init_simd_builtin_types): Define element types for vector types.
(arm_init_bf16_types): New function.
(arm_init_builtins): Add arm_init_bf16_types function call.
* config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
* config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
* config/arm/arm.c (aapcs_vfp_sub_candidate):  Add BFmode.
(arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
(arm_vector_mode_supported_p): Add V4BF, V8BF.
(arm_mangle_type):  Add __bf16.
* config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
arm_bf16_ptr_type_node.
* config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
define_split between ARM registers.
* config/arm/arm_bf16.h: New file.
* config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
* config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
(VQXMOV): Add V8BF.
* config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
* config/arm/vfp.md: Add BFmode to movhf patterns.

gcc/testsuite/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

* g++.dg/abi/mangle-neon.C: Add BF16 SIMD types.
* g++.dg/ext/arm-bf16/bf16-mangle-1.C: New test.
* gcc.target/arm/bfloat16_scalar_1_1.c: New test.
* gcc.target/arm/bfloat16_scalar_1_2.c: New test.
* gcc.target/arm/bfloat16_scalar_2_1.c: New test.
* gcc.target/arm/bfloat16_scalar_2_2.c: New test.
* gcc.target/arm/bfloat16_scalar_3_1.c: New test.
* gcc.target/arm/bfloat16_scalar_3_2.c: New test.
* gcc.target/arm/bfloat16_scalar_4.c: New test.
* gcc.target/arm/bfloat16_simd_1_1.c: New test.
* gcc.target/arm/bfloat16_simd_1_2.c: New test.
* gcc.target/arm/bfloat16_simd_2_1.c: New test.
* gcc.target/arm/bfloat16_simd_2_2.c: New test.
* gcc.target/arm/bfloat16_simd_3_1.c: New test.
* gcc.target/arm/bfloat16_simd_3_2.c: New test.

Add CLI and multilib support for Armv8.1-M Mainline MVE extensions

gcc/ChangeLog:

2020-01-16  Mihail Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* config/arm/arm-cpus.in (mve, mve_float): New features.
(dsp, mve, mve.fp): New options.
* config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
* config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
* doc/invoke.texi: Document the armv8.1-m mve and dps options.

gcc/testsuite/ChangeLog:

2020-01-16  Mihail Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* testsuite/gcc.target/arm/multilib.exp: Add v8.1-M entries.

[PATCH, GCC/ARM, 10/10] Enable -mcmse

The patch is straightforward: it redefines ARMv8_1m_main as having the
same features as ARMv8m_main (and thus as having the cmse feature) with
the extra features represented by armv8_1m_main.  It also removes the
error for using -mcmse on Armv8.1-M Mainline.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
Armv8-M Mainline.
* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
error for using -mcmse when targeting Armv8.1-M Mainline.

[PATCH, GCC/ARM, 9/10] Call nscall function with blxns

This change to use BLXNS to call a nonsecure function from secure
directly (not using a libcall) is made in 2 steps:
- change nonsecure_call patterns to use blxns instead of calling
  __gnu_cmse_nonsecure_call
- loosen requirement for function address to allow any register when
  doing BLXNS.

The former is a straightforward check over whether instructions added in
Armv8.1-M Mainline are available while the latter consist in making the
nonsecure call pattern accept any register by using match_operand and
changing the nonsecure_call_internal expander to no force r4 when
targeting Armv8.1-M Mainline.

The tricky bit is actually in the test update, specifically how to check
that register lists for CLRM have all registers except for the one
holding parameters (already done) and the one holding the address used
by BLXNS. This is achieved with 3 scan-assembler directives.

1) The first one lists all registers that can appear in CLRM but make
   each of them optional.
   Property guaranteed: no wrong register is cleared and none appears
   twice in the register list.
2) The second directive check that the CLRM is made of a fixed number
   of the right registers to be cleared. The number used is the number
   of registers that could contain a secret minus one (used to hold the
   address of the function to call.
   Property guaranteed: register list has the right number of registers
   Cumulated property guaranteed: only registers with a potential secret
   are cleared and they are all listed but ont
3) The last directive checks that we cannot find a CLRM with a register
   in it that also appears in BLXNS. This is check via the use of a
   back-reference on any of the allowed register in CLRM, the
   back-reference enforcing that whatever register match in CLRM must be
   the same in the BLXNS.
   Property guaranteed: register used for BLXNS is different from
   registers cleared in CLRM.

Some more care needs to happen for the gcc.target/arm/cmse/cmse-1.c
testcase due to there being two CLRM generated. To ensure the third
directive match the right CLRM to the BLXNS, a negative lookahead is
used between the CLRM register list and the BLXNS. The way negative
lookahead work is by matching the *position* where a given regular
expression does not match. In this case, since it comes after the CLRM
register list it is requesting that what comes after the register list
does not have a CLRM again followed by BLXNS. This guarantees that the
.*blxns after only matches a blxns without another CLRM before.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm.md (nonsecure_call_internal): Do not force memory
address in r4 when targeting Armv8.1-M Mainline.
(nonsecure_call_value_internal): Likewise.
* config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
a register match_operand again.  Emit BLXNS when targeting
Armv8.1-M Mainline.
(nonsecure_call_value_reg_thumb2): Likewise.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/cmse-1.c: Add check for BLXNS when instructions
introduced in Armv8.1-M Mainline Security Extensions are available and
restrict checks for libcall to __gnu_cmse_nonsecure_call to Armv8-M
targets only.  Adapt CLRM check to verify register used for BLXNS is
not in the CLRM register list.
* gcc.target/arm/cmse/cmse-14.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise and adapt
check for LSB clearing bit to be using the same register as BLXNS when
targeting Armv8.1-M Mainline.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.
* gcc.target/arm/cmse/cmse-15.c: Count BLXNS when targeting Armv8.1-M
Mainline and restrict libcall count to Armv8-M.

[PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall function

This patch adds two new patterns for the VLSTM and VLLDM instructions.
cmse_nonsecure_call_inline_register_clear is then modified to
generate VLSTM and VLLDM respectively before and after calls to
functions with the cmse_nonsecure_call attribute in order to have lazy
saving, clearing and restoring of VFP registers. Since these
instructions do not do writeback of the base register, the stack is adjusted
prior the lazy store and after the lazy load with appropriate frame
debug notes to describe the effect on the CFA register.

As with CLRM, VSCCLRM and VSTR/VLDR, the instruction is modeled as an
unspecified operation to the memory pointed to by the base register.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
(cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
variable as true when floating-point ABI is not hard.  Replace
check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
Generate VLSTM and VLLDM instruction respectively before and
after a function call to cmse_nonsecure_call function.
* config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
(VUNSPEC_VLLDM): Likewise.
* config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
(lazy_load_multiple_insn): Likewise.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Add check for VLSTM and
VLLDM.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.

[PATCH, GCC/ARM, 7/10] Clear all VFP regs inline in hardfloat nscall functions

The patch is fairly straightforward in its approach and consist of the
following 3 logical changes:
- abstract the number of floating-point register to clear in
  max_fp_regno
- use max_fp_regno to decide how many registers to clear so that the
  same code works for Armv8-M and Armv8.1-M Mainline
- emit vpush and vpop instruction respectively before and after a
  nonsecure call

Note that as in the patch to clear GPRs inline, debug information has to
be disabled for VPUSH and VPOP due to VPOP adding CFA adjustment note
for SP when R7 is sometimes used as CFA.

ChangeLog entries are as follows:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm.c (vfp_emit_fstmd): Declare early.
(arm_emit_vfp_multi_reg_pop): Likewise.
(cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
registers to clear in max_fp_regno.  Emit VPUSH and VPOP to save and
restore callee-saved VFP registers.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Add check for
VPUSH and VPOP and update expectation for VSCCLRM.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.

[PATCH, GCC/ARM, 6/10] Clear GPRs inline when calling nscall function

Besides changing the set of registers that needs to be cleared inline,
this patch also generates the push and pop to save and restore
callee-saved registers without trusting the callee inline. To make the
code more future-proof, this (currently) Armv8.1-M specific behavior is
expressed in terms of clearing of callee-saved registers rather than
directly based on the targets.

The patch contains 1 subtlety:

Debug information is disabled for push and pop because the
REG_CFA_RESTORE notes used to describe popping of registers do not stack.
Instead, they just reset the debug state for the register to the one at
the beginning of the function, which is incorrect for a register that is
pushed twice (in prologue and before nonsecure call) and then popped for
the first time. In particular, this occasionally trips CFI note creation
code when there are two codepaths to the epilogue, one of which does not
go through the nonsecure call. Obviously this mean that debugging
between the push and pop is not reliable.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
(cmse_nonsecure_call_clear_caller_saved): Rename into ...
(cmse_nonsecure_call_inline_register_clear): This.  Save and clear
callee-saved GPRs as well as clear ip register before doing a nonsecure
call then restore callee-saved GPRs after it when targeting
Armv8.1-M Mainline.
(arm_reorg): Adapt to function rename.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/cmse-1.c: Add check for PUSH and POP and update
CLRM check.
* gcc.target/arm/cmse/cmse-14.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/union-1.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/union-2.c: Likewise.

[PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM

This patch adds a new pattern for the VSCCLRM instruction.
cmse_clear_registers () is then modified to use the new VSCCLRM
instruction when targeting Armv8.1-M Mainline, thus, making the Armv8-M
register clearing code specific to Armv8-M.

Since the VSCCLRM instruction mandates VPR in the register list, the
pattern is encoded with a parallel which only requires an unspecified
VUNSPEC_CLRM_VPR constant modelling the APSR clearing. Other expression
in the parallel are expected to be set expression for clearing the VFP
registers.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
* config/arm/arm.c (clear_operation_p): Extend to be able to check a
clear_vfp_multiple pattern based on a new vfp parameter.
(cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
targeting Armv8.1-M Mainline.
(cmse_nonsecure_entry_clear_before_return): Clear VFP registers
unconditionally when targeting Armv8.1-M Mainline architecture.  Check
whether VFP registers are available before looking call_used_regs for a
VFP register.
* config/arm/predicates.md (clear_multiple_operation): Adapt to change
of prototype of clear_operation_p.
(clear_vfp_multiple_operation): New predicate.
* config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
* config/arm/vfp.md (clear_vfp_multiple): New define_insn.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/bitfield-1.c: Add check for VSCCLRM.
* gcc.target/arm/cmse/bitfield-2.c: Likewise.
* gcc.target/arm/cmse/bitfield-3.c: Likewise.
* gcc.target/arm/cmse/cmse-1.c: Likewise.
* gcc.target/arm/cmse/struct-1.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.

[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM

This patch adds a new pattern for the CLRM instruction and guards the
current clearing code in output_return_instruction() and thumb_exit()
on Armv8.1-M Mainline instructions not being present.
cmse_clear_registers () is then modified to use the new CLRM instruction
when targeting Armv8.1-M Mainline while keeping Armv8-M register
clearing code for VFP registers.

For the CLRM instruction, which does not mandated APSR in the register
list, checking whether it is the right volatile unspec or a clearing
register is done in clear_operation_p.

Note that load/store multiple were deemed sufficiently different in
terms of RTX structure compared to the CLRM pattern for a different
function to be used to validate the match_parallel.

ChangeLog entries are as follows:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm-protos.h (clear_operation_p): Declare.
* config/arm/arm.c (clear_operation_p): New function.
(cmse_clear_registers): Generate clear_multiple instruction pattern if
targeting Armv8.1-M Mainline or successor.
(output_return_instruction): Only output APSR register clearing if
Armv8.1-M Mainline instructions not available.
(thumb_exit): Likewise.
* config/arm/predicates.md (clear_multiple_operation): New predicate.
* config/arm/thumb2.md (clear_apsr): New define_insn.
(clear_multiple): Likewise.
* config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/bitfield-1.c: Add check for CLRM.
* gcc.target/arm/cmse/bitfield-2.c: Likewise.
* gcc.target/arm/cmse/bitfield-3.c: Likewise.
* gcc.target/arm/cmse/struct-1.c: Likewise.
* gcc.target/arm/cmse/cmse-14.c: Likewise.
* gcc.target/arm/cmse/cmse-1.c: Likewise.  Restrict checks for Armv8-M
GPR clearing when CLRM is not available.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.

[PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions

This patch consists mainly of creating 2 new instruction patterns to
push and pop special FP registers via vldm and vstr and using them in
prologue and epilogue. The patterns are defined as push/pop with an
unspecified operation on the memory accessed, with an unspecified
constant indicating what special FP register is being saved/restored.

Other aspects of the patch include:
  * defining the set of special registers that can be saved/restored and
    their name
  * reserving space in the stack frames for these push/pop
  * preventing return via pop
  * guarding the clearing of FPSCR to target architecture not having
    Armv8.1-M Mainline instructions.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* config/arm/arm.c (fp_sysreg_names): Declare and define.
(use_return_insn): Also return false for Armv8.1-M Mainline.
(output_return_instruction): Skip FPSCR clearing if Armv8.1-M
Mainline instructions are available.
(arm_compute_frame_layout): Allocate space in frame for FPCXTNS
when targeting Armv8.1-M Mainline Security Extensions.
(arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
Mainline entry function.
(cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
targeting Armv8.1-M Mainline or successor.
(arm_expand_epilogue): Fix indentation of caller-saved register
clearing.  Restore FPCXTNS if this is an Armv8.1-M Mainline
entry function.
* config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
(FP_SYSREGS): Likewise.
(enum vfp_sysregs_encoding): Define enum.
(fp_sysreg_names): Declare.
* config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
* config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
(pop_fpsysreg_insn): Likewise.

*** gcc/testsuite/Changelog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

* gcc.target/arm/cmse/bitfield-1.c: add checks for VSTR and VLDR.
* gcc.target/arm/cmse/bitfield-2.c: Likewise.
* gcc.target/arm/cmse/bitfield-3.c: Likewise.
* gcc.target/arm/cmse/cmse-1.c: Likewise.
* gcc.target/arm/cmse/struct-1.c: Likewise.
* gcc.target/arm/cmse/cmse.exp: Run existing Armv8-M Mainline tests
from mainline/8m subdirectory and new Armv8.1-M Mainline tests from
mainline/8_1m subdirectory.
* gcc.target/arm/cmse/mainline/bitfield-4.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-4.c: This.
* gcc.target/arm/cmse/mainline/bitfield-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-5.c: This.
* gcc.target/arm/cmse/mainline/bitfield-6.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-6.c: This.
* gcc.target/arm/cmse/mainline/bitfield-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-7.c: This.
* gcc.target/arm/cmse/mainline/bitfield-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-8.c: This.
* gcc.target/arm/cmse/mainline/bitfield-9.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-9.c: This.
* gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: Move and rename
into ...
* gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c: This.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard/cmse-13.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard/cmse-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard/cmse-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/hard/cmse-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/soft/cmse-13.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/soft/cmse-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/soft/cmse-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/soft/cmse-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c: This.  Clean up
dg-skip-if directive for float ABI.
* gcc.target/arm/cmse/mainline/union-1.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/union-1.c: This.
* gcc.target/arm/cmse/mainline/union-2.c: Move into ...
* gcc.target/arm/cmse/mainline/8m/union-2.c: This.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/union-1.c: New file.
* gcc.target/arm/cmse/mainline/8_1m/union-2.c: New file.
* lib/target-supports.exp (check_effective_target_arm_cmse_clear_ok):
New procedure.

[PATCH, GCC/ARM, 2/10] Add command line support for Armv8.1-M Mainline

Besides the expected enabling of the new value for the -march
command-line option (-march=armv8.1-m.main) and its extensions (see
below), this patch disables support of the Security Extensions for this
newly added architecture. This is done both by not including the cmse
bit in the architecture description and by throwing an error message
when user request Armv8.1-M Mainline Security Extensions. Note that
Armv8-M Baseline and Mainline Security Extensions are still enabled.

Only extensions for already supported instructions are implemented in
this patch. Other extensions (MVE integer and float) will be added in
separate patches. The following configurations are allowed for Armv8.1-M
Mainline with regards to FPU and implemented in this patch:
+ no FPU (+nofp)
+ single precision VFPv5 with FP16 (+fp)
+ double precision VFPv5 with FP16 (+fp.dp)

ChangeLog entry are as follow:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>

* config/arm/arm-cpus.in (armv8_1m_main): New feature.
(ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
(ARMv8_1m_main): New feature group.
(armv8.1-m.main): New architecture.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
(arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
(arm_options_perform_arch_sanity_checks): Error out when targeting
Armv8.1-M Mainline Security Extensions.
* config/arm/arm.h (arm_arch8_1m_main): Declare.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>

* lib/target-supports.exp
(check_effective_target_arm_arch_v8_1m_main_ok): Define.
(add_options_for_arm_arch_v8_1m_main): Likewise.
(check_effective_target_arm_arch_v8_1m_main_multilib): Likewise.

[PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgcc

This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture.

Code to detect whether cmse.c can be buit with -mcmse checks the output
of host GCC when invoked with -mcmse. However, an error from the
compiler does not prevent some minimal output so this always holds true.

2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>

* config/arm/t-arm: Check return value of gcc rather than lack of
output.

gcc-git-customization.sh: Avoid double expansion

gcc-git-customization.sh: avoid double expansion

[GCC][PATCH][AArch64]Add ACLE intrinsics for bfdot for ARMv8.6 Extension

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
* config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
aarch64_bfdot_laneq): New.
* config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
vbfdotq_laneq_f32): New.
* config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
VBFMLA_W, VBF): New.
(isquadop): Add V4BF, V8BF.

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/bfdot-2.c: New.
* gcc.target/aarch64/advsimd-intrinsics/bfdot-3.c: New.

libstdc++: Improve unordered containers == operator (PR 91263)

Avoid comparing elements with operator== multiple times by replacing
uses of find and equal_range with equivalent inlined code that uses
operator== instead of the container's equality comparison predicate.
This is valid because the standard requires that operator== is a
refinement of the equality predicate.

Also replace the _S_is_permutation function with std::is_permutation,
which wasn't yet implemented when this code was first written.

PR libstdc++/91263
* include/bits/hashtable.h (_Hashtable<>): Make _Equality<> friend.
* include/bits/hashtable_policy.h: Include <bits/stl_algo.h>.
(_Equality_base): Remove.
(_Equality<>::_M_equal): Review implementation. Use
std::is_permutation.
* testsuite/23_containers/unordered_multiset/operators/1.cc
(Hash, Equal, test02, test03): New.
* testsuite/23_containers/unordered_set/operators/1.cc
(Hash, Equal, test02, test03): New.

[GCC][PATCH][AArch64]Add ACLE intrinsics for dot product (usdot - vector, <us/su>dot - by element) for AArch64 AdvSIMD ARMv8.6 Extension

gcc/ChangeLog:

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
(aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
(aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
* config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
usdot_laneq, sudot_lane,sudot_laneq): New.
* config/aarch64/aarch64-simd.md (aarch64_usdot): New.
(aarch64_<sur>dot_lane): New.
* config/aarch64/arm_neon.h (vusdot_s32): New.
(vusdotq_s32): New.
(vusdot_lane_s32): New.
(vsudot_lane_s32): New.
* config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
(UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.

gcc/testsuite/ChangeLog:

2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>

* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-4.c: New test.

contrib: Check and if needed set user.name and user.email in gcc-git-customization.sh

As discussed on IRC, this adds a couple more checks in the
customization setup for git.  If the variables user.name and
user.email are not set anywhere in the git config hierarchy, we set
some local values.  We always ask about the values we detect and if
the user gives an answer that is new, we save that in the local
config: this gives the opportunity to use different values to those
configured for the global space.

Also cleaned up a couple of minor niggles, such as using $(cmd) rather
than `cmd` for subshells and some quoting issues when using eval.

* gcc-git-customization.sh: Check that user.name and user.email
are set.  Use $(cmd) instead of `cmd`.  Fix variable quoting when
using eval.

Fix spacing in a dump in value-prof.c.

* value-prof.c (dump_histogram_value): Fix
obvious spacing issue.

Fix value numbering dealing with reverse byte order

Hi,
  While working on bit-field lowering pass, I came across this bug.
The IR looks like:
  VIEW_CONVERT_EXPR<unsigned long>(var1) = _12;
  _1 = BIT_FIELD_REF <var1, 64, 0>;

Where the BIT_FIELD_REF has REF_REVERSE_STORAGE_ORDER set on it
and var1's type has TYPE_REVERSE_STORAGE_ORDER set on it.
PRE/FRE would decided to prop _12 into the BFR statement
which would produce wrong code.
And yes _12 has the correct byte order already; bit-field lowering
removes the implicit byte swaps in the IR and adds the explicity
to make it easier optimize later on.

This patch adds a check for storage_order_barrier_p on the lhs tree
which returns true in the case where we had a reverse order with a VCE.

ChangeLog:
* tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
!storage_order_barrier_p.

Uninitialized padding in struct _dep.

In struct _dep, there is an implicit padding of 4bits. This
bit-field padding is uninitialized when init_dep_1 is being called.
This means we access uninitialized memory but never use it for
anything. Adding an unused bit-field field and initializing it
in init_dep_1 will improve code generation also as we initialize
the whole 32bits now rather than just part of it.

ChangeLog:
* sched-int.h (_dep): Add unused bit-field field for the padding.
* sched-deps.c (init_dep_1): Init unused field.

Fix uninitialized field in expand_operand.

Commit g:f96bf49a0 added the target field to expand_operand.
But it leaves it uninitialized when doing a full initialization
inside create_expand_operand. This fixes the problem and improves
the code generation inside create_expand_operand too.

ChangeLog:
* optabs.h (create_expand_operand): Initialize target field also.

contrib: Verify the id to be printed is ancestor of the corresponding remote release branch (or master), otherwise print nothing.

The monotonically increasing revision ids need to be globally unique, so they should
only identify commits that were committed to the upstream repo to its master or
releases/gcc-N branches. The alias could print something even for private branches
or vendor branches etc., but if such an identifier is then used publicly, it will
refer to something else.

2020-01-16 Jakub Jelinek <jakub@redhat.com>

* gcc-git-customization.sh: Verify the id to be printed is ancestor of
the corresponding remote release branch (or master), otherwise print
nothing.

PR tree-optimization/92429 do not fold when updating epilogue statements

This patch addresses the problem reported in PR92429.  When creating an
epilogue for vectorization we have to replace the SSA_NAMEs in the
PATTERN_DEF_SEQs and RELATED_STMTs of the epilogue's loop_vec_infos. When doing
this we were using simplify_replace_tree which always folds the replacement.
This may lead to a different tree-node than the one which was analyzed in
vect_loop_analyze.  In turn the new tree-node may require a different
vectorization than the one we had prepared for which caused the ICE in
question.

gcc/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR tree-optimization/92429
* tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
* tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
control folding.
* tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
tree.

gcc/testsuite/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR tree-optimization/92429
* gcc.dg/vect/pr92429.c: New test.

Work around array out of bounds warning in mkdeps

This suppresses an array out of bounds warning in mkdeps.c as proposed
by Martin Sebor in the bugzilla.

array subscript 2 is outside array bounds of ‘const char [2]’

Since this warning does occur during bootstrap it currently breaks
werror builds on IBM Z.

The problem can be reproduced also on x86_64 by changing the inlining
threshold using: --param max-inline-insns-auto=80

Bootstrapped and regression tested on x86_64 and IBM Z.

libcpp/ChangeLog:

2020-01-16 Andreas Krebbel <krebbel@linux.ibm.com>

PR tree-optimization/92176
* mkdeps.c (deps_add_default_target): Avoid calling apply_vpath to
suppress an array out of bounds warning.

aarch64: Fix BE SVE mode punning involving floats

The patterns used by aarch64_split_sve_subreg_move only support
integer modes, so if the widest mode is a float, we should get
its integer equivalent.

Fixes gcc.target/aarch64/sel_3.c for big-endian targets.

2020-01-16 Richard Sandiford <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
aarch64_sve_int_mode to each mode.

PR93253 – Document BOZ changes, make it friendlier in legacy code

        PR fortran/93253
        * check.c (gfc_invalid_boz): Mention -fallow-invalid-boz
        in the error message.
        * gfortran.texi (BOZ literal constants): List another missing
        extension and refer to -fallow-invalid-boz.
        * lang.opt (fallow-invalid-boz): Also mention 'X' in the help text
        as it is not covered by the previous wording.
        * primary.c (match_boz_constant): Tweak wording such that it is
        clear how to fix the nonstandard use.

        PR fortran/93253
        * fortran.dg/boz_7.f90: Updated dg-error.

Daily bump.

analyzer: add note about -fdump-ipa-analyzer to internal docs

gcc/ChangeLog:
* doc/analyzer.texi (Overview): Add note about
-fdump-ipa-analyzer.

analyzer: fix comment

I rewrote class impl_region_model_context to avoid using multiple
inheritance during patch review but forgot to update this comment.

Fix it.

gcc/analyzer/ChangeLog:
* engine.cc (class impl_region_model_context): Fix comment.

Fix "PR c++/91073 if constexpr no longer works directly with Concepts."

This is a rather serious regression, filed in July 2019. Luckily the
fix is simple: is localized to parser.c and cp-tree.h in cp and boils
down to only a few lines.

Testing OK on x86_64-linux. Approved off-line by Jason Merrill.

/cp
PR c++/91073
* cp-tree.h (is_constrained_auto): New.
* parser.c (cp_parser_maybe_commit_to_declaration): Correctly
handle concept-check expressions; take a cp_decl_specifier_seq*
instead of a bool.
(cp_parser_condition): Update call.
(cp_parser_simple_declaration): Likewise.
(cp_parser_placeholder_type_specifier): Correctly handle
concept-check expressions.

/testsuite
PR c++/91073
* g++.dg/concepts/pr91073-1.C: New.
* g++.dg/concepts/pr91073-2.C: Likewise.

Revert "PR c++/33799 - destroy return value if local cleanup throws."

This change was blocking the coroutines merge, so I'm backing it out for now
to adjust my approach.

This reverts commit 7c82dd6c02d44d9d2cd84dda137c00b1a3cd6c90.

PR c++/93257 - consteval void function.

A prvalue can have void type, and if it doesn't do anything prohibited in a
constant expression, it's vacuously constant.

* constexpr.c (verify_constant): Allow void_node.

PR c++/92871 - bad code with xvalue and GNU ?: extension.

I steered Jakub wrong on the desired behavior for temp-extend1.C in the
context of bug 92831; it doesn't make sense to try to extend the lifetime of
a temporary that we've already materialized to evaluate the test. So this
patch munges the stabilized expression so that it won't be subject to
lifetime extension.

* call.c (prevent_lifetime_extension): New.
(build_conditional_expr_1): Use it.

Fix ctz issues (PR93231)

Further improve the ctz recognition: Avoid ICEing on negative shift
counts or multiply constants.  Check the type is a char type for the
string constant case to avoid accidentally matching a wide STRING_CST.
Add a tree_expr_nonzero_p check to allow the optimization even if
CTZ_DEFINED_VALUE_AT_ZERO returns 0 or 1.  Add extra test cases.

Bootstrap OK on AArch64 and x64.

    gcc/
PR tree-optimization/93231
* tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
input_type is unsigned.  Use tree_to_shwi for shift constant.
Check CST_STRING element size is CHAR_TYPE_SIZE bits.
(simplify_count_trailing_zeroes): Add test to handle known non-zero
inputs more efficiently.

    testsuite/
PR tree-optimization/93231
* gcc.dg/pr90838.c: New test.
* gcc.dg/pr93231.c: New test.
* gcc.target/aarch64/pr90838.c: Use #define u 0.

libstdc++: Fix weakly_incrementable to allow __int128 (PR 93267)

The __iota_diff_t alias can be the type __int128, but that does not
satisfy the signed_integral and __is_signed_integer_like concepts when
__STRICT_ANSI__ is defined (which is true for -std=c++2a).

Because weakly_incrementable is defined in terms of signed_integral, it
is not satisfied by __int128, which means iota_view's iterator doesn't
always satisfy input_or_output_iterator and so iota_view is not always a
range.

The solution is to define __max_size_type and __max_diff_type using
__int128, so that __is_signed_integer_like allows __int128, and then
make weakly_incrementable use __is_signed_integer_like instead of
signed_integral.

PR libstdc++/93267
* include/bits/iterator_concepts.h (__max_diff_type, __max_size_type):
Move here from <bits/range_access.h> and define using __int128 when
available.
(__is_integer_like, __is_signed_integer_like): Move here from
<bits/range_access.h>.
(weakly_incrementable): Use __is_signed_integer_like.
* include/bits/range_access.h (__max_diff_type, __max_size_type)
(__is_integer_like, __is_signed_integer_like): Move to
<bits/iterator_concepts.h>.
(__make_unsigned_like_t): Move here from <ranges>.
* include/std/ranges (__make_unsigned_like_t): Move to
<bits/range_access.h>.
(iota_view): Replace using-directive with using-declarations.
* testsuite/std/ranges/iota/93267.cc: New test.
* testsuite/std/ranges/iota_view.cc: Move to new 'iota' sub-directory.

Remove invalid SSE2 ISA requirements in *movsf_internal.

* config/i386/i386.md (*movsf_internal): Do not require
SSE2 ISA for alternatives 14 and 15.

[PR90916] Fix typo

middle-end/93273 - fix sinking clobbers across backedges

The previous work to fix PR93199 didn't take into account backedges
when defering insertion.  The following simply avoids to defer in that
case since we know we'll not take secondary opportunities there.

2020-01-15  Richard Biener  <rguenther@suse.de>

        PR middle-end/93273
        * tree-eh.c (sink_clobbers): If we already visited the destination
        block do not defer insertion.
        (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
        the purpose of defered insertion.

* g++.dg/torture/pr93273.C: New testcase.

Bump gcc/BASE-VER to 10.0.1 now that we are in stage4.

2020-01-15 Jakub Jelinek <jakub@redhat.com>

* BASE-VER: Bump to 10.0.1.

PR tree-optimization/93247 - ICE in get_load_store_type

My earlier update_epilogue_loop_vinfo patch introduced an ICE on these
tests for AVX512. If we use pattern stmts, STMT_VINFO_GATHER_SCATTER_P
is valid for both the original stmt and the pattern stmt, but
STMT_VINFO_MEMORY_ACCESS_TYPE is valid only for the latter.

2020-01-15 Richard Sandiford <richard.sandiford@arm.com>

gcc/
PR tree-optimization/93247
* tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
type of the stmt that we're going to vectorize.

gcc/testsuite/
PR tree-optimization/93247
* gcc.dg/vect/pr93247-1.c: New test.
* gcc.dg/vect/pr93247-2.c: Likewise.

Fix type mismatch in SLPed constructors

Having the "same" vector types with different modes means that we can
end up vectorising a constructor with a different mode from the lhs.
This patch adds a VIEW_CONVERT_EXPR in that case.

This showed up on existing tests when testing with fixed-length
-msve-vector-bits=128.

2020-01-15 Richard Sandiford <richard.sandiford@arm.com>

gcc/
* tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
type from the lhs.

Add *.md diff=md.

2020-01-15 Segher Boessenkool <segher@kernel.crashing.org>
Jakub Jelinek <jakub@redhat.com>

* .gitattributes: Add *.md diff=md.
contrib/
* gcc-git-customization.sh: Change uses to use in comment.

Do not call streamer_read_hwi in a function call.

* ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
2 calls of streamer_read_hwi in a function call.

Handle output of older git in gcc-descr and gcc-undescr aliases.

contrib: Don't add push rules for personal and vendor spaces.

Originally, it seemed like a good idea to add automatic 'push' rules
to the git configuration, so that personal- and vendor-space commits
would automatically push to the right place.  Unfortunately, this
changes git's behaviour and with these settings "git push" will try to
push all branches in a local tree up to the corresponding location on
the server (ignoring the push.default setting).  The only known
mitigation for this is to ALWAYS use "git push <server> <branch>".

So instead, we no-longer add those rules by default and will document
the options on the wiki.  We don't automatically remove the push
entries but do print out the command that will do so, if the user so
wishes.

* gcc-git-customization.sh: Explain why we want the user's
upstream account name.  Don't add push rules.  Check if push rules
have been added and suggest that they should be removed.
* git-fetch-vendor.sh: Don't add push rules.

gcc/testsuite/ChangeLog:

* gcc.dg/Wstringop-overflow-17.c: Tweak test to avoid unrelated
failures due the absence of loop unrolling.

Optimize alias subset recording

When an alias-set is an already existing subset there is no need
to re-record its children as childs of the parent.

2020-01-15 Richard Biener <rguenther@suse.de>

* alias.c (record_alias_subset): Avoid redundant work when
subset is already recorded.

Fix setting of DECL_CONTEXT in pushdecl (PR c/93072).

Bug 93072 is a case where the C front end (a) wrongly interprets an
inline declaration at block scope as indicating that DECL_CONTEXT
should be set for an inline function and (b) this results in an ICE.
This is a regression resulting from a previous fix of mine for other
bugs involving such declarations being wrongly interpreted elsewhere
as nested function declarations. The fix is similar to the previous
fix: use TREE_PUBLIC instead of DECL_EXTERNAL in another place as the
relevant test to determine whether to set DECL_CONTEXT. (When a
variable reaches the code in question in pushdecl, the two are
equivalent.)

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

PR c/93072
gcc/c:
* c-decl.c (pushdecl): Use TREE_PUBLIC, not DECL_EXTERNAL, to
determine whether to set DECL_CONTEXT.

gcc/testsuite:
* gcc.dg/inline-42.c, gcc.dg/inline-43.c: New tests.

invoke.texi: update -fdiagnostics-show-cwe for analyzer

gcc/ChangeLog:
* doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
the analyzer options provide CWE identifiers.

analyzer: fix ICE on METHOD_TYPE (PR 93212)

PR analyzer/93212 reports an ICE when attempting to use -fanalyzer
on a C++ source file. That isn't supported yet, but the fix is
trivial (handling METHOD_TYPE as well as FUNCTION_TYPE).

gcc/analyzer/ChangeLog:
PR analyzer/93212
* region-model.cc (make_region_for_type): Use
FUNC_OR_METHOD_TYPE_P rather than comparing against FUNCTION_TYPE.
* region-model.h (function_region::function_region): Likewise.

analyzer: fix global-sm-state issue affecting sm-signal

sm-signal.cc was failing to warn about the use of an fprintf call in a
signal handler when the signal handler function was non-static.

The root cause was a failure to copy global sm-state within
sm_state_map::clone_with_remapping as called by
program_state::can_merge_with_p, which led to the exploded node for
the entrypoint to the handler in the "normal" state being erroneously
reused for the "in_signal_handler" state, thus losing the global state,
and thus failing to warn.

This patch fixes the above, so that non-equal global sm-state values
prevent merger of program_state, thus requiring separate exploded nodes
for the "normal" and "in signal handler" states, and thus triggering
the warning for the reproducer.

gcc/analyzer/ChangeLog:
* program-state.cc (sm_state_map::clone_with_remapping): Copy
m_global_state.
(selftest::test_program_state_merging_2): New selftest.
(selftest::analyzer_program_state_cc_tests): Call it.

gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/signal-6.c: New test.

analyzer: cleanups to checker_path

This patch adds DISABLE_COPY_AND_ASSIGN to checker_path, and makes its
fields private.

gcc/analyzer/ChangeLog:
* checker-path.h (checker_path::get_checker_event): New function.
(checker_path): Add DISABLE_COPY_AND_ASSIGN; make fields private.
* diagnostic-manager.cc
(diagnostic_manager::prune_for_sm_diagnostic): Replace direct
access to checker_path::m_events with accessor functions. Fix
overlong line.
(diagnostic_manager::prune_interproc_events): Replace direct
access to checker_path::m_events with accessor functions.
(diagnostic_manager::finish_pruning): Likewise.

analyzer: delete checker_event::clone

checker_event has a clone vfunc implemented by all the concrete
subclasses, but this is never used (a holdover from a very early
implementation). This patch deletes it.

gcc/analyzer/ChangeLog:
* checker-path.h (checker_event::clone): Delete vfunc decl.
(debug_event::clone): Delete vfunc impl.
(custom_event::clone): Delete vfunc impl.
(statement_event::clone): Delete vfunc impl.
(function_entry_event::clone): Delete vfunc impl.
(state_change_event::clone): Delete vfunc impl.
(start_cfg_edge_event::clone): Delete vfunc impl.
(end_cfg_edge_event::clone): Delete vfunc impl.
(call_event::clone): Delete vfunc impl.
(return_event::clone): Delete vfunc impl.
(setjmp_event::clone): Delete vfunc impl.
(rewind_from_longjmp_event::clone): Delete vfunc impl.
(rewind_to_setjmp_event::clone): Delete vfunc impl.
(warning_event::clone): Delete vfunc impl.

analyzer: ensure .dot output is valid for an empty BB

This patch fixes an issue with the output of -fdump-analyzer-supergraph
on BBs with no statements, where the resulting files were unreadable by
dot e.g.:

Error: syntax error in line 1
... <TABLE BORDER="0"></TABLE> ...
in label of node node_10

gcc/analyzer/ChangeLog:
* supergraph.cc (supernode::dump_dot): Ensure that the TABLE
element has at least one TR.

gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/dot-output.c: Add test coverage for a BB with
no statements.

analyzer: fix tests for UNKNOWN_LOCATION

In the reproducer for PR analyzer/58237 I noticed that some events were
missing locations (and text); for example event 3 here:

    |   15 |   while (fgets(buf, 10, fp) != NULL)
    |      |         ~
    |      |         |
    |      |         (2) following 'false' branch...
    |
  'f1': event 3
    |
    |cc1:
    |
  'f1': event 4
    |
    |<source>:19:1:
    |   19 | }
    |      | ^
    |      | |
    |      | (4) 'fp' leaks here; was opened at (1)
    |

The root cause is that various places in the analyzer compare locations
against UNKNOWN_LOCATION, which fails to detect an unknown location for
the case where an unknown_location has been wrapped into an ad-hoc
location to record a block.

This patch fixes the issue by using get_pure_location whenever testing
against UNKNOWN_LOCATION to look through ad-hoc wrappers.

For the case above, it thus picks a better location in
supernode::get_start_location for event (3) above, improving it to:

    |   15 |   while (fgets(buf, 10, fp) != NULL)
    |      |         ~
    |      |         |
    |      |         (2) following 'false' branch...
    |......
    |   19 | }
    |      | ~
    |      | |
    |      | (3) ...to here
    |      | (4) 'fp' leaks here; was opened at (1)
    |

gcc/analyzer/ChangeLog:
PR analyzer/58237
* engine.cc (leak_stmt_finder::find_stmt): Use get_pure_location
when comparing against UNKNOWN_LOCATION.
(stmt_requires_new_enode_p): Likewise.
(exploded_graph::dump_exploded_nodes): Likewise.
* supergraph.cc (supernode::get_start_location): Likewise.
(supernode::get_end_location): Likewise.

gcc/testsuite/ChangeLog:
PR analyzer/58237
* gcc.dg/analyzer/file-paths-1.c: New test.

tree-diagnostic-path.cc: properly handle ad-hoc wrappers of UNKNOWN_LOCATION

In the reproducer for PR analyzer/58237 I noticed that some events that
were missing locations were also missing text; for example event 3 here:

    |   15 |   while (fgets(buf, 10, fp) != NULL)
    |      |         ~
    |      |         |
    |      |         (2) following 'false' branch...
    |
  'f1': event 3
    |
    |cc1:
    |

The root cause is that the path_summary-printing code doesn't consider
ad-hoc locations when looking for reserved locations, and so fails to
detect an unknown location for the case where an unknown location has
been wrapped into an ad-hoc location to record a block.

This patch fixes the issue by using get_pure_location, thus looking
through ad-hoc wrappers, improving the result to:

    |   15 |   while (fgets(buf, 10, fp) != NULL)
    |      |         ~
    |      |         |
    |      |         (2) following 'false' branch...
    |
  'f1': event 3
    |
    |cc1:
    | (3): ...to here
    |

gcc/ChangeLog:
* tree-diagnostic-path.cc (path_summary::event_range::print):
When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
using get_pure_location.

analyzer: add known stdio functions to sm-file.cc (PR analyzer/58237)

The analyzer ought to report various file leaks for the reproducer in
PR analyzer/58237, such as:

  void f1(const char *str)
  {
    FILE * fp = fopen(str, "r");
    char buf[10];
    while (fgets(buf, 10, fp) != NULL)
    {
      /* Do something with buf */
    }
    /* Missing call to fclose. Need warning here for resource leak */
  }

but fails to do so, due to not recognizing fgets, and thus
conservatively assuming that it could close "fp".

This patch adds a function_set to sm-file.cc of numerous stdio.h
functions that are known to not close the file (and which require a
valid FILE *, but that's a matter for a followup), fixing the issue.

gcc/analyzer/ChangeLog:
PR analyzer/58237
* analyzer-selftests.cc (selftest::run_analyzer_selftests): Call
selftest::analyzer_sm_file_cc_tests.
* analyzer-selftests.h (selftest::analyzer_sm_file_cc_tests): New
decl.
* sm-file.cc: Include "analyzer/function-set.h" and
"analyzer/analyzer-selftests.h".
(get_file_using_fns): New function.
(is_file_using_fn_p): New function.
(fileptr_state_machine::on_stmt): Return true for known functions.
(selftest::analyzer_sm_file_cc_tests): New function.

gcc/testsuite/ChangeLog:
PR analyzer/58237
* gcc.dg/analyzer/file-1.c (test_4): New.
* gcc.dg/analyzer/file-pr58237.c: New test.

tree-optimization: Fix tree dse of __*_chk PR93262

The following testcase shows that GCC trunk mishandles DSE of __*_chk
calls.  Tail trimming of the calls is fine, we want to just decrease the
third argument and keep the first two and last arguments unmodified.
But for head trimming, we currently increment the two by head_trim and
decrease the third by head_trim, so
  __builtin___memcpy_chk (&a, b_2(D), 48, 32);
  __builtin_memset (&a, 32, 16);
into:
  _5 = b_2(D) + 16;
  __builtin___memcpy_chk (&MEM <char> [(void *)&a + 16B], _5, 32, 32);
  __builtin_memset (&a, 32, 16);
This is wrong, because the 32 was the determined (maximum) size of the
destination (char a[32]), but &a[16] has maximum size of 16, not 32.
The __builtin___memcpy_chk (&MEM <char> [(void *)&a + 16B], _5, 32, 32);
call is just folded later into
__builtin_memcpy (&MEM <char> [(void *)&a + 16B], _5, 32);
because it says that it copies as many bytes into destination as the
destination has.  We need:
  __builtin___memcpy_chk (&MEM <char> [(void *)&a + 16B], _5, 32, 16);
instead, which will terminate the program instead of letting it silently
overflow the buffer.
The patch just punts if we'd need to decrease the last argument below 0.

Fortunately, release branches are unaffected.
P.S. it was quite hard to make the runtime test working, in builtins.exp
neither dg-options nor dg-additional-options work and builtins.exp adds
-fno-tree-dse among several other -fno-* options.  Fortunately optimize
attribute works.

2020-01-15  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/93262
* tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
perform head trimming only if the last argument is constant,
either all ones, or larger or equal to head trim, in the latter
case decrease the last argument by head_trim.

* gcc.c-torture/execute/builtins/pr93262-chk.c: New test.
* gcc.c-torture/execute/builtins/pr93262-chk-lib.c: New file.
* gcc.c-torture/execute/builtins/pr93262-chk.x: New file.

tree-optimization: Fix tree dse of strncpy PR93249

As the testcase shows, tail trimming of strncpy in tree-ssa-dse.c is fine,
we just copy or clear fewer bytes in the destination, but unlike
memcpy/memset etc., head trimming is problematic in certain cases.
If we can prove that there are no zero bytes among initial head_trim bytes,
it is ok to trim it, if we can prove there is at least one zero byte among
initial head_trim bytes, we could (not implemented in the patch) turn
the strncpy into memset 0, but otherwise we need to avoid the head trimming,
because the presence or absence of NUL byte there changes the behavior for
subsequent bytes, whether further bytes from src are copied or if further
bytes are cleared.

2020-01-15 Jakub Jelinek <jakub@redhat.com>

PR tree-optimization/93249
* tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
(maybe_trim_memstar_call): Move head_trim and tail_trim vars to
function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
perform head trim unless we can prove there are no '\0' chars
from the source among the first head_trim chars.

* gcc.c-torture/execute/pr93249.c: New test.

Daily bump.

analyzer: introduce a set of known async-signal-unsafe functions

This patch uses the class function_set from the previous patch to
generalize the test for an fprintf inside a signal handler to
check for a set of known async-signal-unsafe functions.

gcc/analyzer/ChangeLog:
* analyzer-selftests.cc (selftest::run_analyzer_selftests): Call
selftest::analyzer_sm_signal_cc_tests.
* analyzer-selftests.h (selftest::analyzer_sm_signal_cc_tests):
New decl.
* sm-signal.cc: Include "analyzer/function-set.h" and
"analyzer/analyzer-selftests.h".
(get_async_signal_unsafe_fns): New function.
(signal_unsafe_p): Reimplement in terms of the above.
(selftest::analyzer_sm_signal_cc_tests): New function.

gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/signal-5.c: New test.

analyzer: add function-set.cc/h

This patch adds a simple mechanism for tracking sets of functions
for which a particular property holds, as a pragmatic way to build
knowledge about important APIs into the analyzer without requiring
markup of the user's libc.

gcc/ChangeLog:
* Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.

gcc/analyzer/ChangeLog:
* analyzer-selftests.cc (selftest::run_analyzer_selftests): Call
selftest::analyzer_function_set_cc_tests.
* analyzer-selftests.h (selftest::analyzer_function_set_cc_tests):
New decl.
* function-set.cc: New file.
* function-set.h: New file.