Improve diagnostic for forgotten ().

* parser.c (cp_parser_postfix_dot_deref_expression): Use
complete_type_or_else for unknown_type_node, too.

From-SVN: r236220

tree-vect.h (check_vect): Handle AVX2, remove XOP handling.

* gcc.dg/vect/tree-vect.h (check_vect): Handle AVX2,
remove XOP handling.

From-SVN: r236216

i386.c (ix86_compute_frame_layout, [...]): Use HOST_WIDE_INT_C macro.

* config/i386/i386.c (ix86_compute_frame_layout, ix86_expand_prologue,
ix86_expand_split_stack_prologue): Use HOST_WIDE_INT_C macro.
(ix86_split_to_parts): Likewise.  Fix up formatting.

From-SVN: r236215

Cast to unsigned HOST_WIDE_INT in printf format

* tree-ssa-loop-ivopts.c (create_new_ivs): Cast to
unsigned HOST_WIDE_INT with HOST_WIDE_INT_PRINT_UNSIGNED in
printf format.

From-SVN: r236214

nvptx.c (nvptx_mangle_decl_assembler_name): New.

* config/nvptx/nvptx.c (nvptx_mangle_decl_assembler_name): New.
(nvptx_name_replacement): Delete.
(write_fn_proto, write_fn_proto_from_insn,
nvptx_output_call_insn): Remove nvptx_name_replacement call.
(TARGET_MANGLE_DECL_ASSEMBLER_NAME): Override.
* langhooks.c (add_builtin_funcction_common): Call
targetm.mangle_decl_assembler_name.

From-SVN: r236212

libstdc++/71073 add system_header pragma to Debug Mode headers

PR libstdc++/71073
* include/debug/bitset: Add #pragma GCC system_header.
* include/debug/deque: Likewise.
* include/debug/list: Likewise.
* include/debug/map: Likewise.
* include/debug/set: Likewise.
* include/debug/string: Likewise.
* include/debug/unordered_map: Likewise.
* include/debug/unordered_set: Likewise.
* include/debug/vector: Likewise.
* include/debug/functions.h: Adjust whitespace.

From-SVN: r236211

nvptx.c (write_fn_proto): Handle BUILT_IN_ATOMIC_COMPARE_EXCHANGE_n oddity.

gcc/
* config/nvptx/nvptx.c (write_fn_proto): Handle
BUILT_IN_ATOMIC_COMPARE_EXCHANGE_n oddity.

gcc/testsuite/
* gcc.dg/atomic-noinline-aux.c: Include stddef.h. Fix
__atomic_is_lock_free declaration.

From-SVN: r236209

IVOPTS dump fall-out

* tree-ssa-loop-ivopts.c (create_new_ivs): Use HOST_WIDE_INT_PRINT_DEC
and PRIu64 in printf format.

From-SVN: r236208

[obvious] Typo fix in tree-ssa-loop-ivanon.c

* tree-ssa-loop-ivanon.c (try_unroll_loop_completely): Typo fix in
comment.

From-SVN: r236206

[obvious] Fix param name in dump file

* tree-ssa-loop-ivcanon.c (try_unroll_loop_completely):
Change --param max-completely-peeled-times to
--param max-completely-peel-times in dump file printing.

From-SVN: r236205

re PR tree-optimization/42587 (bswap not recognized for memory)

2016-05-13  Richard Biener  <rguenther@suse.de>

PR tree-optimization/42587
* tree-ssa-math-opts.c (perform_symbolic_merge): Handle BIT_FIELD_REF.
(find_bswap_or_nop_1): Likewise.
(bswap_replace): Likewise.

* gcc.dg/optimize-bswapsi-4.c: New testcase.

From-SVN: r236204

Fix ASAN bootstrap (uninitialized variable warning)

* tree-vect-patterns.c (vect_recog_mask_conversion_pattern):
Initialize a variable with default value.

From-SVN: r236203

Enhance explanation of halt_on_error.

* doc/invoke.texi: Enhance explanation of error recovery
of sanitizers.

From-SVN: r236202

Enhance dumps of IVOPTS

* tree-ssa-loop-ivopts.c (avg_loop_niter): Fix coding style.
(struct cost_pair): Change inv_expr_id (int) to inv_expr
(iv_inv_expr_ent *).
(struct iv_inv_expr_ent): Comment struct fields.
(sort_iv_inv_expr_ent): New function.
(struct ivopts_data): Rename inv_expr_id to max_inv_expr_id.
(struct iv_ca): Replace used_inv_expr and num_used_inv_expr with
a hash_map between iv_inv_expr_ent and number of usages.
(niter_for_exit): Fix coding style.
(tree_ssa_iv_optimize_init): Use renamed variable.
(determine_base_object): Fix coding style.
(alloc_iv): Likewise.
(find_interesting_uses_outside): Likewise.
(add_candidate_1): Likewise.
(add_standard_iv_candidates): Likewise.
(set_group_iv_cost): Replace inv_expr_id with inv_expr.
(prepare_decl_rtl): Fix coding style.
(get_address_cost): Likewise.
(get_shiftadd_cost): Likewise.
(force_expr_to_var_cost): Likewise.
(compare_aff_trees): Likewise.
(get_expr_id): Restructure the function.
(get_loop_invariant_expr_id): Renamed to
get_loop_invariant_expr.
(get_computation_cost_at): Replace usage of inv_expr_id with
inv_expr.
(get_computation_cost): Likewise.
(determine_group_iv_cost_generic): Likewise.
(determine_group_iv_cost_address): Likewise.
(iv_period): Fix coding style.
(iv_elimination_compare_lt): Likewise.
(may_eliminate_iv): Likewise.
(determine_group_iv_cost_cond):  Replace usage of inv_expr_id with
inv_expr.
(determine_group_iv_costs): Dump invariant expressions.
(iv_ca_recount_cost): Use the newly added hash_map.
(iv_ca_set_remove_invariants): Fix coding style.
(iv_ca_set_add_invariants): Fix coding style.
(iv_ca_set_no_cp): Utilize the newly added hash_map for used
invariants.
(iv_ca_set_cp): Likewise.
(iv_ca_new): Initialize the newly added hash_map and remove
initialization of fields.
(iv_ca_free): Delete the hash_map.
(iv_ca_dump): Dump invariant expressions.
(iv_ca_extend): Fix coding style.
(try_add_cand_for): Likewise.
(create_new_ivs): Dump information about # of avg iterations and
# of used invariant expressions.
(rewrite_use_compare): Fix coding style.
(free_loop_data): Set default value for max_inv_expr_id.
* g++.dg/tree-ssa/ivopts-3.C: Change test-case to follow
the new format of dump output.

From-SVN: r236200

cse.c (rest_of_handle_cse): Use cleanup_cfg returned value cse_cfg_altered computation.

gcc/

* cse.c (rest_of_handle_cse): Use cleanup_cfg
returned value cse_cfg_altered computation.
(rest_of_handle_cse2): Likewise.
(rest_of_handle_cse_after_global_opts): Likewise.

gcc/testsuite/

* gcc.dg/pr71084.c: New test.

From-SVN: r236199

Fix PR target/53440 - handle generic thunks better for TARGET_32BIT.

This partially fixes PR target/53440 atleast in ARM and
Thumb2 state. I haven't yet managed to get my head around
rewriting the Thumb1 support yet.

Tested on armhf with a bootstrap and regression test
with no regressions.

Queued for stage1 now as it isn't technically a regression.

regards
Ramana

2016-05-13  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/53440
        * config/arm/arm.c (arm32_output_mi_thunk): New.
        (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework
        to split Thumb1 vs TARGET_32BIT functionality.
        (arm_thumb1_mi_thunk): New.

        * g++.dg/inherit/thunk1.C: Support arm / aarch64.

From-SVN: r236198

Set TARGET_OMIT_STRUCT_RETURN_REG to true

The reason this caught my eye on aarch64 is because
the return value register (x0) is not identical to the register in which
the hidden parameter for AArch64 is set (x8). Thus setting this to true
seems to be quite reasonable and shaves off 100 odd mov x0, x8's from
cc1 in a bootstrap build.

I don't expect this to make a huge impact on performance but as they
say every little counts.  The AAPCS64 is quite explicit about not
requiring that the contents of x8 be kept live.

Bootstrapped and regression tested on aarch64.

Ok to apply ?

Ramana

gcc/
* config/aarch64/aarch64.c (TARGET_OMIT_STRUCT_RETURN_REG): Set to
true.

gcc/testsuite

* gcc.target/aarch64/struct_return.c: New test.

From-SVN: r236197

Fix SEGV in ix86_in_large_data_p (PR target/71080)

PR target/71080
* config/i386/i386.c (ix86_in_large_data_p): Guard against NULL exp.

From-SVN: r236196

builtins.c (expand_builtin_memcmp): Do not emit the call here.

* builtins.c (expand_builtin_memcmp): Do not emit the call here.
(expand_builtin_trap): Emit a regular call.
(set_builtin_user_assembler_name): Remove obsolete cases.
* dse.c (scan_insn): Adjust.
* except.c: Include calls.h.
(sjlj_emit_function_enter): If DONT_USE_BUILTIN_SETJMP is defined,
emit a regular call to setjmp.
* expr.c (emit_block_move_hints): Call emit_block_copy_via_libcall.
(block_move_libcall_safe_for_call_parm): Use memcpy builtin.
(emit_block_move_via_libcall): Delete.
(block_move_fn): Delete.
(init_block_move_fn): Likewise.
(emit_block_move_libcall_fn): Likewise.
(emit_block_op_via_libcall): New function.
(set_storage_via_libcall): Tidy up and use memset builtin.
(block_clear_fn): Delete.
(init_block_clear_fn): Likewise.
(clear_storage_libcall_fn): Likewise.
(expand_assignment): Call emit_block_move_via_libcall.
Do not include gt-expr.h.
* expr.h (emit_block_op_via_libcall): Declare.
(emit_block_copy_via_libcall): New inline function.
(emit_block_move_via_libcall): Likewise.
(emit_block_comp_via_libcall): Likewise.
(block_clear_fn): Delete.
(init_block_move_fn): Likewise.
(init_block_clear_fn): Likewise.
(emit_block_move_via_libcall): Likewise.
(set_storage_via_libcall): Add default parameter value.
* libfuncs.h (enum libfunc_index): Remove obsolete values.
(abort_libfunc): Delete.
(memcpy_libfunc): Likewise.
(memmove_libfunc): Likewise.
(memcmp_libfunc): Likewise.
(memset_libfunc): Likewise.
(setbits_libfunc): Likewise.
(setjmp_libfunc): Likewise.
(longjmp_libfunc): Likewise.
(profile_function_entry_libfunc): Likewise.
(profile_function_exit_libfunc): Likewise.
(gcov_flush_libfunc): Likewise.
* optabs-libfuncs.c (build_libfunc_function): Set DECL_ARTIFICIAL
and DECL_VISIBILITY on the declaration.
(init_optabs): Do not initialize obsolete libfuncs.
* optabs.c (prepare_cmp_insn): Call emit_block_comp_via_libcall.
* tree-core.h (ECF_RET1): Define.
(ECF_TM_PURE): Adjust.
(ECF_TM_BUILTIN): Likewise.
* tree.c (set_call_expr_flags): Deal with ECF_RET1.
(build_common_builtin_nodes): Initialize abort builtin.
Add ECF_RET1 on memcpy, memmove and memset builtins.
Pass final flags for alloca and alloca_with_align builtins.
* config/alpha/alpha.c (alpha_init_libfuncs): Do not initialize
obsolete builtins.
* config/ia64/ia64.c (ia64_vms_init_libfuncs): Likewise.
* config/i386/i386.c (ix86_expand_set_or_movmem): Adjust call to
set_storage_via_libcall and call emit_block_copy_via_libcall.

From-SVN: r236195

Daily bump.

From-SVN: r236189

* fi.po: Update.

From-SVN: r236183

i386.md (*call_got_x32): Change operand 0 to DImode before it is passed to ix86_output_call_operand.

* config/i386/i386.md (*call_got_x32): Change operand 0 to
DImode before it is passed to ix86_output_call_operand.
(*call_value_got_x32): Ditto for operand 1.

From-SVN: r236182

[LRA] PR70904, relax the restriction on subreg reload for wide mode

2016-05-12  Jiong Wang  <jiong.wang@arm.com>

gcc/
  PR rtl-optimization/70904
  * lra-constraint.c (process_addr_reg): Relax the restriction on
  subreg reload for wide mode.

From-SVN: r236181

re PR c/70756 (Wrong column number shown for "error: invalid use of flexible array member")

PR c/70756
* c-common.c (pointer_int_sum): Call size_in_bytes_loc instead of
size_in_bytes and pass LOC to it.

* c-decl.c (build_compound_literal): Pass LOC down to
c_incomplete_type_error.
* c-tree.h (require_complete_type): Adjust declaration.
(c_incomplete_type_error): Likewise.
* c-typeck.c (require_complete_type): Add location parameter, pass it
down to c_incomplete_type_error.
(c_incomplete_type_error): Add location parameter, pass it down to
error_at.
(build_component_ref): Pass location down to c_incomplete_type_error.
(default_conversion): Pass location down to require_complete_type.
(build_array_ref): Likewise.
(build_function_call_vec): Likewise.
(convert_arguments): Likewise.
(build_unary_op): Likewise.
(build_c_cast): Likewise.
(build_modify_expr): Likewise.
(convert_for_assignment): Likewise.
(c_finish_omp_clauses): Likewise.

* call.c (build_new_op_1): Pass LOC to cp_build_modify_expr.
* cp-tree.h (cp_build_modify_expr): Update declaration.
(cxx_incomplete_type_error, cxx_incomplete_type_diagnostic): New inline
overloads.
* cp-ubsan.c (cp_ubsan_dfs_initialize_vtbl_ptrs): Pass INPUT_LOCATION to
cp_build_modify_expr.
* decl2.c (set_guard): Likewise.
(handle_tls_init): Likewise.
* init.c (perform_member_init): Likewise.
(expand_virtual_init): Likewise.
(build_new_1): Likewise.
(build_vec_delete_1): Likewise.
(get_temp_regvar): Likewise.
(build_vec_init): Likewise.
* method.c (do_build_copy_assign): Likewise.
(assignable_expr): Likewise.
* semantics.c (finish_omp_for): Likewise.
* typeck.c (cp_build_binary_op): Pass LOCATION to pointer_diff and
cp_pointer_int_sum.
(cp_pointer_int_sum): Add location parameter.  Pass it down to
pointer_int_sum.
(pointer_diff): Add location parameter.  Use it.
(build_modify_expr): Pass location down to cp_build_modify_expr.
(cp_build_modify_expr): Add location parameter.  Use it.
(build_x_modify_expr): Pass location down to cp_build_modify_expr.
* typeck2.c (cxx_incomplete_type_diagnostic,
cxx_incomplete_type_error): Add location parameter.

* langhooks-def.h (lhd_incomplete_type_error): Adjust declaration.
* langhooks.c (lhd_incomplete_type_error): Add location parameter.
* langhooks.h (incomplete_type_error): Likewise.
* tree.c (size_in_bytes_loc): Renamed from size_in_bytes.  Add location
parameter, pass it down to incomplete_type_error.
* tree.h (size_in_bytes): New inline overload.
(size_in_bytes_loc): Renamed from size_in_bytes.

* c-c++-common/pr70756-2.c: New test.
* c-c++-common/pr70756.c: New test.

From-SVN: r236180

Add dg-require-atomic-builtins to test

PR libstdc++/71081
* testsuite/experimental/memory_resource/1.cc: Require atomics.

From-SVN: r236177

re PR tree-optimization/71059 (gcc ICE at -O3 on valid code on x86_64-linux-gnu in "vn_nary_op_insert_into")

2016-05-12  Richard Biener  <rguenther@suse.de>

PR tree-optimization/71059
* tree-ssa-pre.c (phi_translate_1): Fully fold translated
nary before looking up or entering the expression into the VN
hashes.
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): Fix comment typo.
Make sure to re-use NARYs without result as inserted by
phi-translation.

* gcc.dg/torture/pr71059.c: New testcase.

From-SVN: r236175

re PR middle-end/71062 (r235622 and restrict pointers)

2016-05-12  Richard Biener  <rguenther@suse.de>

PR tree-optimization/71062
* tree-ssa-alias.h (struct pt_solution): Add vars_contains_restrict
field.
* tree-ssa-structalias.c (set_uids_in_ptset): Set vars_contains_restrict
if the var is a restrict tag.
* tree-ssa-alias.c (ptrs_compare_unequal): If vars_contains_restrict
do not disambiguate pointers against it.
(dump_points_to_solution): Re-structure and adjust for new
vars_contains_restrict flag.
* gimple-pretty-print.c (pp_points_to_solution): Likewise.

* gcc.dg/torture/pr71062.c: New testcase.

From-SVN: r236174

Document ASAN_OPTIONS="halt_on_error" env variable.

* doc/invoke.texi: Explain connection between -fsanitize-recover=address
and ASAN_OPTIONS="halt_on_error=1".

From-SVN: r236172

re PR tree-optimization/71006 (ICE: verify_gimple failed (error: type mismatch in conditional expression) w/ -O1 -ftree-loop-vectorize)

gcc/

PR tree-optimization/71006
* tree-vect-loop.c (vect_determine_vectorization_factor): Don't
consider COND_EXPR as a mask producer.

gcc/testsuite/

PR tree-optimization/71006
* gcc.dg/pr71006.c: New test.

From-SVN: r236171

re PR driver/71063 (ICE: Segmentation fault with --help="^")

PR driver/71063
* opts.c (common_handle_option): Detect missing argument for --help^.

* gcc.dg/opts-7.c: New test.

From-SVN: r236170

[ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt handlers

PR target/70830
* config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction
when popping the PC and within an interrupt handler routine.
Add missing tab to output of "ldmfd".
(output_return_instruction): Output LDMFD with SP update rather
than POP when returning from interrupt handler.

* gcc.target/arm/interrupt-1.c: Change dg-compile to dg-assemble.
Add -save-temps to dg-options.
Scan for ldmfd rather than pop instruction.
* gcc.target/arm/interrupt-2.c: Likewise.
* gcc.target/arm/pr70830.c: New test.

From-SVN: r236169

i386.md (isa): Add x64_avx512dq, enable if TARGET_64BIT && TARGET_AVX512DQ.

* config/i386/i386.md (isa): Add x64_avx512dq, enable if
TARGET_64BIT && TARGET_AVX512DQ.
* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
(*vec_extractv4si_zext): Add avx512dq alternative.
(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
use v instead of x constraint in other alternatives where possible.

* gcc.target/i386/avx512bw-vpextr-1.c: New test.
* gcc.target/i386/avx512dq-vpextr-1.c: New test.

From-SVN: r236167

sse.md (sse2_loadld): Use v instead of x constraint in alternatives 0,1,4.

* config/i386/sse.md (sse2_loadld): Use v instead of x
constraint in alternatives 0,1,4.

From-SVN: r236166

sse.md (pinsr_evex_isa): New mode attr.

* config/i386/sse.md (pinsr_evex_isa): New mode attr.
(<sse2p4_1>_pinsr<ssemodesuffix>): Add 2 alternatives with
v constraints instead of x and <pinsr_evex_isa> isa attribute.

* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
* gcc.target/i386/avx512vl-vpinsr-1.c: New test.

From-SVN: r236165

re PR target/71019 (AVX512BW instructions emitted even without AVX512BW)

PR target/71019
* config/i386/sse.md (<sse2_avx2>_packssdw<mask_name>,
<sse4_1_avx2>_packusdw<mask_name>): Make sure EVEX encoded insn
is not emitted unless TARGET_AVX512BW.
(<sse2_avx2>_packuswb<mask_name>, <sse2_avx2>_packsswb<mask_name>):
Likewise.  For TARGET_AVX512BW, use "=v" constraint instead of "=x"
for the result operand.

* gcc.target/i386/avx512vl-pack-1.c: New test.
* gcc.target/i386/avx512vl-pack-2.c: New test.
* gcc.target/i386/avx512bw-pack-2.c: New test.

From-SVN: r236163

sse.md (*vec_setv4sf_sse4_1, [...]): Use v constraint instead of x in avx alternatives.

* config/i386/sse.md (*vec_setv4sf_sse4_1, sse4_1_insertps): Use v
constraint instead of x in avx alternatives.  Use maybe_evex instead
of vex prefix.

* gcc.target/i386/avx512vl-vinsertps-1.c: New test.

From-SVN: r236162

constraints.md (Yv): New constraint.

* config/i386/constraints.md (Yv): New constraint.
* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
* config/i386/i386.md (avx512fvecmode): New mode attr.
(*pushtf): Use v constraint instead of x.
(*movtf_internal): Likewise.  For TARGET_AVX512VL and
xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
(*absneg<mode>2): Use Yv constraint instead of x constraint.
(*absnegtf2_sse): Likewise.
(copysign<mode>3_const, copysign<mode>3_var): Likewise.
* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
avx512f alternatives.
(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.

* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.

From-SVN: r236161

re PR tree-optimization/71060 (Compiler reports "loop vectorized" but actually  it was not)

2016-05-12  Richard Biener  <rguenther@suse.de>

PR tree-optimization/71060
* tree-data-ref.c (initialize_data_dependence_relation): Do not
require exact match of DR_BASE_OBJECT but only matching address and
type.

From-SVN: r236159

re PR tree-optimization/70986 (ICE on valid code at -O3 on x86_64-linux-gnu in combine_blocks, at tree-if-conv.c:2219)

2016-05-12  Richard Biener  <rguenther@suse.de>

PR tree-optimization/70986
* cfganal.c: Include cfgloop.h.
(dfs_find_deadend): Prefer to take edges exiting loops.

* gcc.dg/torture/pr70986-1.c: New testcase.
* gcc.dg/torture/pr70986-2.c: Likewise.
* gcc.dg/torture/pr70986-3.c: Likewise.

From-SVN: r236158

Daily bump.

From-SVN: r236152

pr70963.c: Require at least power8 at both compile and run time.

2016-05-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/pr70963.c: Require at least power8 at both
compile and run time.

From-SVN: r236146

PR43651: add warning for duplicate qualifier

gcc/c/

PR c/43651
* c-decl.c (declspecs_add_qual): Warn when -Wduplicate-decl-specifier
is enabled.
* c-errors.c (pedwarn_c90): Return true if warned.
* c-tree.h (pedwarn_c90): Change return type to bool.
(enum c_declspec_word): Add new enumerator cdw_atomic.

gcc/

PR c/43651
* doc/invoke.texi (Wduplicate-decl-specifier): Document new option.

gcc/testsuite/

PR c/43651
* gcc.dg/Wduplicate-decl-specifier-c11.c: New test.
* gcc.dg/Wduplicate-decl-specifier.c: Likewise.

gcc/c-family/

PR c/43651
* c.opt (Wduplicate-decl-specifier): New option.

From-SVN: r236142

sse-13.c: Add dg-add-options bind_pic_locally directive.

* gcc.target/i386/sse-13.c: Add dg-add-options bind_pic_locally
directive.
* gcc.target/i386/pr66746.c: Ditto.

From-SVN: r236140

i386.c (legitimize_pic_address): Use copy_to_suggested_reg instead of gen_movsi.

* config/i386/i386.c (legitimize_pic_address): Use
copy_to_suggested_reg instead of gen_movsi.

From-SVN: r236138

predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with...

[gcc]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/predicates.md (quad_memory_operand): Move most of
the code into quad_address_p and call it to share code with
vsx_quad_dform_memory_operand.
(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
d-form support.
* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
bit instead of being a separate word.  Split -mpower9-dform into
two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
for the register class supporting 128-bit quad word memory
offsets.
(mode_supports_vsx_dform_quad): Helper function to return if the
register class uses quad word memory offsets.
(rs6000_debug_addr_mask): Add support for quad word memory
offsets.
(rs6000_debug_reg_global): Always print if we are using LRA or
not.
(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
instructions are enabled, set up the appropriate addr_masks for
128-bit types.
(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
-mpower9-dform-scalar, instead of -mpower9-dform.
(rs6000_option_override_internal): Split -mpower9-dform into two
switches, -mpower9-dform-scalar and -mpower9-dform-vector.  The
-mpower9-dform switch sets or clears both.  If we are not using
the LRA register allocator, do not enable -mpower9-dform-vector by
default.  If we are using LRA, enable -mpower9-dform-vector and
-mvsx-timode if it is appropriate.  Issue a warning if either
-mpower9-dform-vector or -mvsx-timode are explicitly used without
enabling LRA.
(quad_address_offset_p): New helper function to return if the
offset is legal for quad word memory instructions.
(quad_address_p): New function to determin if GPR or vector
register quad word memory addresses are legal.
(mem_operand_gpr): Validate quad word address offsets.
(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
d-form (register + offset) instructions.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Add more debug statements for
-mdebug=addr.
(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
d-form instructions.  Distinguish different cases in debug
output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
instructions.  If ISA 3.0 is available, generate lxvx/stxvx instead
of the ISA 2.06 indexed memory instructions.
(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
use them to save/restore the saved vector registers instead of
using Altivec instructions.
(rs6000_emit_epilogue): Likewise.
(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
(rs6000_opt_masks): Split -mpower9-dform into
-mpower9-dform-scalar and -mpower9-dform-vector.
(rs6000_print_options_internal): Print -mno-<switch> if <switch>
was not selected.
* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
ISA 3.0 vector indexed memory instructions, and fold the code into
the normal mov<mode> patterns.
(p9_vecstore_<mode>): Likewise.
(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
instructions.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
* config/rs6000/constraints.md (wO constraint): New constraint for
ISA 3.0 vector d-form support.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
-mpower9-dform-scalar instead of -mpower9-dform.  Add note not to
include -mpower9-dform-vector until we switch over to LRA.
(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two.
switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
for -mpower9-dform and -mlra.
* doc/md.texi (wO constraint): Document wO constraint.

[gcc/testsuite]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
support.
* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
warning when using -mvsx-timode.
* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.

From-SVN: r236133

genautomata.c cleanup

* genattr.c (main): Change 'rtx' to 'rtx_insn *' in prototypes of
'insn_latency', 'maximal_insn_latency', 'min_insn_conflict_delay'.
* genautomata.c (output_internal_insn_code_evaluation): Simplify.
Move handling of non-insn arguments inline into the sole user:
(output_trans_func): ...here.
(output_min_insn_conflict_delay_func): Change 'rtx' to 'rtx_insn *'
in emitted function prototype.
(output_internal_insn_latency_func): Ditto.  Simplify.
(output_internal_maximal_insn_latency_func): Ditto.  Delete
always-unused argument.
(output_insn_latency_func): Ditto.
(output_maximal_insn_latency_func): Ditto.

From-SVN: r236132

attr-opt-1.c: Move to c-c++-common/.

* gcc.dg/attr-opt-1.c: Move to c-c++-common/.
* gcc.dg/pr18079-2.c: Remove file.

From-SVN: r236130

re PR c++/71024 (Missing warning for contradictory attributes)

PR c++/71024
* c-common.c (diagnose_mismatched_attributes): New function.
* c-common.h (diagnose_mismatched_attributes): Declare.

* c-decl.c (diagnose_mismatched_decls): Factor out code to
diagnose_mismatched_attributes and call it.

* decl.c (duplicate_decls): Call diagnose_mismatched_decls.

* c-c++-common/attributes-3.c: New test.

From-SVN: r236129

pr68671.c: Xfail on PTX -- assembler crash.

* gcc.dg/pr68671.c: Xfail on PTX -- assembler crash.
* gcc.c-torture/execute/pr68185.c: Likewise.
* gcc.dg/ipa/pr70306.c: Requires global constructors.
* gcc.dg/pr69634.c: Requires scheduling.
* gcc.dg/torture/pr66178.c: Require label values.
* gcc.dg/setjmp-6.c: Require indirect jumps.

From-SVN: r236125

re PR tree-optimization/71055 (FAIL: gcc.dg/torture/pr53663-1.c   -Os  execution test)

2016-05-11  Richard Biener  <rguenther@suse.de>

PR tree-optimization/71055
* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
sth with precision not equal to access size verify we don't chop
off bits.

* gcc.dg/torture/pr71055.c: New testcase.

From-SVN: r236122

re PR debug/71057 (ICE in schedule_generic_params_dies_gen, at dwarf2out.c:24142)

2016-05-11  Richard Biener  <rguenther@suse.de>

PR debug/71057
* dwarf2out.c (retry_incomplete_types): Set early_dwarf.
(dwarf2out_finish): Move retry_incomplete_types call ...
(dwarf2out_early_finish): ... here.

* g++.dg/debug/pr71057.C: New testcase.

From-SVN: r236121

re PR fortran/70855 (ICE with -fopenmp in gfc_trans_omp_workshare(): Bad statement code)

PR fortran/70855
* frontend-passes.c (inline_matmul_assign): Disable in !$omp workshare.

* gfortran.dg/gomp/pr70855.f90: New test.

From-SVN: r236119

libstdc++/71049 fix --disable-libstdcxx-dual-abi bootstrap

PR libstdc++/71049
* src/c++11/cow-stdexcept.cc [!_GLIBCXX_USE_DUAL_ABI]: Don't define
exception constructors with __sso_string parameters.

From-SVN: r236118

re PR middle-end/71002 (-fstrict-aliasing breaks Boost's short string optimization implementation)

2016-05-11  Richard Biener  <rguenther@suse.de>

PR middle-end/71002
* alias.c (reference_alias_ptr_type): Preserve alias-set zero
if the langhook insists on it.
* fold-const.c (make_bit_field_ref): Add arg for the original
reference and preserve its alias-set.
(decode_field_reference): Take exp by reference and adjust it
to the original memory reference.
(optimize_bit_field_compare): Adjust callers.
(fold_truth_andor_1): Likewise.
* gimplify.c (gimplify_expr): Adjust in-SSA form test.

* g++.dg/torture/pr71002.C: New testcase.

From-SVN: r236117

re PR middle-end/70807 (fwprop pass ICE with incoming CDI_DOMINATORS)

gcc/

PR middle-end/70807
* cfgrtl.h (delete_insn_and_edges): Now return bool.
* cfgrtl.c (delete_insn_and_edges): Likewise.
* config/i386/i386.c (convert_scalars_to_vector): Remove
redundant code.
* cse.c (cse_insn): Compute cse_cfg_altered.
(delete_trivially_dead_insns): Likewise.
(cse_cc_succs): Likewise.
(rest_of_handle_cse): Free dominance info if required.
(rest_of_handle_cse2): Likewise.
(rest_of_handle_cse_after_global_opts): Likewise.

gcc/testsuite/

PR middle-end/70807
* gcc.dg/pr70807.c: New test.

From-SVN: r236114

PR c++/38611 - missing -Wattributes on a typedef with attribute aligned

From-SVN: r236112

[RS6000] complex long double ABI_V4 fix

Revision 235794 regressed compat/scalar-by-value-6 for powerpc-linux
-m32 due to accidentally changing the ABI.  By another historical
accident, complex long double is stupidly passed in gprs for -m32.

* config/rs6000/rs6000.c (is_complex_IBM_long_double,
abi_v4_pass_in_fpr): New functions.
(rs6000_function_arg_boundary): Exclude complex IBM long double
from 64-bit alignment when ABI_V4.
(rs6000_function_arg, rs6000_function_arg_advance_1,
rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.

From-SVN: r236111

Daily bump.

From-SVN: r236110

cfgcleanup: Handle a branch with just a return in both arms (PR71028)

If we have a conditional jump that has only a return in both the branch
path and the fallthrough path, and the return on the branch path can not
be made a conditional return, we will try to make a conditional return
from the fallthrough path, and that does not work because we then try
to redirect the (new) jump in the fallthrough block to the original
dest in the branch path, which is the exit block.

For the testcase on ARM we end up in this situation because before the
jump2 pass there are some other insns in the return blocks as well, but
the same insns in both, so those are moved above the conditional jump.
Only later (in the ce3 pass) are the conditional jump and two returns
melded into one return, so we need to handle this strange case here.

PR rtl-optimization/71028
* cfgcleanup.c (try_optimize_cfg): Do not flip a conditional
jump with just a return in the fallthrough block if the branch
block contains just a returns as well.

From-SVN: r236106

Simple bitop reassoc in match.pd

2016-05-10  Marc Glisse  <marc.glisse@inria.fr>

gcc/
* fold-const.c (fold_binary_loc) [(X ^ Y) & Y]: Remove and merge with...
* match.pd ((X & Y) ^ Y): ... this.
((X & Y) & Y, (X | Y) | Y, (X ^ Y) ^ Y, (X & Y) & (X & Z), (X | Y)
| (X | Z), (X ^ Y) ^ (X ^ Z)): New transformations.

gcc/testsuite/
* gcc.dg/tree-ssa/bit-assoc.c: New testcase.
* gcc.dg/tree-ssa/pr69270.c: Adjust.
* gcc.dg/tree-ssa/vrp59.c: Disable forwprop.

From-SVN: r236103

Simplify read-md.c and read-rtl.c using require_char_ws

read-md.c and read-rtl.c repeatedly use this pattern:

    c = read_skip_spaces ();
    if (c != ')')
      fatal_expected_char (')', c);

Simplify them by introduce a helper function to do this.

gcc/ChangeLog:
* read-md.c (require_char_ws): New function.
(read_string): Simplify using require_char_ws.
(handle_constants): Likewise.
(handle_enum): Likewise.
(handle_file): Likewise.
* read-md.h (require_char_ws): New declaration.
* read-rtl.c (read_conditions): Simplify using require_char_ws.
(read_mapping): Likewise.
(read_rtx_code): Likewise.
(read_nested_rtx): Likewise.

From-SVN: r236101

sysv4.h (CRTOFFLOADBEGIN): Define.

* config/rs6000/sysv4.h (CRTOFFLOADBEGIN): Define. Add crtoffloadbegin.o
if offloading is enabled and -fopenacc or -fopenmp is specified.
(CRTOFFLOADEND): Likewise.
(STARTFILE_LINUX_SPEC): Add CRTOFFLOADBEGIN.
(ENDFILE_LINUX_SPEC): Add CRTOFFLOADEND.

From-SVN: r236098

i386.c (legitimize_pic_address): Merge 64-bit and 32-bit gotoff_operand code paths.

* config/i386/i386.c (legitimize_pic_address): Merge 64-bit and 32-bit
gotoff_operand code paths.  Use copy_to_suggested_regs and
expand_simple_binop where appropriate.  Cleanup.

From-SVN: r236096

configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.

2016-05-10  Matthias Klose  <doko@ubuntu.com>

        * configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.
        * configure: Regenerate.

From-SVN: r236093

re PR target/70799 (STV pass does not convert DImode shifts)

gcc/

PR target/70799
* config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Allow
integer constants.
(dimode_scalar_chain::vector_const_cost): New.
(dimode_scalar_chain::compute_convert_gain): Handle constants.
(dimode_scalar_chain::convert_op): Likewise.
(dimode_scalar_chain::convert_insn): Likewise.

gcc/testsuite/

PR target/70799
* gcc.target/i386/pr70799-1.c: New test.

From-SVN: r236090

re PR middle-end/70877 ([MPX] ICE in in convert_move)

gcc/

PR middle-end/70877
* tree-chkp.c (chkp_add_bounds_to_call_stmt): Handle
calls with type casted fndecl.

gcc/testsuite/

PR middle-end/70877
* gcc.target/i386/pr70877.c: New test.

From-SVN: r236088

DWARF: fix stack usage assessment for DW_OP_neg

When the DWARF back-end generates DW_OP_neg operations in DWARF
procedures, we get an ICE because of inconsistent stack usage
computation for the embedding expression. This is because
resolve_args_picking_1 thinks DW_OP_neg is a binary operation (pops 2
stack slots, pushes 1) whereas it really is an unary one (one pop, one
push).

This change fixes resolve_args_picking_1 and adds a regression testcase
(which crashes with the current trunk).  Bootstrapped and regtested
without regression on x86_64-linux.

gcc/

* dwarf2out.c (resolve_args_picking_1): Consider DW_OP_neg as an
unary operation, not a binary one.

gcc/testsuite/

* gnat.dg/debug6.adb, gnat.dg/debug6_pkg.ads: New testcase.

From-SVN: r236087

re PR tree-optimization/70876 (ICE in chkp_find_bounds: Unexpected tree code with_size_expr)

gcc/

PR tree-optimization/70786
* tree-chkp.c (chkp_find_bounds_1): Support WITH_SIZE_EXPR.
* gcc/calls.c (initialize_argument_information): Bind bounds
with corresponding args passed by reference.

gcc/testsuite/

PR tree-optimization/70786
* gcc.target/i386/pr70876.c: New test.

From-SVN: r236086

Test begin and end functions for directory iterators

* include/experimental/bits/fs_dir.h (begin, end): Add noexcept.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Test begin and end functions.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.

From-SVN: r236085

libstdc++/71038 fix error checks in filesystem::copy_file

PR libstdc++/71038
* src/filesystem/ops.cc (do_copy_file): Fix backwards conditions.
* testsuite/experimental/filesystem/operations/copy_file.cc: New test.

From-SVN: r236084

re PR target/70927 ([6 only] avx512dq instructions emitted even with -mavx512vl -mno-avx512dq)

PR target/70927
* config/i386/sse.md (<sse>_andnot<mode>3<mask_name>),
*<code><mode>3<mask_name>): For !TARGET_AVX512DQ and EVEX encoding,
use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute
accordingly.

* gcc.target/i386/avx512vl-logic-1.c: New test.
* gcc.target/i386/avx512vl-logic-2.c: New test.
* gcc.target/i386/avx512dq-logic-2.c: New test.

From-SVN: r236083

re PR target/70963 (vec_cts/vec_ctf intrinsics produce wrong results for 64-bit floating point)

[gcc]

2016-05-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

PR target/70963
* config/rs6000/vsx.md (vsx_xvcvdpsxds_scale): Generate correct
code for a zero scale factor.
(vsx_xvcvdpuxds_scale): Likewise.

[gcc/testsuite]

2016-05-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

PR target/70963
* gcc.target/powerpc/pr70963.c: New.

From-SVN: r236082

Add debugging ruler to diagnostic-show-locus.c

When debugging diagnostic-show-locus.c, it's invaluable to have a
"ruler" showing column numbers.

This patch adds in support via a new "show_ruler_p" flag within
the diagnostic_context.  There's no direct way for end-users to enable
this, but plugins can enable it by setting the flag, so the
plugin that tests the diagnostic subsystem uses this to verify that
the ruler is correctly printed.

gcc/ChangeLog:
* diagnostic-show-locus.c (layout::layout): Call show_ruler
if show_ruler_p was set on the context.
(layout::show_ruler): New method.
* diagnostic.h (struct diagnostic_context): Add field
"show_ruler_p".

gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic-test-show-locus-bw.c
(test_very_wide_line): Add ruler to expected output.
* gcc.dg/plugin/diagnostic-test-show-locus-color.c
(test_very_wide_line): Likewise.
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c
(test_show_locus): Within the handling of "test_very_wide_line",
enable show_ruler_p on the diagnostic context.

From-SVN: r236080

re PR tree-optimization/71039 (ICE: verify_ssa failed (error: definition in block 4 does not dominate use in block 5) w/ -O1 and above)

2016-05-10  Richard Biener  <rguenther@suse.de>

PR tree-optimization/71039
* tree-ssa-phiprop.c: Include tree-ssa-loop.h.
(chk_uses): New function.
(propagate_with_phi): Verify we can safely replicate the lhs of an
aggregate assignment on all incoming edges.

* gcc.dg/torture/pr71039.c: New testcase.

From-SVN: r236079

Optimize __directory_iterator_proxy for the common case

* include/experimental/bits/fs_dir.h (__directory_iterator_proxy):
Overload operator* to move from rvalues.

From-SVN: r236078

nested-func-10.c: Requires alloca.

* gcc.dg/nested-func-10.c: Requires alloca.
* gcc.dg/nested-func-9.c: Requires alloca.
* gcc.c-torture/execute/pr70460.c: Requires labels.
* gcc.c-torture/compile/pr70199.c: Requires labels.
* gcc.target/nvptx/decl.c: Compile only.
* gcc.target/nvptx/trailing-init.c: Compile only.
* gcc.target/nvptx/ary-init.c: Compile only.

From-SVN: r236077

libstdc++/71036 Handle EEXIST in filesystem::create_directory

PR libstdc++/71036
* src/filesystem/ops.cc (create_dir): Handle EEXIST from mkdir.
* testsuite/experimental/filesystem/operations/create_directory.cc:
New test.

From-SVN: r236076

Add rudimentary support for atomics on RX.

Add rudimentary support for atomics on RX.  It is implemented by flipping
interrupts off/on around the atomic sequences.

gcc/
* config/rx/rx-protos.h (is_interrupt_func, is_fast_interrupt_func):
Forward declare.
(rx_atomic_sequence): New class.
* config/rx/rx.c (rx_print_operand): Use symbolic names for PSW bits.
(is_interrupt_func, is_fast_interrupt_func): Make non-static and
non-inline.
(rx_atomic_sequence::rx_atomic_sequence,
rx_atomic_sequence::~rx_atomic_sequence): New functions.
* config/rx/rx.md (CTRLREG_PSW, CTRLREG_USP, CTRLREG_FPSW, CTRLREG_CPEN,
CTRLREG_BPSW, CTRLREG_BPC, CTRLREG_ISP, CTRLREG_FINTV,
CTRLREG_INTB): New constants.
(FETCHOP): New code iterator.
(fethcop_name, fetchop_name2): New iterator code attributes.
(QIHI): New mode iterator.
(atomic_exchange<mode>, atomic_exchangesi, xchg_mem<mode>,
atomic_fetch_<fetchop_name>si, atomic_fetch_nandsi,
atomic_<fetchop_name>_fetchsi, atomic_nand_fetchsi): New patterns.

From-SVN: r236075

libstdc++/71037 Add base path to filesystem::canonical exceptions

PR libstdc++/71037
* src/filesystem/ops.cc (canonical(const path&, const path&)): Add
base path to exception.
* testsuite/experimental/filesystem/operations/canonical.cc: Test
paths contained in exception.

From-SVN: r236074

2.cc: Remove unused using declaration.

* testsuite/experimental/type_erased_allocator/2.cc: Remove unused
using declaration.

From-SVN: r236073

libstdc++/71005 fix post-increment for filesystem iterators

PR libstdc++/71005
* include/experimental/bits/fs_dir.h (__directory_iterator_proxy):
New type.
(directory_iterator::operator++(int)): Return proxy.
(recursive_directory_iterator::operator++(int)): Likewise.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Test post-increment.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.

From-SVN: r236072

re PR c/70255 (change of the order of summation of floating point numbers despite no-associative-math)

PR c/70255
* c-decl.c (diagnose_mismatched_decls): Warn for optimize attribute
on a declaration following the definition.

* gcc.dg/attr-opt-1.c: New test.

From-SVN: r236071

Handle memory leak in tree-inline.c.

* tree-inline.c (remap_dependence_clique): Do not remap
debugging statements.

From-SVN: r236070

S/390: Disable scalar vector instructions with -mno-vx.

Although the scalar variants of the vector instructions aren't
actually vector instructions they are still executed in the vector
facility and therefore need to be disabled when disabling the facility
with -mno-vx.

Fixed with the attached patch.  Committed to head, GCC 6, and GCC 5
branches.

gcc/ChangeLog:

2016-05-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

* config/s390/s390.md ("*vec_cmp<insn_cmp>df_cconly")
("*fixuns_truncdfdi2_z13")
("*fixuns_trunc<FP:mode><GPR:mode>2_z196")
("*fix_truncdfdi2_bfp_z13", "*floatunsdidf2_z13")
("*extendsfdf2_z13"): Replace TARGET_Z13 with TARGET_VX.

From-SVN: r236067

re PR tree-optimization/70497 (Missed CSE of subregs on GIMPLE)

2016-05-10  Richard Biener  <rguenther@suse.de>

PR tree-optimization/70497
PR tree-optimization/28367
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): New function
split out from ...
(visit_reference_op_load): ... here.
(vn_reference_lookup_3): Use it to handle subreg-like accesses
with simplified BIT_FIELD_REFs.
* tree-ssa-pre.c (eliminate_insert): Handle inserting BIT_FIELD_REFs.
* tree-complex.c (extract_component): Handle BIT_FIELD_REFs
correctly.

* gcc.dg/torture/20160404-1.c: New testcase.
* gcc.dg/tree-ssa/ssa-fre-54.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-55.c: Likewise.

From-SVN: r236066

DWARF: add abstract origin links on lexical blocks DIEs

Track from which abstract lexical block concrete ones come from in DWARF
so that debuggers can inherit the former from the latter. This enables
debuggers to properly handle the following case:

  * function Child2 is nested in a lexical block, itself nested in
    function Child1;
  * function Child1 is inlined into some call site;
  * function Child2 is never inlined.

Here, Child2 is described in DWARF only in the abstract instance of
Child1. So when debuggers decode Child1's concrete instances, they need
to fetch the definition for Child2 in the corresponding abstract
instance: the DW_AT_abstract_origin link on the lexical block that
embeds Child1 enables them to do that.

Bootstrapped and regtested on x86_64-linux.

gcc/ChangeLog:

* dwarf2out.c (add_abstract_origin_attribute): Adjust
documentation comment.  For BLOCK nodes, add a
DW_AT_abstract_origin attribute that points to the DIE generated
for the origin BLOCK.
(gen_lexical_block_die): Call add_abstract_origin_attribute for
blocks from inlined functions.

gcc/testsuite/Changelog:

* gcc.dg/debug/dwarf2/nested_fun.c: New testcase.

From-SVN: r236065

[RTEMS] Fix moxie libgcc support

libgcc/

PR libgcc/70720
* config.host (moxie-*-rtems*): Merge this stanza with other moxie
targets so the same extra_parts are built.  Also have tmake_file add
on to its value rather than override.

From-SVN: r236064

[libatomic] Add missing files for RTEMS support

Add missing files for:

2016-04-27  Sebastian Huber  <sebastian.huber@embedded-brains.de>

* configure.tgt (configure_tgt_pre_target_cpu_XCFLAGS): New variable.
(*-*-rtems*): New supported target.
* config/rtems/host-config.h: New file.
* config/rtems/lock.c: Likewise.

From-SVN: r236060

Daily bump.

From-SVN: r236056

[RS6000] Stop regrename twiddling with split-stack prologue

PR target/70947
* config/rs6000/rs6000.c (rs6000_expand_split_stack_prologue): Stop
regrename modifying insns saving lr before __morestack call.
* config/rs6000/rs6000.md (split_stack_return): Similarly for
insns restoring lr after __morestack call.

From-SVN: r236052

* sv.po: Update.

From-SVN: r236050

i386.md (set_got, [...]): Remove constraints from expanders.

* config/i386/i386.md (set_got, set_got_labelled, lwp_llwpcb,
lwp_lwpval<mode>3, lwp_lwpins<mode>3): Remove constraints from
expanders.
* config/i386/sse.md (vec_interleave_high<mode>,
vec_interleave_low<mode>, <avx512>_vpermi2var<mode>3_maskz,
<avx512>_vpermt2var<mode>3_maskz): Likewise.

From-SVN: r236045

rs6000.c (rs6000_reassociation_width): Add function for TARGET_SCHED_REASSOCIATION_WIDTH to enable parallel...

        * config/rs6000/rs6000.c (rs6000_reassociation_width): Add
        function for TARGET_SCHED_REASSOCIATION_WIDTH to enable
        parallel reassociation for power8 and forward.

From-SVN: r236043

i386.md (absneg splitters with general regs): Use general_reg_operand predicate.

* config/i386/i386.md (absneg splitters with general regs): Use
general_reg_operand predicate.
(btsq peephole2): Use x86_64_immediate_operand to check if new
value is suitable for immediate operand.  Generate emitted insn
using RTL expressions.
(btcq peephole2): Ditto.
(btrq peephole2): Ditto.  Generate correct immediate operand
for AND masking.

testsuite/ChangeLog:

* gcc.target/i386/fabsneg-1.c New test.

From-SVN: r236042

Fix handling of negative bitpos in expand_debug_expr

expand_debug_expr handled negative bit positions using:

                else if (bitpos < 0)
                  {
                    HOST_WIDE_INT units
                      = (-bitpos + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
                    op0 = adjust_address_nv (op0, mode1, units);
                    bitpos += units * BITS_PER_UNIT;
                  }

Here "units" is the negative of the (negative) byte offset, so I think
we should be offsetting OP0 by -units instead.  E.g. a bitpos of -17
would give units==3, so this code would move OP0 up by 3 bytes and set
bitpos to 7, giving a total bitpos of 31.

Just noticed by inspection.  An assert triggered for:

        gcc.target/i386/mpx/bitfields-1-lbv.c
        gcc.target/i386/mpx/field-addr-7-lbv.c
        gcc.target/i386/mpx/reference-3-lbv.cpp
        gcc.target/i386/mpx/reference-4-lbv.cpp

at -m32 but otherwise this case doesn't seem to trigger during a
bootstrap and regtest.

Tested on x86_64-linux-gnu.

gcc/
* cfgexpand.c (expand_debug_expr): Fix address offset for negative
bitpos.

From-SVN: r236041

Missing pointer dereference in tree-affine.c

wide_int_constant_multiple_p used:

          if (*mult_set && mult != 0)
            return false;

to check whether we had previously seen a nonzero multiple, but "mult" is
a pointer to the previous value rather than the previous value itself.

Noticed by inspection while working on another patch, so I don't have a
testcase.  I tried adding an assert for combinations that were wrongly
rejected before but it didn't trigger during a bootstrap and regtest.

Tested on x86_64-linux-gnu.

gcc/
* tree-affine.c (wide_int_constant_multiple_p): Add missing
pointer dereference.

From-SVN: r236040

MAINTAINERS (Write After Approval): Add myself.

2016-05-09  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

* MAINTAINERS (Write After Approval): Add myself.

From-SVN: r236034

[RS6000] Fragile testcase breaks with -frename-registers

PR testsuite/70826
* gcc.target/powerpc/savres.c: Compile with -fno-rename-registers.

From-SVN: r236033

re PR tree-optimization/70985 (ICE on valid code at -O3 on x86_64-linux-gnu: verify_gimple failed)

2016-05-09  Richard Biener  <rguenther@suse.de>

PR tree-optimization/70985
* match.pd (BIT_FIELD_REF -> (type)): Disable on GIMPLE when
op0 isn't a gimple register.

* gcc.dg/torture/pr70985.c: New testcase.

From-SVN: r236032

Add pipeline description for MSA.

gcc/
* config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic)
(i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store)
(i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l)
(i6400_fpu_mult): New cpu units.
(i6400_msa_add_d, i6400_msa_int_add, i6400_msa_short_logic3)
(i6400_msa_short_logic2, i6400_msa_short_logic, i6400_msa_move)
(i6400_msa_cmp, i6400_msa_short_float2, i6400_msa_div_d)
(i6400_msa_div_w, i6400_msa_div_h, i6400_msa_div_b)
(i6400_msa_copy, i6400_msa_branch, i6400_fpu_msa_store)
(i6400_fpu_msa_load, i6400_fpu_msa_move, i6400_msa_long_logic1)
(i6400_msa_long_logic2, i6400_msa_mult, i6400_msa_long_float2)
(i6400_msa_long_float4, i6400_msa_long_float5)
(i6400_msa_long_float8, i6400_msa_fdiv_df)
(i6400_msa_fdiv_sf): New reservations.
* config/mips/p5600.md (p5600_fpu_intadd, p5600_fpu_cmp)
(p5600_fpu_float, p5600_fpu_logic_a, p5600_fpu_logic_b)
(p5600_fpu_div, p5600_fpu_logic, p5600_fpu_float_a)
(p5600_fpu_float_b, p5600_fpu_float_c, p5600_fpu_float_d)
(p5600_fpu_mult, p5600_fpu_fdiv, p5600_fpu_load): New cpu units.
(msa_short_int_add, msa_short_logic, msa_short_logic_move_v)
(msa_short_cmp, msa_short_float2, msa_short_logic3)
(msa_short_store4, msa_long_load, msa_short_store)
(msa_long_logic, msa_long_float2, msa_long_float4)
(msa_long_float5, msa_long_float8, msa_long_mult)
(msa_long_fdiv, msa_long_div): New reservations.

From-SVN: r236031