Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

DSP48E1 sim model: add SIMD tests

Signed-off-by: David Shah <dave@ds0.me>

DSP48E1 model: test CE inputs

Signed-off-by: David Shah <dave@ds0.me>

DSP48E1 sim model: fix seq tests and add preadder tests

Signed-off-by: David Shah <dave@ds0.me>

DSP48E1 sim model: seq test working

Signed-off-by: David Shah <dave@ds0.me>

DSP48E1 sim model: Comb, no pre-adder, mode working

Signed-off-by: David Shah <dave@ds0.me>

[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>

[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>

Fix compile error

Run "opt_expr -fine" instead of "wreduce" due to #1213

Do not SigSpec::extract() beyond bounds

Merge remote-tracking branch 'origin/master' into xc7dsp

Do not pack registers if (* keep *)

Merge pull request #1248 from YosysHQ/eddie/abc9_speedup

abc9: speedup by using using "clean" more efficiently

Add comment

Revert "Add TODO"

This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.

Add TODO

Compute box_lookup just once

Run "clean" on mapped_mod in its own design

Run "clean -purge" on holes_module in its own design

Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes

ecp5: Make cells_sim.v consistent with nextpnr

ecp5: Make cells_sim.v consistent with nextpnr

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #1213 from YosysHQ/eddie/wreduce_add

wreduce/opt_expr: improve width reduction for $add and $sub cells

[wip] DSP48E1 sim model improvements

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor

 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

Merge pull request #1249 from mmicko/anlogic_fix

anlogic : Fix alu mapping

Merge pull request #1252 from YosysHQ/clifford/fix1231

Fix handling of functions/tasks without top-level begin-end block

Merge pull request #1253 from YosysHQ/clifford/check

Be less aggressive with running design->check()

Merge pull request #1257 from YosysHQ/clifford/cellcosts

Redesign of cell cost API

Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #1241 from YosysHQ/clifford/jsonfix

Improved JSON attr/param encoding

Tweak default gate costs, cleanup "stat -tech cmos"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Redesign of cell cost API

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add signed opt_expr tests

Add signed test

Move LSB-trimming functionality from wreduce to opt_expr

Add SigSpec::extract_end() convenience function

Restore original SigSpec::extract()

Move LSB tests from wreduce to opt_expr

Merge remote-tracking branch 'origin/master' into eddie/wreduce_add

Merge pull request #1232 from YosysHQ/dave/write_gzip

Add support for writing gzip-compressed files

[wip] DSP48E1 sim model improvements

Signed-off-by: David Shah <dave@ds0.me>

Be less aggressive with running design->check()

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add test for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>

Add support for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>

Fix handling of functions/tasks without top-level begin-end block, fixes #1231

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1251 from YosysHQ/clifford/nmux

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

[wip] DSP48E1 sim model improvements

Signed-off-by: David Shah <dave@ds0.me>

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

Signed-off-by: Clifford Wolf <clifford@clifford.at>

anlogic : Fix alu mapping

Merge pull request #1242 from jfng/fix-proc_prune-partial

proc_prune: Promote partially redundant assignments.

Merge pull request #1238 from mmicko/vsbuild_fix

Visual Studio build fix

Merge pull request #1239 from mmicko/mingw_fix

Fix formatting for msys2 mingw build

Add comment about supporting $dffe in ice40_dsp

Pack P register properly

Trim Y_WIDTH

Add DSP_SIGNEDONLY back

DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH

Change $__softmul back to $mul

Cope with sign extension in mul2dsp

Revert "Do not do sign extension in techmap; let packer do it"

This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.

Merge remote-tracking branch 'origin/master' into xc7dsp

Fix B_WIDTH > DSP_B_MAXWIDTH case

CO is sign extension only if signed multiplier

Fix typo

Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map

xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER

Fix linking issue for new mxe and pthread

Fix yosys linking for mxe

New mxe hacks needed to support 2ca237e

Fix formatting for msys2 mingw build using GetSize

proc_prune: Promote partially redundant assignments.

Update JSON front-end to process new attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Implement improved JSON attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Do not compute sign bit if result is zero

For signed multipliers, compute sign bit separately...

Restore old CO behaviour

Helper: SigSpec::operator[] to accept negative indices

Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.

Merge pull request #1233 from YosysHQ/clifford/defer

Call "read_verilog" with -defer from "read"

Visual Studio build fix

Merge remote-tracking branch 'upstream/master'

RST -> RSTBRST for RAMB8BWER

Merge pull request #1228 from YosysHQ/dave/yy_buf_size

verilog_lexer: Increase YY_BUF_SIZE to 65536

Merge pull request #1234 from mmicko/fix_gzip_no_exist

Fix case when file does not exist

Fix case when file does not exist

Update README to use "read" instead of "read_verilog"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Call "read_verilog" with -defer from "read"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1226 from YosysHQ/dave/gzip

Add support for gzip'd input files

Fix spacing

Update test_autotb doc to reflect default value of zero

Add doc for "test_autotb -seed" option

Pop the CO bit from O

Allow adders/accumulators with 33 bits using CO output

Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>

verilog_lexer: Increase YY_BUF_SIZE to 65536

Signed-off-by: David Shah <dave@ds0.me>

Fix frontend auto-detection for gzipped input

Signed-off-by: David Shah <dave@ds0.me>

Add support for reading gzip'd input files

Signed-off-by: David Shah <dave@ds0.me>

Merge branch 'master' of github.com:YosysHQ/yosys

Bump abc to fix &mfs bug

Merge branch 'ZirconiumX-synth_intel_m9k'