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Michael Neuling [Fri, 6 Sep 2019 05:05:01 +0000 (15:05 +1000)]
Fix verific script with new VHDL files
This really needs to be auto generated, but here we are.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Fri, 6 Sep 2019 00:09:26 +0000 (10:09 +1000)]
Merge pull request #17 from antonblanchard/writeback-signal
Use a better input signal in writeback
Anton Blanchard [Thu, 5 Sep 2019 23:46:55 +0000 (09:46 +1000)]
Use a better input signal in writeback
w_in comes from the execution unit, it makes more sense to call
it e_in.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 3 Sep 2019 20:33:40 +0000 (06:33 +1000)]
Merge pull request #16 from antonblanchard/decode2_rework2
Rework decode2
Anton Blanchard [Tue, 3 Sep 2019 02:44:03 +0000 (12:44 +1000)]
Rework decode2
The decode2 stage was spaghetti code and needed cleaning up.
Create a series of functions to pull fields from a ppc instruction
and also a series of helpers to extract values for the execution
units.
As suggested by Paul, we should pass all signals to the execution
units and only set the valid signal conditionally, which should
use less resources.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 31 Aug 2019 03:34:38 +0000 (13:34 +1000)]
Merge pull request #13 from mikey/dynamic-ranges
Remove dynamic ranges from code
Michael Neuling [Wed, 28 Aug 2019 23:47:45 +0000 (09:47 +1000)]
Remove dynamic ranges from code
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.
Also add basic script to run verific and generate verilog.
1. https://www.verific.com/
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Thu, 29 Aug 2019 23:06:48 +0000 (09:06 +1000)]
Merge pull request #10 from antonblanchard/arty-fix
Arty A7 reset pin is C2
Anton Blanchard [Thu, 29 Aug 2019 22:39:44 +0000 (08:39 +1000)]
Arty A7 reset pin is C2
Use C2 for reset, and fix up a few whitespace issues.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 29 Aug 2019 22:38:13 +0000 (08:38 +1000)]
Merge pull request #7 from riktw/fusesoc_arty_a7
Fusesoc arty a7
Anton Blanchard [Thu, 29 Aug 2019 22:26:35 +0000 (08:26 +1000)]
Merge pull request #9 from antonblanchard/travis-fix
A few Travis CI fixes
Anton Blanchard [Thu, 29 Aug 2019 22:12:54 +0000 (08:12 +1000)]
A few Travis CI fixes
- Switch to using ghdl/vunit:llvm, it's a smaller container
- We need to "apt update" before installing packages
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
riktw [Tue, 27 Aug 2019 20:20:02 +0000 (22:20 +0200)]
Added support for building for Arty A7 boards
Anton Blanchard [Wed, 28 Aug 2019 21:46:51 +0000 (07:46 +1000)]
Merge pull request #5 from antonblanchard/travis-test
Add an initial travis.yml
Anton Blanchard [Tue, 27 Aug 2019 00:40:43 +0000 (10:40 +1000)]
Add an initial travis.yml
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 28 Aug 2019 04:50:11 +0000 (14:50 +1000)]
Add srd and srw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 28 Aug 2019 04:07:29 +0000 (14:07 +1000)]
Add sim only divw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 12:12:33 +0000 (22:12 +1000)]
Fix ghdl build error with pp_soc_memory
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 02:02:00 +0000 (12:02 +1000)]
micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 01:50:25 +0000 (11:50 +1000)]
Merge pull request #6 from mikey/gif
Add pretty gif demo of MicroPython on Microwatt to README.md
Anton Blanchard [Tue, 27 Aug 2019 01:44:34 +0000 (11:44 +1000)]
Add -Wall to CFLAGS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 27 Aug 2019 01:19:15 +0000 (11:19 +1000)]
Add pretty gif demo of MicroPython on Microwatt to README.md
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Mon, 26 Aug 2019 13:11:51 +0000 (23:11 +1000)]
Add missing argument to fprintf warning
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 12:32:15 +0000 (22:32 +1000)]
Add some initial FPGA synthesis instructions
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 02:33:15 +0000 (12:33 +1000)]
Rebuild hello world assuming a 50MHz clock
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 12:02:17 +0000 (22:02 +1000)]
Merge pull request #3 from olofk/plle2
Add and use plle2 primitive for nexys boards
Olof Kindgren [Sat, 24 Aug 2019 09:25:21 +0000 (11:25 +0200)]
Add and use plle2 primitive for nexys boards
Anton Blanchard [Mon, 26 Aug 2019 01:33:38 +0000 (11:33 +1000)]
Merge pull request #4 from sharkcz/build
don't cross compile when on Power
Dan Horák [Sat, 24 Aug 2019 12:02:35 +0000 (14:02 +0200)]
don't cross compile when on Power
Anton Blanchard [Fri, 23 Aug 2019 22:59:17 +0000 (08:59 +1000)]
Add a simple hello_world example that also echos input
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 23 Aug 2019 19:25:48 +0000 (05:25 +1000)]
Merge pull request #2 from olofk/fusesoc_nexys_a7
Fusesoc nexys a7
Olof Kindgren [Fri, 23 Aug 2019 12:20:20 +0000 (14:20 +0200)]
Added synthesis target
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.
To run synthesis only for a part, run
fusesoc run --target=synth --tool=vivado microwatt --part=<part>
where part is a valid Xilinx part such as xc7a100tcsg324-1
Olof Kindgren [Fri, 23 Aug 2019 12:09:06 +0000 (14:09 +0200)]
Add Nexys Video support
Olof Kindgren [Fri, 23 Aug 2019 11:32:05 +0000 (13:32 +0200)]
Add FuseSoC core description file with Nexys A7 support
Olof Kindgren [Fri, 23 Aug 2019 11:19:11 +0000 (13:19 +0200)]
Add constraint file for Nexys A7
Olof Kindgren [Fri, 23 Aug 2019 11:18:39 +0000 (13:18 +0200)]
Expose ram init file and memory size through toplevel
Olof Kindgren [Fri, 23 Aug 2019 11:17:35 +0000 (13:17 +0200)]
Add dummy clock generator
Anton Blanchard [Fri, 23 Aug 2019 06:23:53 +0000 (16:23 +1000)]
Add a few more FPGA related files
Add a temporary gcc patch to remove hardware divide instructions.
Also add a firmware.hex file built with a gcc with the above patch.
Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 22 Aug 2019 06:46:13 +0000 (16:46 +1000)]
Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
projects / microwatt.git / log