mesa.git
13 years agomesa/st: add RGTC format support.
Dave Airlie [Thu, 24 Feb 2011 23:24:15 +0000 (09:24 +1000)]
mesa/st: add RGTC format support.

this just adds a format check + format conversion.

13 years agoswrast: add RGTC support
Dave Airlie [Thu, 24 Feb 2011 04:27:18 +0000 (14:27 +1000)]
swrast: add RGTC support

13 years agomesa: Add RGTC texture store/fetch support.
Dave Airlie [Tue, 22 Feb 2011 00:35:15 +0000 (10:35 +1000)]
mesa: Add RGTC texture store/fetch support.

This adds support for the RGTC unsigned and signed
texture storage and fetch methods.

the code is a port of the DXT5 alpha compression code.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agomesa: make_float_temp_image non-static
Dave Airlie [Thu, 24 Feb 2011 23:12:40 +0000 (09:12 +1000)]
mesa: make_float_temp_image non-static

We need this to do signed stuff for RGTC.

13 years agorgtc: llvmpipe/softpipe refuse RGTC until u_format has support.
Dave Airlie [Mon, 28 Feb 2011 03:33:17 +0000 (13:33 +1000)]
rgtc: llvmpipe/softpipe refuse RGTC until u_format has support.

So far I haven't implemented the u_format code for these.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agor300g: force swizzles for RGTC
Dave Airlie [Sun, 27 Feb 2011 07:00:50 +0000 (17:00 +1000)]
r300g: force swizzles for RGTC

still can't get signed to work

13 years agor600g: implement instanced drawing support
Christian König [Mon, 28 Feb 2011 01:00:01 +0000 (02:00 +0100)]
r600g: implement instanced drawing support

13 years agost/mesa & v_bug_mgr: two small instanced drawing fixes
Christian König [Mon, 28 Feb 2011 00:54:36 +0000 (01:54 +0100)]
st/mesa & v_bug_mgr: two small instanced drawing fixes

13 years agoRevert "r600g: Don't negate result of ABS instruction"
Dave Airlie [Mon, 28 Feb 2011 01:10:10 +0000 (11:10 +1000)]
Revert "r600g: Don't negate result of ABS instruction"

This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254.

This actually breaks gears here on my rv670.

13 years agor600g: Process TRUNC with tgis_op2
Fabian Bieler [Sun, 27 Feb 2011 15:10:55 +0000 (16:10 +0100)]
r600g: Process TRUNC with tgis_op2

TRUNC is neither a scalar instruction nor exclusive to the Trans unit.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agor600g: Don't negate result of ABS instruction
Fabian Bieler [Fri, 25 Feb 2011 09:11:37 +0000 (10:11 +0100)]
r600g: Don't negate result of ABS instruction

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agoi915g: implement cache flushing
Daniel Vetter [Fri, 25 Feb 2011 22:40:27 +0000 (23:40 +0100)]
i915g: implement cache flushing

With an extremely dumb strategy. But it's the same i915c employs.

Also improve the hw_atom code slightly by statically specifying the
required batch space. For extremely variably stuff (shaders, constants)
it would probably be better to add a new parameter to the hw_atom->validate
function.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: buffer validation for blitter
Daniel Vetter [Fri, 25 Feb 2011 21:51:03 +0000 (22:51 +0100)]
i915g: buffer validation for blitter

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: buffer validation for render state
Daniel Vetter [Sun, 27 Feb 2011 20:57:31 +0000 (21:57 +0100)]
i915g: buffer validation for render state

Also contains the first few bits for hw state atoms.

v2: Implement suggestion by Jakob Bornecrantz.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g/winsys: buffer validation support
Daniel Vetter [Sun, 27 Feb 2011 16:51:48 +0000 (17:51 +0100)]
i915g/winsys: buffer validation support

v2: Add the batch bo to the libdrm validation lost, for otherwise
libdrm won't take previously used buffers into account.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: add raw batchbuffer dumping in drm winsys
Daniel Vetter [Sun, 27 Feb 2011 15:32:38 +0000 (16:32 +0100)]
i915g: add raw batchbuffer dumping in drm winsys

These files can be decoded with intel_dump_decode from the intel-gpu-tools
available at:

http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: cleanup static state calculation, part 2
Daniel Vetter [Sat, 26 Feb 2011 14:53:01 +0000 (15:53 +0100)]
i915g: cleanup static state calculation, part 2

Now also for the DRAW_RECT command

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: cleanup static state calculation, part 1
Daniel Vetter [Sat, 26 Feb 2011 14:24:51 +0000 (15:24 +0100)]
i915g: cleanup static state calculation, part 1

Move it to i915_state_static.c This way i915_emit_state.c only emits
state and doesn't (re)calculate it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoglsl/builtins: Fix return type for textureSize sampler2DArray variants.
Kenneth Graunke [Sat, 26 Feb 2011 00:33:40 +0000 (16:33 -0800)]
glsl/builtins: Fix return type for textureSize sampler2DArray variants.

A copy and paste error.

13 years agoglx: Adjust the MESA_multithread_makecurrent spec to match implementation.
Eric Anholt [Thu, 24 Feb 2011 23:25:59 +0000 (15:25 -0800)]
glx: Adjust the MESA_multithread_makecurrent spec to match implementation.

This came out of discussion at the office today, and we agreed that
solving this for indirect wasn't really interesting, though the
server-side change would be of a similar level of difficulty.

13 years agointel: Use the current context rather than last bound context for a drawable.
Eric Anholt [Tue, 15 Feb 2011 02:57:49 +0000 (18:57 -0800)]
intel: Use the current context rather than last bound context for a drawable.

If another thread bound a context to the drawable then unbound it, the
driContextPriv would end up NULL.

With the previous two fixes, this fixes glx-multithread-makecurrent-2,
despite the issue not being about the multithreaded makecurrent.

13 years agodri2: Don't call the dri2 flush hook for swapbuffers unless we have a context.
Eric Anholt [Tue, 15 Feb 2011 03:03:37 +0000 (19:03 -0800)]
dri2: Don't call the dri2 flush hook for swapbuffers unless we have a context.

The driver only has one reasonable place to look for its context to
flush anything, which is the current context.  Don't bother it with
having to check.

13 years agoglx: Don't do the implicit glFlush in SwapBuffers if it's the wrong drawable.
Eric Anholt [Tue, 15 Feb 2011 02:38:33 +0000 (18:38 -0800)]
glx: Don't do the implicit glFlush in SwapBuffers if it's the wrong drawable.

The GLX Spec says you only implicitly glFlush if the drawable being
swapped is the current context's drawable.

13 years agomesa: Add new MESA_multithread_makecurrent extension.
Eric Anholt [Fri, 4 Feb 2011 01:26:02 +0000 (17:26 -0800)]
mesa: Add new MESA_multithread_makecurrent extension.

This extension allows a client to bind one context in multiple threads
simultaneously.  It is then up to the client to manage synchronization of
access to the GL, just as normal multithreaded GL from multiple contexts
requires synchronization management to shared objects.

13 years agoi915g: make dynamic state emission actually lazy
Daniel Vetter [Sat, 26 Feb 2011 18:11:32 +0000 (19:11 +0100)]
i915g: make dynamic state emission actually lazy

Premature semicolon.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agogallivm: Initialize stack values
Jakob Bornecrantz [Sat, 26 Feb 2011 19:12:27 +0000 (20:12 +0100)]
gallivm: Initialize stack values

valgrind gives me a warning with llvmpipe with profile builds but
not debug builds, this seems to fix the issue at least.

13 years agoglsl/Makefile: Remove builtin_function.cpp if generation fails.
Arkadiusz Miskiewicz [Sat, 26 Feb 2011 18:26:09 +0000 (10:26 -0800)]
glsl/Makefile: Remove builtin_function.cpp if generation fails.

Fixes bug #34346.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
13 years agoi915g: Handle null constants properly
Jakob Bornecrantz [Sat, 26 Feb 2011 14:45:13 +0000 (15:45 +0100)]
i915g: Handle null constants properly

13 years agoi915g: fix null deref in draw_rect emission
Daniel Vetter [Fri, 25 Feb 2011 22:32:48 +0000 (23:32 +0100)]
i915g: fix null deref in draw_rect emission

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: simplify math in constants emission
Daniel Vetter [Fri, 25 Feb 2011 17:03:16 +0000 (18:03 +0100)]
i915g: simplify math in constants emission

The old code even falls apart for nr == 0 (which is caught earlier, but)!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
13 years agoi915g: Use the same debug env vars in drm and sw winsys
Jakob Bornecrantz [Sat, 26 Feb 2011 14:24:13 +0000 (15:24 +0100)]
i915g: Use the same debug env vars in drm and sw winsys

13 years agoi915g: Use unchecked writes in sw winsys batchbuffer
Jakob Bornecrantz [Sat, 26 Feb 2011 00:42:19 +0000 (01:42 +0100)]
i915g: Use unchecked writes in sw winsys batchbuffer

13 years agoCheck for out of memory when creating fence
Alan Hourihane [Sat, 26 Feb 2011 10:30:19 +0000 (10:30 +0000)]
Check for out of memory when creating fence

13 years agoutil: Don't destroy shaders null shaders
Jakob Bornecrantz [Sat, 26 Feb 2011 01:32:22 +0000 (02:32 +0100)]
util: Don't destroy shaders null shaders

Fixes regression from a08e612fd8e7ca2ac2fef8961e56e5b094033717

13 years agoutil: Don't create array texture shaders if the driver doesn't support it
Jakob Bornecrantz [Fri, 25 Feb 2011 23:50:52 +0000 (00:50 +0100)]
util: Don't create array texture shaders if the driver doesn't support it

13 years agoi965/fs: Initial plumbing to support TXD.
Kenneth Graunke [Fri, 25 Feb 2011 01:49:07 +0000 (17:49 -0800)]
i965/fs: Initial plumbing to support TXD.

This adds the opcode and the code to convert ir_txd to OPCODE_TXD;
it doesn't actually add support yet.

13 years agoi965/fs: Complete TXL support on gen5+.
Kenneth Graunke [Thu, 28 Oct 2010 19:53:21 +0000 (12:53 -0700)]
i965/fs: Complete TXL support on gen5+.

Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.

13 years agoi965/fs: Complete TXL support on gen4.
Kenneth Graunke [Thu, 28 Oct 2010 20:12:20 +0000 (13:12 -0700)]
i965/fs: Complete TXL support on gen4.

Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.

13 years agoi965/fs: Use a properly named constant in TXB handling.
Kenneth Graunke [Thu, 28 Oct 2010 20:07:11 +0000 (13:07 -0700)]
i965/fs: Use a properly named constant in TXB handling.

The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're
doing a non-bias texture lookup.  It has the same value as the new constant
BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no
functional changes.

13 years agoi965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.
Kenneth Graunke [Thu, 28 Oct 2010 20:04:41 +0000 (13:04 -0700)]
i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.

From volume 4, page 161 of the public i965 documentation.

13 years agogallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issue
Jerome Glisse [Fri, 25 Feb 2011 16:56:29 +0000 (11:56 -0500)]
gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issue

There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa
due to ureg_src size, reshuffling the structure member to better better
alignment work around the issue.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893

7.9 + 7.10 candidate

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
13 years agogallium/st: place value check before value is use
Jerome Glisse [Fri, 25 Feb 2011 16:49:23 +0000 (11:49 -0500)]
gallium/st: place value check before value is use

7.9 & 7.10 candidate

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
13 years agogallium/util: add 1d/2d mipmap generation support
Dave Airlie [Fri, 25 Feb 2011 04:37:06 +0000 (14:37 +1000)]
gallium/util: add 1d/2d mipmap generation support

so far only hw mipmap generation is testing on softpipe,
passes test added to piglit.

this requires another patch to mesa to let array textures mipmaps
even start to happen.

13 years agoscons: Reduce all Cygwin platform names to 'cygwin'.
Vinson Lee [Fri, 25 Feb 2011 03:49:37 +0000 (19:49 -0800)]
scons: Reduce all Cygwin platform names to 'cygwin'.

platform.system in SCons on Cygwin includes the OS version number.
Windows XP - CYGWIN_NT-5.1
Windows Vista - CYGWIN_NT-6.0
Windows 7 - CYGWIN_NT-6.1

Reduce all Cygwin platform variants to just 'cygwin' so anything
downstream can simply use 'cygwin' instead of the different full
platform names.

13 years agor600g: explicity set sign bits for RGTC
Dave Airlie [Thu, 24 Feb 2011 23:13:14 +0000 (09:13 +1000)]
r600g: explicity set sign bits for RGTC

13 years agor600g: bc 4/5 or rgtc textures need to be tiled as well.
Dave Airlie [Thu, 24 Feb 2011 03:55:25 +0000 (13:55 +1000)]
r600g: bc 4/5 or rgtc textures need to be tiled as well.

Make the s3tc upload code more generic.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agor300g: explicit sign bits on RGTC textures
Dave Airlie [Thu, 24 Feb 2011 23:14:53 +0000 (09:14 +1000)]
r300g: explicit sign bits on RGTC textures

13 years agoi965: Increase Sandybridge point size clamp in the clip state.
Kenneth Graunke [Thu, 24 Feb 2011 19:17:02 +0000 (11:17 -0800)]
i965: Increase Sandybridge point size clamp in the clip state.

255.875 matches the hardware documentation.  Presumably this was a typo.

NOTE: This is a candidate for the 7.10 branch, along with
      commit 2bfc23fb86964e4153f57f2a56248760f6066033.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agointel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
Neil Roberts [Sat, 5 Feb 2011 10:21:11 +0000 (10:21 +0000)]
intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer

In the case where glBlitFramebuffer is being used to copy to a texture
without scaling it is faster if we can use the hardware to do a blit
rather than having to do a texture render. In most of the drivers
glCopyTexSubImage2D will use a blit so this patch makes it check for
when glBlitFramebuffer is doing a simple copy and then divert to
glCopyTexSubImage2D.

This was originally proposed as an extension to the common meta-ops.
However, it was rejected as using the BLT is only advantageous for Intel
hardware.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agonvc0: fix PointCoord enable in FP header
Christoph Bumiller [Wed, 23 Feb 2011 13:54:25 +0000 (14:54 +0100)]
nvc0: fix PointCoord enable in FP header

13 years agonvc0: change TGSI CMP translation to use slct
Christoph Bumiller [Wed, 23 Feb 2011 16:29:02 +0000 (17:29 +0100)]
nvc0: change TGSI CMP translation to use slct

Saves us the explicit compare instruction needed with selp.

13 years agonvc0: sprite coord enable is per GENERIC, not overall index
Christoph Bumiller [Wed, 23 Feb 2011 14:00:26 +0000 (15:00 +0100)]
nvc0: sprite coord enable is per GENERIC, not overall index

13 years agonvc0: fix new_value calls using type instead of size
Christoph Bumiller [Thu, 24 Feb 2011 14:28:04 +0000 (15:28 +0100)]
nvc0: fix new_value calls using type instead of size

13 years agonvc0: set local memory usage info in shader header
Christoph Bumiller [Thu, 24 Feb 2011 16:26:44 +0000 (17:26 +0100)]
nvc0: set local memory usage info in shader header

Before this, l[] access was a no-op.

13 years agonvc0: don't fold loads from local memory
Christoph Bumiller [Sun, 20 Feb 2011 12:13:11 +0000 (13:13 +0100)]
nvc0: don't fold loads from local memory

13 years agonvc0: presin and preex2 can load from const space
Christoph Bumiller [Thu, 24 Feb 2011 16:23:23 +0000 (17:23 +0100)]
nvc0: presin and preex2 can load from const space

13 years agonvc0: kick out empty live ranges
Christoph Bumiller [Tue, 22 Feb 2011 20:50:17 +0000 (21:50 +0100)]
nvc0: kick out empty live ranges

They affect overlap tests even though they're actually empty.

13 years agonvc0: preemptively insert branch at ENDIF
Christoph Bumiller [Thu, 24 Feb 2011 16:22:15 +0000 (17:22 +0100)]
nvc0: preemptively insert branch at ENDIF

Might be necessary if a block sneaks in somewhere, like a common
block for moves of phi sources after a loop break.

This is harmless and normally will be removed before emission.

13 years agonvc0: correct allocation of constrained registers
Christoph Bumiller [Thu, 24 Feb 2011 16:08:23 +0000 (17:08 +0100)]
nvc0: correct allocation of constrained registers

In linear scan we can't allocate multiple values with different
live ranges at the same time to assign them consecutive regs.

Maybe we should just switch to graph coloring for all values ...

13 years agonvc0: sync textures with render targets ourselves
Christoph Bumiller [Thu, 24 Feb 2011 16:04:49 +0000 (17:04 +0100)]
nvc0: sync textures with render targets ourselves

Fixes for example piglit/fbo-flushing and nexuiz' bloom effect.

13 years agonvc0: improve userspace fencing
Christoph Bumiller [Sun, 20 Feb 2011 16:57:47 +0000 (17:57 +0100)]
nvc0: improve userspace fencing

Before, there were situations in which we never checked the fences
for completion (some loading screens for example) and thus never
released memory.

13 years agonvc0: values for undefined outputs must have file GPR
Christoph Bumiller [Sun, 20 Feb 2011 14:10:02 +0000 (15:10 +0100)]
nvc0: values for undefined outputs must have file GPR

13 years agonvc0: multiply polygon offset units by 2
Christoph Bumiller [Sat, 19 Feb 2011 19:26:49 +0000 (20:26 +0100)]
nvc0: multiply polygon offset units by 2

Wasn't sure if this still was necessary because the piglit test
started to fail at some point on nv50 where we already do this.

13 years agonvc0: fix SSG
Christoph Bumiller [Sat, 19 Feb 2011 19:26:29 +0000 (20:26 +0100)]
nvc0: fix SSG

13 years agonvc0: don't visit target blocks of a loop break multiple times
Christoph Bumiller [Sat, 19 Feb 2011 13:18:28 +0000 (14:18 +0100)]
nvc0: don't visit target blocks of a loop break multiple times

13 years agonvc0: don't overwrite phi sources at the end of a loop
Christoph Bumiller [Sat, 19 Feb 2011 13:14:40 +0000 (14:14 +0100)]
nvc0: don't overwrite phi sources at the end of a loop

Except the reference to its own result.

13 years agogallium/utils: Fix vertex element setup
Fabian Bieler [Thu, 24 Feb 2011 09:56:16 +0000 (10:56 +0100)]
gallium/utils: Fix vertex element setup

Check if element was translated per element instead of per buffer.

13 years agosvga: Ensure rendertargets and textures are always rebound at every command buffer...
José Fonseca [Wed, 23 Feb 2011 13:32:37 +0000 (13:32 +0000)]
svga: Ensure rendertargets and textures are always rebound at every command buffer start.

The svga_update_state() mechanism is inadequate as it will always end up
flushing the primitives before processing the SVGA_NEW_COMMAND_BUFFER
dirty state flag.

13 years agoi965: Remember to pack the constant blend color as floats into the batch
Chris Wilson [Thu, 24 Feb 2011 12:59:52 +0000 (12:59 +0000)]
i965: Remember to pack the constant blend color as floats into the batch

Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agointel: Reset the buffer offset after releasing reference to packed upload
Chris Wilson [Thu, 24 Feb 2011 12:29:51 +0000 (12:29 +0000)]
intel: Reset the buffer offset after releasing reference to packed upload

Fixes oglc/vbo(basic.bufferdata)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agoi965: Unmap the correct pointer after discontiguous upload
Chris Wilson [Thu, 24 Feb 2011 10:58:22 +0000 (10:58 +0000)]
i965: Unmap the correct pointer after discontiguous upload

Fixes piglit/fbo-depth-sample-compare:

==14722== Invalid free() / delete / delete[]
==14722==    at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722==    by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722==    by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==    by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==    by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==    by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==    by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==    by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==    by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==    by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==  Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722==    at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722==    by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722==    by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==    by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==    by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==    by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==    by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==    by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==    by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==    by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==    by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agointel: Protect against waiting on a NULL render target bo
Chris Wilson [Thu, 24 Feb 2011 10:12:37 +0000 (10:12 +0000)]
intel: Protect against waiting on a NULL render target bo

If we fall back to software rendering due to the render target being
absent (GPU hang or other error in creating the named target), then we
do not need to nor should we wait upon the results.

Reported-by: Magnus Kessler <Magnus.Kessler@gmx.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agor600g: EXT_texture_array support.
Dave Airlie [Thu, 17 Feb 2011 05:07:57 +0000 (15:07 +1000)]
r600g: EXT_texture_array support.

This adds EXT_texture_array support to r600g, it passes the piglit
array-texture test but I suspect may not be complete.

It currently requires a kernel patch to fix the CS checker to allow
these, so you need to use R600_ARRAY_TEXTURE=true for now
to enable them.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agost/mesa: treat 1D ARRAY upload like a depth or 2D array upload.
Dave Airlie [Fri, 18 Feb 2011 04:51:58 +0000 (14:51 +1000)]
st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.

This is because the HW doesn't always store a 1D array like a
2D texture, it more likely stores it like 2D texture (i.e.
alignments etc).

This means we upload each slice separately and let the driver
work out where to put it.

this might break nvc0 as I can't test it, I have only nv50 here.

Signed-off-by: Dave Airlie <airlied@redhat.com>
13 years agoscons: Fix Cygwin platform names.
Vinson Lee [Thu, 24 Feb 2011 02:21:14 +0000 (18:21 -0800)]
scons: Fix Cygwin platform names.

Fixes immediate Python exceptions with SCons on Cygwin.

13 years agoi915g: Lazy emit dynamic state
Jakob Bornecrantz [Tue, 22 Feb 2011 23:12:08 +0000 (23:12 +0000)]
i915g: Lazy emit dynamic state

13 years agoi915g: Lazy emit immediate state
Jakob Bornecrantz [Mon, 21 Feb 2011 23:39:10 +0000 (23:39 +0000)]
i915g: Lazy emit immediate state

13 years agoi915g: Disable LIS7 state updates for now
Jakob Bornecrantz [Tue, 22 Feb 2011 22:07:03 +0000 (22:07 +0000)]
i915g: Disable LIS7 state updates for now

13 years agoi915g: Clean up in i915_state_immediate
Jakob Bornecrantz [Mon, 21 Feb 2011 23:09:43 +0000 (23:09 +0000)]
i915g: Clean up in i915_state_immediate

13 years agoi915g: Remove outdated comment
Jakob Bornecrantz [Mon, 21 Feb 2011 22:47:40 +0000 (22:47 +0000)]
i915g: Remove outdated comment

13 years agoi915g: Use dump function in sw winsys
Jakob Bornecrantz [Tue, 22 Feb 2011 00:20:39 +0000 (00:20 +0000)]
i915g: Use dump function in sw winsys

13 years agoi915g: Enable mirror repeat wrap mode
Jakob Bornecrantz [Wed, 23 Feb 2011 00:11:09 +0000 (00:11 +0000)]
i915g: Enable mirror repeat wrap mode

13 years agoi915g: Always set vbo to flush on flushes
Jakob Bornecrantz [Tue, 22 Feb 2011 22:28:06 +0000 (22:28 +0000)]
i915g: Always set vbo to flush on flushes

Reported-by Chris Wilson <chris@chris-wilson.co.uk>

13 years agointel: gen3 is particular sensitive to batch size
Chris Wilson [Wed, 23 Feb 2011 23:09:36 +0000 (23:09 +0000)]
intel: gen3 is particular sensitive to batch size

... and prefers a small batch whereas gen4+ prefer a large batch to
carry more state.

Tuning using openarena/padman indicate that a batch size of just 4096 is
best for those cases.

Bugzilla: https://bugs.freedesktop.org/process_bug.cgi
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agoi915: And remember assign the new value to the state reg...
Chris Wilson [Wed, 23 Feb 2011 22:09:12 +0000 (22:09 +0000)]
i915: And remember assign the new value to the state reg...

Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 years agoFix GLX_USE_TLS define.
Tom Fogal [Tue, 22 Feb 2011 05:32:18 +0000 (22:32 -0700)]
Fix GLX_USE_TLS define.

It was only getting set in the case of DRI drivers.

13 years agor600g: Request DWORD aligned vertex buffers.
Fabian Bieler [Mon, 14 Feb 2011 21:44:42 +0000 (22:44 +0100)]
r600g: Request DWORD aligned vertex buffers.

The spec says that the offsets in the vertex-fetch instructions need to be byte-aligned and makes no specification with regard to the required alignment of the offset and stride in the vertex resource constant register.

However, testing indicates that all three values need to be DWORD aligned.

13 years agost/mesa: fix computing the lowest address for interleaved attribs
Wiktor Janas [Wed, 23 Feb 2011 06:10:12 +0000 (07:10 +0100)]
st/mesa: fix computing the lowest address for interleaved attribs

Ptr can be very well NULL, so when there are two arrays, with one having
offset 0 (and thus NULL Ptr), and the other having a non-zero offset,
the non-zero value is taken as minimum (because of !low_addr ? start ...).
On 32-bit systems, this somehow works. On 64-bit systems, it leads to crashes.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
13 years agovbo: added vbo_check_buffers_are_unmapped() debug function
Brian Paul [Tue, 22 Feb 2011 21:31:15 +0000 (14:31 -0700)]
vbo: added vbo_check_buffers_are_unmapped() debug function

13 years agovbo: removed unused #defines, add comments
Brian Paul [Tue, 22 Feb 2011 21:23:50 +0000 (14:23 -0700)]
vbo: removed unused #defines, add comments

13 years agomesa: move comment, change debug code
Brian Paul [Tue, 22 Feb 2011 20:37:30 +0000 (13:37 -0700)]
mesa: move comment, change debug code

13 years agovbo: simplify NeedFlush flag clearing
Brian Paul [Tue, 22 Feb 2011 20:31:09 +0000 (13:31 -0700)]
vbo: simplify NeedFlush flag clearing

13 years agovbo: use ctx intstead of exec->ctx
Brian Paul [Tue, 22 Feb 2011 20:24:56 +0000 (13:24 -0700)]
vbo: use ctx intstead of exec->ctx

13 years agor300g: fix missing initializers warning
Brian Paul [Tue, 22 Feb 2011 19:44:42 +0000 (12:44 -0700)]
r300g: fix missing initializers warning

13 years agoi915g: remove extra semicolons
Brian Paul [Tue, 22 Feb 2011 19:44:10 +0000 (12:44 -0700)]
i915g: remove extra semicolons

13 years agoxlib: pass Display pointer to XMesaGarbageCollect()
Andy Skinner [Fri, 11 Feb 2011 15:31:25 +0000 (07:31 -0800)]
xlib: pass Display pointer to XMesaGarbageCollect()

Fixes an issue when different displays are used on different threads.

Signed-off-by: Brian Paul <brianp@vmware.com>
13 years agoi965: Increase Sandybridge point size clamp.
Kenneth Graunke [Sun, 20 Feb 2011 01:22:47 +0000 (17:22 -0800)]
i965: Increase Sandybridge point size clamp.

255.875 matches the hardware documentation.  Presumably this was a typo.

Found by inspection.  Not known to fix any issues.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoi965/fs: Correctly set up gl_FragCoord.w on Sandybridge.
Kenneth Graunke [Sun, 20 Feb 2011 00:48:24 +0000 (16:48 -0800)]
i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.

pixel_w is the final result; wpos_w is used on gen4 to compute it.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoi965/fs: Refactor control flow stack handling.
Kenneth Graunke [Sun, 20 Feb 2011 00:12:28 +0000 (16:12 -0800)]
i965/fs: Refactor control flow stack handling.

We can't safely use fixed size arrays since Gen6+ supports unlimited
nesting of control flow.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoi965/fs: Avoid register coalescing away gen6 MATH workarounds.
Kenneth Graunke [Sat, 19 Feb 2011 09:05:11 +0000 (01:05 -0800)]
i965/fs: Avoid register coalescing away gen6 MATH workarounds.

The code that generates MATH instructions attempts to work around
the hardware ignoring source modifiers (abs and negate) by emitting
moves into temporaries.  Unfortunately, this pass coalesced those
registers, restoring the original problem.  Avoid doing that.

Fixes several OpenGL ES2 conformance failures on Sandybridge.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>