intel: Remove dead code in intelAllocateBuffer

After commit "intel: Convert to using private depth/stencil buffers", we
request from DRI2GetBuffersWithFormat only the front left and back left
buffers. We no longer request depth and stencil buffers.

Assert that in intelAllocateBuffer and remove the related dead code.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

configure.ac: Remove extra ;;

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=53053

configure.ac: Don't duplicate CFLAGS

These assignments caused CFLAGS specified on the configure line to
appear twice in the final CFLAGS. Removing them makes the behavior
reasonable -- USER_CFLAGS are appended at the end of CFLAGS, allowing
the builder to override flags added by configure.ac like
-fno-strict-aliasing.

Reviewed-by: Adam Jackson <ajax@redhat.com>

configure.ac: Remove contractions to stop breaking syntax highlighting

Reviewed-by: Adam Jackson <ajax@redhat.com>

configure.ac: remove remnants of ppc asm support

Missed by d387899388bd7090bda50593e35f8ed3cb730c47.

Reviewed-by: Adam Jackson <ajax@redhat.com>

linux: Default to dri not xlib on all arches

Even on s390{,x} where there's no video card, you still want this so GLX
protocol works.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>

nv50,nvc0: make resolve sampler objects allow sRGB conversion

Just figured out what that bit does.

Note: It's converted back to sRGB on write, so no effective
conversion occurs.

Revert "gallium: specify resource_resolve destination via a pipe_surface"

This reverts commit 5d5af7d359e0060fa00b90a8f04900b96f9058b0.

It turns out the issue this was supposed to fix merely counter-acted
a bug in the hardware driver that I wasn't aware of.

The resource_resolve is not supposed to do sRGB conversion, period.
(This would violate the requirement that source and destination must
be of the same format).

r200: get rid of dubious aux scissor bits

no point in emitting aux scissor values if we
a) never enable them
b) never set the actual values

plus it is enough to have that aux scissor enable reg (which we never set to
enable) in one place not two.

radeon/r200: get rid of some unneeded cliprect/scissor code

Noone was interested in the number of cliprects, and noone cared
about the intersect result neither. So just nuke this.

r200: get rid of old gart memory functions from old dri1

Those functions are SO dead.

radeon/r200: fix bogus clears

There were several problems with these functions (which are a remnant
of dri1 hyperz mostly - should bring it back somehow someday).
First, it would always do a swrast clear if the buffer to clear was a fbo.
Second, for buffers we wouldn't handle the clear (I guess aux/accum?) we
would actually still have tried to clear that later even when we already
cleared it with swrast.

radeon/r200: fix bogus assert/scissor wrt width/height 2048

This addresses one issue raised in bug #51658 discovered by Eugene St Leger.
The assert is bogus since there's no problem with texture width/height being
2048 (the width/height programmed is width/height minus one).
OTOH though the programmed size for scissor rect should be width/height
minus one too otherwise bad things may happen (as it is inclusive, and there's
not enough bits for more than a value of 2047).

radeon/llvm: fix calculation of max register number

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeon/llvm: Add pseudo-support for 64-bit immediate types on SI

SI does not support 64-bit immediates natively, but llvm will generate
i64 immediates when indexing loads and stores (since SI has 64-bit
pointers).  The i64 indices will always be small enough to fit into
32-bits (i.e. the high 32 bits will always be all zeros), so we can
treat these index values as 32-bits.

radeon/llvm: Fix incorrect return value in SelectADDRReg()

We need to return true when we match the pattern.

radeon/llvm: Move SMRD IMM pattern before SMRD SGPR pattern

In tablegen, if two patterns match, the one that comes first in the file
is given preference.  We want the SMRD IMM pattern to be given
preference, because it encodes the pointer offset in its immediate
field, which saves us an add instruction.

glsl: Reject linking shaders with too many uniform blocks.

Part of fixing piglit maxblocks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Return -1 for glGetUniformLocation on UBOs.

Fixes piglit ARB_uniform_buffer_object/getuniformlocation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Assign array and matrix stride values according to std140 layout.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add support for default layout qualifiers for uniforms.

I ended up having to add rallocing of the ast_type_qualifier in order
to avoid pulling in ast.h for glsl_parser_extras.h, because I wanted
to track an ast_type_qualifier in the state.

Fixes piglit ARB_uniform_buffer_object/row-major.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Merge UBO layout qualifiers in a qualifier list.

Yes, you get to say things like "layout(row_major, column_major)" and
get column major.

Part of fixing piglit ARB_uniform_buffer_object/row_major.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add support for GL_ARB_ubo's glGetActiveUniformName().

This is like a stripped-down version of glGetActiveUniform that just
returns the name, since the other return values (type and size) of
that function are now meant to be handled with
glGetActiveUniformsiv().

Fixes piglit ARB_uniform_buffer_object/getactiveuniformname

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add support for most of the other pnames of glGetActiveUniformBlockiv().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add support for getting active uniform block names.

Fixes piglit ARB_uniform_buffer_object/getactiveuniformblockname.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add support for glUniformBlockBinding() and the API to get it back.

Fixes piglit ARB_uniform_buffer_object/uniformbufferbinding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Incorporate all UBO language changes into GLSL 1.40.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add support for glGetProgramiv pnames for UBOs.

Fixes piglit ARB_uniform_buffer_object/getprogramiv.

v2: Add extension checks.
v3: Appease MSVC.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Refactor #version validation to be more future-proof.

The previous implementation required a flag in _mesa_glsl_parse_state
and line of code to initialize it for every version of the shading
language we intend to support.  As we look to add 150, 330, 400, 410,
420, and beyond, this gets rather unwieldy.

This patch retains the switch statement (to reject, say, #version 111),
but removes all the bits.  Code to check for ctx->API == API_OPENGL_CORE
could easily be added to the 110 and 120 cases to reject those.

v2: Use _mesa_is_desktop_gl to preserve the existing behavior in the
    presence of the new API_OPENGL_CORE enumeration.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]

i965: Add support for GL_SKIP_DECODE_EXT on other SRGB formats.

Fixes some failures in getteximage-formats.

v2: Remove stray include, and drop extra test for encoding == GL_SRGB --
    _mesa_get_srgb_format_linear() returns the same format if it wasn't SRGB.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48120
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
NOTE: This is a candidate for the 8.0 branch.

glsl: Fix #pragma invariant(all) language version check.

It was using state->Const.GLSL_100ES, which is set if the driver
supports ARB_ES2_compatibility or we're in ES2 mode.  Instead, it should
use state->language_version, as that represents the actual GLSL version
of the shader being compiled.

Since the correct logic is < 120 && !100, just make it == 110.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Support glGetString(GL_SHADING_LANGUAGE_VERSION) for >= 1.40.

This will need to get refactored when we add support for core profiles
or forward-compatible contexts, but we may as well have it in the
meantime.  This allows us to override the GLSL version and experiment.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

ir_to_mesa: make size_swizzles[] array static const

Move installing osmesa.pc to drivers/osmesa

Move installing osmesa.pc to drivers/osmesa, where it belongs better

This also restores the installation of gl.pc if we are building osmesa at the
same time as libGL, which was broken in commit 39785488 when the .pc
installation was converted to automake

v2:
Remove HAVE_OSMESA_DRIVER automake conditional, it's now pointless as we
will only be building in the drivers/osmesa directory if the condition it
checked was true.

Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/util: Use GCC built-in functions for NaN and infinity.

This patch fixes this build failure with Intel Compiler.

src/gallium/auxiliary/util/u_format_tests.c(903): error: floating-point operation result is out of range
     {PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0xffff), PACKED_1x16(0x7c01), UNPACKED_1x1(        NAN, 0.0, 0.0, 1.0)},

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>

mesa: don't enable legacy GL functions when using API_OPENGL_CORE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

intel: add support for using API_OPENGL_CORE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

meta: add support for using API_OPENGL_CORE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: add support for using API_OPENGL_CORE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add support for using API_OPENGL_CORE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add api check functions

These functions make it easier to check for multiple API types.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add API_OPENGL_CORE api

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Fix ir_last_opcode value.

Now that ir_quadop_vector exists, ir_last_binop and ir_last_opcode are
no longer the same.  Only one place currently uses this enumeration, and
already handles ir_quadop_vector correctly.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Olivier Galibert <galibert@pobox.com>

glsl: Request an Nx1 type instance in ir_quadop_vector lowering pass.

No types have 0 columns.  The glsl_type::get_instance method contains

   if ((rows < 1) || (rows > 4) || (columns < 1) || (columns > 4))
      return error_type;

To get a vector, use columns = 1.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Olivier Galibert <galibert@pobox.com>

glsl: Make bvec and ivec types accessible without using get_instance.

It's more convenient to use shortcuts like glsl_type::bvec2_type than
the longwinded glsl_type::get_instance(GLSL_TYPE_BOOL, 2, 1).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Olivier Galibert <galibert@pobox.com>

radeon/llvm: Cleanup AMDIL.h

radeon/llvm: Rename all AMDIL* classes to AMDGPU*

radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget

radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering

radeon/llvm: Remove IL_cmp DAG node

radeon/llvm: Cleanup and reorganize AMDIL .td files

radeon/llvm: Remove lowering code for unsupported features

e.g. function calls, load/store from stack

radeon/llvm: Remove AMDILVersion.td

radeon/llvm: Remove AMDILAlgorithms.tpp

radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cpp

radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo

radeon/llvm: Change the tablegen target from AMDIL to AMDGPU

i965: Support MESA_FORMAT_SIGNED_RGBA_16.

The hardware supports this format with no known quirks, so we may as
well enable it.

Alpha blending is not supported until Sandybridge, but as far as I can
tell, OpenGL doesn't require alpha blending on SNORM formats.  Plus, we
already expose R8G8B8A8_SNORM which has a similar restriction.

Fixes 6 piglit texwrap-2D-*SNORM* cases,
gl-3.1/required-sized-texture-formats, and 10 oglconform snorm-textures
subcases

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

gbm: Fix build for wayland include

backends/gbm_dri.c fails to find wayland-server.h.

Signed-off-by: Elvis Lee <kwangwoong.lee@lge.com>

mesa: fix _math_matrix_copy(), again

The matrix is 16 GLfloats in size.  Since from->inv is just a pointer (not
an array), sizeof(*from->inv) wasn't right.

mesa: Fix wrong sizeof argument in _math_matrix_copy.

Fixes Coverity wrong sizeof argument defect.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Signed-off-by: Brian Paul <brianp@vmware.com>

radeonsi: fix db and stencil setup v2

v2: fix tiling for small pitches, that finally makes
    glxgears and readPixSanity work

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix stencil op mapping

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix assertion in si_bind_vs_sampler

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix shader binding

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix dummy export in shaders v2

v2: add assertion for vertex shader

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix vertex buffer and elements

Let's just use the T# descriptors until we get a fetch shader.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix shader size and handling

We should always upload the shader here.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: rename r600_resource to si_resource

Also split it into seperate header and add
some helper functions.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

glcpp: Add a newline to expanded #line directives.

Otherwise, the preprocessor happily outputs

    #line 2 4 <your next line of code>

and the main compiler gets horribly confused and fails to compile.

This is not the right solution (line numbers in error messages will
likely be off-by-one in certain circumstances), but until Carl comes
up with a proper fix, this gets programs running again.

Fixes regressions in Regnum Online, Overgrowth, Piglit, and others since
commit aac78ce8234d96932c38b3f48b1d828077bc0027.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51802
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51506
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41152
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: specify resource_resolve destination via a pipe_surface

The format member of pipe_surface may differ from that of the
pipe_resource, which is used to communicate, for instance, whether
sRGB encode should be enabled in the resolve operation or not.

Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB
is disabled.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: call update_renderbuffer_surface for sRGB renderbuffers, too

sRGBEnabled should affect both textures and renderbuffers, so we need
to check/update the pipe_surface format for both.

Fixes, for instance, rendering appearing too bright in wine applications
using sRGB multisample renderbuffers.

NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>

nv50: fix depth/stencil multisample memory storage types

Leftover from libdrm_nouveau v2 interface change.

nv50: fix resource_resolve shader start offsets

st/mesa: undo a couple static asserts

Hmm, gcc didn't catch these mistakes, but MSVC did.

st/mesa: use STATIC_ASSERT in a few places

mesa: whitespace, etc. fixes in program.h

meta: fix glDrawPixels fallback test, stencil drawing

Remove the check for pixel transfer ops.  If any RGB/depth scale/bias
is in effect, it'll be applied in the glTexImage step.

If drawing stencil pixels we need to disable pixel transfer so that
alpha scale/bias are not applied to the stencil data.

These issues were spotted by Roland.

Fixes Blender performance issues reported in
http://bugs.freedesktop.org/show_bug.cgi?id=47375

NOTE: This is a candidate for the 8.0 branch.

Tested-by: Barto <mister.freeman@laposte.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

radeon: fix 'sowftware' typo

i965/gen7: Reduce GT1 WM thread count according to updated BSpec.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=52382

i965: Fix typo in shader channel select field name.

"chanel" isn't very searchable.  I can type, honest!

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.

No functional change.  This patch modifies intel_miptree_alloc_mcs to
allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of
MESA_FORMAT_A8.  In principle it doesn't matter, since we only access
the buffer using MCS-specific hardware mechanisms, so all that's
important is to use a format with the correct size.  However,
MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to
avoid it.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

intel: increase wm thread number to 80 on gen6 GT2

It seems reset is not required for setting the max_wm_threads to 80
on gen6 GT2.

Increases performance in the Counter-Strike: Source video stress test
by 7.18% (n=5).

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Matt Turner <mattst88@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>

r600g: Emit dispatch state for compute directly to the cs

We no longer rely on an evergreen_compute_resource for emitting dispatch
state.

Reviewed-by: Marek Olšák <maraeo@gmail.com>

r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atom

The value of this register will always be DI_PT_POINTLIST for compute
shaders.

Reviewed-by: Marek Olšák <maraeo@gmail.com>

r600g: Atomize compute shader state

Reviewed-by: Marek Olšák <maraeo@gmail.com>

r600g: Add helper functions for emitting compute SET_CONTEXT packets

Reviewed-by: Marek Olšák <maraeo@gmail.com>

radeon/llvm: Add instruction defs for branches on SI

radeon/llvm: Fix VOPC and V_CNDMASK encoding

radeon/llvm: Assert if we try to copy SCC reg

radeon/llvm: Add SI DAG optimizations for setcc, select_cc

These are needed for correctly lowering branch instructions in some
cases.

radeon/llvm: Add support for encoding SI branch instructions

radeon/llvm: Add special nodes for SALU operations on VCC

The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit.  In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.

radeon/llvm: Add i1 registers for SI.

radeon/llvm: Fix CCReg definitions on SI

radeonsi: Enable PIPE_SHADER_CAP_INTEGERS

radeonsi: Add support for loading integers from constant memory

radeon/llvm: Add bitconvert patterns for SI

radeon/llvm: Add custom lowering for SELECT_CC nodes on SI

radeon/llvm: Move conditional pattern leafs to common tablegen file