Eddie Hung [Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)]
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Miodrag Milanović [Sun, 29 Sep 2019 08:37:34 +0000 (10:37 +0200)]
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
Support binary files for backends, fixes #1407
Clifford Wolf [Sun, 29 Sep 2019 08:36:25 +0000 (10:36 +0200)]
Merge pull request #1411 from aman-goel/YosysHQ-master
Corrects BTOR2 backend
Miodrag Milanovic [Sat, 28 Sep 2019 07:50:29 +0000 (09:50 +0200)]
Add aiger and protobuf backends binary support
Miodrag Milanovic [Sat, 28 Sep 2019 07:28:51 +0000 (09:28 +0200)]
Support binary files for backends, fixes #1407
Eddie Hung [Sat, 28 Sep 2019 01:49:45 +0000 (18:49 -0700)]
Fix box name
Eddie Hung [Fri, 27 Sep 2019 21:32:07 +0000 (14:32 -0700)]
Re-order
Eddie Hung [Fri, 27 Sep 2019 21:21:47 +0000 (14:21 -0700)]
Missing (* mul2dsp *) for sliceB
Eddie Hung [Fri, 27 Sep 2019 18:57:53 +0000 (11:57 -0700)]
Ooops AREG and BREG to default to -1
Aman Goel [Fri, 27 Sep 2019 16:40:17 +0000 (12:40 -0400)]
Corrects btor2 backend
Marcin Kościelnicki [Fri, 27 Sep 2019 09:03:04 +0000 (11:03 +0200)]
Fix _TECHMAP_REMOVEINIT_ handling.
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396.
Aman Goel [Fri, 27 Sep 2019 16:30:27 +0000 (12:30 -0400)]
Merge pull request #7 from YosysHQ/master
Syncing with official repo
Miodrag Milanović [Fri, 27 Sep 2019 15:37:55 +0000 (17:37 +0200)]
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt_difference
Change order of parameters, to work on other OS
Miodrag Milanovic [Fri, 27 Sep 2019 09:31:55 +0000 (11:31 +0200)]
Change order of parameters, to work on other os
Clifford Wolf [Fri, 27 Sep 2019 07:57:28 +0000 (09:57 +0200)]
Merge pull request #1404 from YosysHQ/fix_gzip_macos
Make read/write gzip files on macos works, fixes #1357
Eddie Hung [Thu, 26 Sep 2019 21:31:02 +0000 (14:31 -0700)]
Update doc with max cascade chain of 20
Eddie Hung [Thu, 26 Sep 2019 20:59:05 +0000 (13:59 -0700)]
Do not always zero out C (e.g. during cascade breaks)
Eddie Hung [Thu, 26 Sep 2019 20:44:41 +0000 (13:44 -0700)]
Update doc
Eddie Hung [Thu, 26 Sep 2019 20:40:38 +0000 (13:40 -0700)]
Zero out ports
Eddie Hung [Thu, 26 Sep 2019 20:29:18 +0000 (13:29 -0700)]
xilinx_dsp_cascade to also cascade AREG and BREG
Eddie Hung [Thu, 26 Sep 2019 19:09:57 +0000 (12:09 -0700)]
Try recursive pmgen for P cascade
Eddie Hung [Thu, 26 Sep 2019 18:13:08 +0000 (11:13 -0700)]
Missing an '&'
Eddie Hung [Thu, 26 Sep 2019 17:45:14 +0000 (10:45 -0700)]
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
Miodrag Milanovic [Thu, 26 Sep 2019 17:35:12 +0000 (19:35 +0200)]
Make read/write gzip files on macos works, fixes #1357
Eddie Hung [Thu, 26 Sep 2019 17:34:14 +0000 (10:34 -0700)]
Typo
Eddie Hung [Thu, 26 Sep 2019 17:32:01 +0000 (10:32 -0700)]
CREG to check for \keep
Eddie Hung [Thu, 26 Sep 2019 17:31:55 +0000 (10:31 -0700)]
Remove newline
Eddie Hung [Thu, 26 Sep 2019 17:15:05 +0000 (10:15 -0700)]
select once
Eddie Hung [Thu, 26 Sep 2019 16:57:11 +0000 (09:57 -0700)]
Stop trying to be too smart by prematurely optimising
Eddie Hung [Thu, 26 Sep 2019 05:58:55 +0000 (22:58 -0700)]
mul2dsp.v slice names
Eddie Hung [Thu, 26 Sep 2019 05:58:03 +0000 (22:58 -0700)]
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
Eddie Hung [Thu, 26 Sep 2019 01:21:08 +0000 (18:21 -0700)]
Reject if (* init *) present
Eddie Hung [Thu, 26 Sep 2019 00:26:47 +0000 (17:26 -0700)]
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung [Thu, 26 Sep 2019 00:25:44 +0000 (17:25 -0700)]
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
This reverts commit
234738b103d4f2b3d937ed928fd89bc4e31627f1.
Eddie Hung [Thu, 26 Sep 2019 00:24:11 +0000 (17:24 -0700)]
Revert "No need for $__mul anymore?"
This reverts commit
1d875ac76a354f654f28b9632d83f6b43542e827.
Eddie Hung [Thu, 26 Sep 2019 00:22:30 +0000 (17:22 -0700)]
Rework xilinx_dsp postAdd for new wreduce call
Eddie Hung [Thu, 26 Sep 2019 00:22:04 +0000 (17:22 -0700)]
Only wreduce on t:$add
Eddie Hung [Wed, 25 Sep 2019 23:51:31 +0000 (16:51 -0700)]
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung [Wed, 25 Sep 2019 23:45:51 +0000 (16:45 -0700)]
Fix memory issue since SigSpec& could be invalidated
Eddie Hung [Wed, 25 Sep 2019 23:43:24 +0000 (16:43 -0700)]
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
ICE40 tests. adffs test update (equiv_opt -multiclock).
Eddie Hung [Wed, 25 Sep 2019 21:06:21 +0000 (14:06 -0700)]
No need for $__mul anymore?
Eddie Hung [Wed, 25 Sep 2019 21:05:59 +0000 (14:05 -0700)]
unextend only used in init
Eddie Hung [Wed, 25 Sep 2019 21:04:36 +0000 (14:04 -0700)]
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung [Wed, 25 Sep 2019 17:33:16 +0000 (10:33 -0700)]
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
SergeyDegtyar [Wed, 25 Sep 2019 11:43:26 +0000 (14:43 +0300)]
Change sync controls to async.
Clifford Wolf [Wed, 25 Sep 2019 07:20:54 +0000 (09:20 +0200)]
Merge pull request #1402 from YosysHQ/clifford/portlist
Add "portlist" command
Clifford Wolf [Wed, 25 Sep 2019 07:20:38 +0000 (09:20 +0200)]
Improve "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 24 Sep 2019 16:08:59 +0000 (18:08 +0200)]
Add "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
SergeyDegtyar [Tue, 24 Sep 2019 11:55:32 +0000 (14:55 +0300)]
adffs test update (equiv_opt -multiclock).
Eddie Hung [Tue, 24 Sep 2019 05:02:22 +0000 (22:02 -0700)]
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung [Tue, 24 Sep 2019 04:58:40 +0000 (21:58 -0700)]
"abc_padding" attr for blackbox outputs that were padded, remove them later
Eddie Hung [Tue, 24 Sep 2019 04:58:04 +0000 (21:58 -0700)]
Force $inout.out ports to begin with '$' to indicate internal
Eddie Hung [Tue, 24 Sep 2019 04:56:28 +0000 (21:56 -0700)]
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Add a xilinx_finalise pass"
This reverts commit
23d90e0439ffef510632ce45a3d2aff1c129f405.
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
This reverts commit
67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
Eddie Hung [Tue, 24 Sep 2019 02:52:54 +0000 (19:52 -0700)]
Revert "Vivado does not like zero width port connections"
This reverts commit
895e2befa76bd326cc47fd40de112ea067fcaf98.
Eddie Hung [Tue, 24 Sep 2019 02:04:07 +0000 (19:04 -0700)]
Vivado does not like zero width port connections
Eddie Hung [Tue, 24 Sep 2019 01:56:18 +0000 (18:56 -0700)]
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung [Tue, 24 Sep 2019 01:56:02 +0000 (18:56 -0700)]
Add a xilinx_finalise pass
Eddie Hung [Mon, 23 Sep 2019 23:00:11 +0000 (16:00 -0700)]
Set [AB]CASCREG to legal values
Eddie Hung [Mon, 23 Sep 2019 20:58:10 +0000 (13:58 -0700)]
Comment to explain separating CREG packing
Eddie Hung [Mon, 23 Sep 2019 20:27:10 +0000 (13:27 -0700)]
Separate out CREG packing into new pattern, to avoid conflict with PREG
Eddie Hung [Mon, 23 Sep 2019 20:27:00 +0000 (13:27 -0700)]
Move log_debug("\n") later
Eddie Hung [Mon, 23 Sep 2019 20:26:34 +0000 (13:26 -0700)]
Move unextend initialisation later
Eddie Hung [Mon, 23 Sep 2019 20:00:44 +0000 (13:00 -0700)]
Use new port() overload once more
Miodrag Milanović [Mon, 23 Sep 2019 18:06:40 +0000 (20:06 +0200)]
Merge pull request #1399 from nakengelhardt/fix-show-macos
fix show command for macos
Eddie Hung [Mon, 23 Sep 2019 17:58:28 +0000 (10:58 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
N. Engelhardt [Mon, 23 Sep 2019 16:25:04 +0000 (18:25 +0200)]
add xdot dependency to Brewfile
N. Engelhardt [Mon, 23 Sep 2019 15:25:30 +0000 (17:25 +0200)]
fix show command for macos
Clifford Wolf [Sat, 21 Sep 2019 09:25:36 +0000 (11:25 +0200)]
Merge pull request #1392 from YosysHQ/eddie/fix1391
(* techmap_autopurge *) fixes when ports aren't consistently-sized
Eddie Hung [Sat, 21 Sep 2019 00:58:51 +0000 (17:58 -0700)]
Hell let's add the original #1381 testcase too
Eddie Hung [Sat, 21 Sep 2019 00:52:23 +0000 (17:52 -0700)]
Revert abc9.cc
Eddie Hung [Sat, 21 Sep 2019 00:49:26 +0000 (17:49 -0700)]
Add testcase
Eddie Hung [Sat, 21 Sep 2019 00:48:37 +0000 (17:48 -0700)]
Trim mismatched connection to be same (smallest) size
Eddie Hung [Sat, 21 Sep 2019 00:42:36 +0000 (17:42 -0700)]
Fix first testcase in #1391
Eddie Hung [Fri, 20 Sep 2019 21:24:31 +0000 (14:24 -0700)]
Grammar
Eddie Hung [Fri, 20 Sep 2019 21:21:22 +0000 (14:21 -0700)]
Use new port/param overload in pmg
Eddie Hung [Fri, 20 Sep 2019 19:42:28 +0000 (12:42 -0700)]
Output pattern matcher items as log_debug()
Eddie Hung [Fri, 20 Sep 2019 19:37:29 +0000 (12:37 -0700)]
OPMODE is port not param
Eddie Hung [Fri, 20 Sep 2019 19:21:36 +0000 (12:21 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Fri, 20 Sep 2019 19:18:37 +0000 (12:18 -0700)]
Do not run xilinx_dsp_cascadeAB for now
Eddie Hung [Fri, 20 Sep 2019 19:07:14 +0000 (12:07 -0700)]
WIP for xiinx_dsp_cascadeAB
Eddie Hung [Fri, 20 Sep 2019 19:04:16 +0000 (12:04 -0700)]
Run until convergence
Eddie Hung [Fri, 20 Sep 2019 19:03:45 +0000 (12:03 -0700)]
Cleanup ice40_dsp.pmg
Eddie Hung [Fri, 20 Sep 2019 19:03:25 +0000 (12:03 -0700)]
Cleanup xilinx_dsp
Eddie Hung [Fri, 20 Sep 2019 19:03:10 +0000 (12:03 -0700)]
More exceptions
Eddie Hung [Fri, 20 Sep 2019 17:11:36 +0000 (10:11 -0700)]
Fix signedness bug
Eddie Hung [Fri, 20 Sep 2019 17:07:54 +0000 (10:07 -0700)]
Update doc
Eddie Hung [Fri, 20 Sep 2019 17:00:09 +0000 (10:00 -0700)]
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
Eddie Hung [Fri, 20 Sep 2019 16:59:42 +0000 (09:59 -0700)]
Add an overload for port/param with default value
Eddie Hung [Fri, 20 Sep 2019 16:02:29 +0000 (09:02 -0700)]
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung [Fri, 20 Sep 2019 15:56:16 +0000 (08:56 -0700)]
Revert "Move mul2dsp before wreduce"
This reverts commit
e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
Eddie Hung [Fri, 20 Sep 2019 15:41:40 +0000 (08:41 -0700)]
Move mul2dsp before wreduce
Eddie Hung [Fri, 20 Sep 2019 15:41:28 +0000 (08:41 -0700)]
Small cleanup
Clifford Wolf [Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)]
Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
Clifford Wolf [Fri, 20 Sep 2019 10:16:20 +0000 (12:16 +0200)]
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:28:20 +0000 (10:28 +0200)]
Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:27:17 +0000 (10:27 +0200)]
Add "add -mod"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 07:58:42 +0000 (09:58 +0200)]
Merge pull request #1384 from YosysHQ/clifford/fix1381
Add techmap_autopurge attribute
Eddie Hung [Fri, 20 Sep 2019 05:48:57 +0000 (22:48 -0700)]
Disable support for SB_MAC16 reset since it is async