Yasuko Eckert [Tue, 3 Jun 2014 20:32:29 +0000 (13:32 -0700)]
ext: Redirect McPAT object files
All object files and McPAT binaries are moved to directory gem5/build/mcpat/
rather than creating them locally.
Steve Reinhardt [Sun, 1 Jun 2014 01:00:23 +0000 (18:00 -0700)]
style: eliminate equality tests with true and false
Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.
It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.
Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.
Nilay Vaish [Sun, 25 May 2014 02:30:46 +0000 (21:30 -0500)]
stats: changes due to recent o3 patch.
Nilay Vaish [Fri, 23 May 2014 11:07:02 +0000 (06:07 -0500)]
stats: changes due to o3 cpu and ruby message buffer patches
Nilay Vaish [Fri, 23 May 2014 11:07:02 +0000 (06:07 -0500)]
ruby: slicc: remove unused ids DNUCA*
Nilay Vaish [Fri, 23 May 2014 11:07:02 +0000 (06:07 -0500)]
ruby: remove old protocol documentation
Nilay Vaish [Fri, 23 May 2014 11:07:02 +0000 (06:07 -0500)]
ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.
Nilay Vaish [Fri, 23 May 2014 11:07:02 +0000 (06:07 -0500)]
cpu: o3: remove stat totalCommittedInsts
This patch removes the stat totalCommittedInsts. This variable was used for
recording the total number of instructions committed across all the threads
of a core. The instructions committed by each thread are recorded invidually.
The total would now be generated by summing these individual counts.
Anthony Gutierrez [Thu, 15 May 2014 17:26:31 +0000 (13:26 -0400)]
config: remove unecessary assignment of etherlink interfaces
in makeDualRoot() the etherlink interfaces are set using the tsunami interface
however, they are set again a few lines later based on whether or not the system
is a realview or tsunami system; the original assignment is always overwritten
or there will be a fatal. this seems like an artifact from when tsunami was the
only type of system capable of running with the dual option.
Steve Reinhardt [Mon, 12 May 2014 21:23:31 +0000 (14:23 -0700)]
syscall emulation: clean up & comment SyscallReturn
Steve Reinhardt [Mon, 12 May 2014 21:22:17 +0000 (17:22 -0400)]
tests: update t1000 & pc-switcheroo-full stats
committed reference config.json files too
Steve Reinhardt [Sun, 11 May 2014 02:13:51 +0000 (22:13 -0400)]
tests: update eio ref outputs for new stats
Also committed reference config.json files for
the eio tests.
Andreas Hansson [Fri, 9 May 2014 22:58:50 +0000 (18:58 -0400)]
stats: Bump stats for the fixes, and mostly DRAM controller changes
Andreas Hansson [Fri, 9 May 2014 22:58:49 +0000 (18:58 -0400)]
config: Bump DRAM sweep bus speed to match DDR4 config
This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.
Andreas Hansson [Fri, 9 May 2014 22:58:49 +0000 (18:58 -0400)]
tests: Reflect name change in DRAM tests
This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.
--HG--
rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
Andreas Hansson [Fri, 9 May 2014 22:58:49 +0000 (18:58 -0400)]
mem: Update DDR3 and DDR4 based on datasheets
This patch makes a more firm connection between the DDR3-1600
configuration and the corresponding datasheet, and also adds a
DDR3-2133 and a DDR4-2400 configuration. At the moment there is also
an ongoing effort to align the choice of datasheets to what is
available in DRAMPower.
Andreas Hansson [Fri, 9 May 2014 22:58:49 +0000 (18:58 -0400)]
mem: Add DRAM cycle time
This patch extends the current timing parameters with the DRAM cycle
time. This is needed as the DRAMPower tool expects timestamps in DRAM
cycles. At the moment we could get away with doing this in a
post-processing step as the DRAMPower execution is separate from the
simulation run. However, in the long run we want the tool to be called
during the simulation, and then the cycle time is needed.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Simplify DRAM response scheduling
This patch simplifies the DRAM response scheduling based on the
assumption that they are always returned in order.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Add precharge all (PREA) to the DRAM controller
This patch adds the basic ingredients for a precharge all operation,
to be used in conjunction with DRAM power modelling.
Currently we do not try and apply any cleverness when precharging all
banks, thus even if only a single bank is open we use PREA as opposed
to PRE. At the moment we only have a single tRP (tRPpb), and do not
model the slightly longer all-bank precharge constraint (tRPab).
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Remove printing of DRAM params
This patch removes the redundant printing of DRAM params.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Add tRTP to the DRAM controller
This patch adds the tRTP timing constraint, governing the minimum time
between a read command and a precharge. Default values are provided
for the existing DRAM types.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Merge DRAM latency calculation and bank state update
This patch merges the two control paths used to estimate the latency
and update the bank state. As a result of this merging the computation
is now in one place only, and should be easier to follow as it is all
done in absolute (rather than relative) time.
As part of this change, the scheduling is also refined to ensure that
we look at a sensible estimate of the bank ready time in choosing the
next request. The bank latency stat is removed as it ends up being
misleading when the DRAM access code gets evaluated ahead of time (due
to the eagerness of waking the model up for scheduling the next
request).
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Add tWR to DRAM activate and precharge constraints
This patch adds the write recovery time to the DRAM timing
constraints, and changes the current tRASDoneAt to a more generic
preAllowedAt, capturing when a precharge is allowed to take place.
The part of the DRAM access code that accounts for the precharge and
activate constraints is updated accordingly.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Merge DRAM page-management calculations
This patch treats the closed page policy as yet another case of
auto-precharging, and thus merges the code with that used for the
other policies.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Add DRAM power states to the controller
This patch adds power states to the controller. These states and the
transitions can be used together with the Micron power model. As a
more elaborate use-case, the transitions can be used to drive the
DRAMPower tool.
At the moment, the power-down modes are not used, and this patch
simply serves to capture the idle, auto refresh and active modes. The
patch adds a third state machine that interacts with the refresh state
machine.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Ensure DRAM refresh respects timings
This patch adds a state machine for the refresh scheduling to
ensure that no accesses are allowed while the refresh is in progress,
and that all banks are propely precharged.
As part of this change, the precharging of banks of broken out into a
method of its own, making is similar to how activations are dealt
with. The idle accounting is also updated to ensure that the refresh
duration is not added to the time that the DRAM is in the idle state
with all banks precharged.
Andreas Hansson [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
mem: Make DRAM read/write switching less conservative
This patch changes the read/write event loop to use a single event
(nextReqEvent), along with a state variable, thus joining the two
control flows. This change makes it easier to follow the state
transitions, and control what happens when.
With the new loop we modify the overly conservative switching times
such that the write-to-read switch allows bank preparation to happen
in parallel with the bus turn around. Similarly, the read-to-write
switch uses the introduced tRTW constraint.
Ali Saidi [Thu, 17 Apr 2014 21:56:09 +0000 (16:56 -0500)]
arm: Make sure UndefinedInstructions are properly initialized
Ali Saidi [Thu, 17 Apr 2014 21:55:54 +0000 (16:55 -0500)]
arm: allow DC instructions by default so SE mode works
Ali Saidi [Thu, 17 Apr 2014 21:55:05 +0000 (16:55 -0500)]
sim, arm: implement more of the at variety syscalls
Needed for new AArch64 binaries
Andrew Bardsley [Fri, 9 May 2014 22:58:48 +0000 (18:58 -0400)]
cpu: Useful getters for ActivityRecorder
Add some useful getters to ActivityRecorder
Andrew Bardsley [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
cpu: Add flag name printing to StaticInst
This patch adds a the member function StaticInst::printFlags to allow all
of an instruction's flags to be printed without using the individual
is... member functions or resorting to exposing the 'flags' vector
It also replaces the enum definition StaticInst::Flags with a
Python-generated enumeration and adds to the enum generation mechanism
in src/python/m5/params.py to allow Enums to be placed in namespaces
other than Enums or, alternatively, in wrapper structs allowing them to
be inherited by other classes (so populating that class's name-space
with the enumeration element names).
Andrew Bardsley [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
cpu: Timebuf const accessors
Add const accessors for timebuf elements.
Andrew Bardsley [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
arm: Add branch flags onto macroops
Mark branch flags onto macroops to allow branch prediction before
microop decomposition
Andrew Bardsley [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
cpu: Allow setWhen on trace objects
Allow setting of 'when' in trace records. This allows later times
than the arbitrary record creation point to be used as inst. times
Curtis Dunham [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
arm: add preliminary ISA splits for ARM arch
Curtis Dunham [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
Geoffrey Blake [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
config: Avoid generating a reference to myself for Parent.any
The unproxy code for Parent.any can generate a circular reference
in certain situations with classes hierarchies like those in ClockDomain.py.
This patch solves this by marking ouself as visited to make sure the
search does not resolve to a self-reference.
Geoffrey Blake [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
arch, arm: Preserve TLB bootUncacheability when switching CPUs
The ARM TLBs have a bootUncacheability flag used to make some loads
and stores become uncacheable when booting in FS mode. Later the
flag is cleared to let those loads and stores operate as normal. When
doing a takeOverFrom(), this flag's state is not preserved and is
momentarily reset until the CPSR is touched. On single core runs this
is a non-issue. On multi-core runs this can lead to crashes on the O3
CPU model from the following series of events:
1) takeOverFrom executed to switch from Atomic -> O3
2) All bootUncacheability flags are reset to true
3) Core2 tries to execute a load covered by bootUncacheability, it
is flagged as uncacheable
4) Core2's load needs to replay due to a pipeline flush
3) Core1 core does an action on CPSR
4) The handling code for CPSR then checks all other cores
to determine if bootUncacheability can be set to false
5) Asynchronously set bootUncacheability on all cores to false
6) Core2 replays load previously set as uncacheable and notices
it is now flagged as cacheable, leads to a panic.
This patch implements takeOverFrom() functionality for the ARM TLBs
to preserve flag values when switching from atomic -> detailed.
Curtis Dunham [Fri, 9 May 2014 22:58:47 +0000 (18:58 -0400)]
cpu: add more instruction mix statistics
For the o3, add instruction mix (OpClass) histogram at commit (stats
also already collected at issue). For the simple CPUs we add a
histogram of executed instructions
Mitch Hayenga [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
mem: Squash prefetch requests from downstream caches
This patch squashes prefetch requests from downstream caches,
so that they do not steal cachelines away from caches closer
to the cpu. It was originally coded by Mitch Hayenga and
modified by Aasheesh Kolli.
Stephan Diestelhorst [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
stats: Method stats source
This source for stats binds an object and a method / function from the object
to a stats object. This allows pulling out stats from object methods without
needing to go through a global, or static shim.
Syntax is somewhat unpleasant, but the templates and method pointer type
specification were quite tricky. Interface is very clean though; and similar
to .functor
Akash Bagdia [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
cpu, arm: Allow the specification of a socket field
Allow the specification of a socket ID for every core that is reflected in the
MPIDR field in ARM systems. This allows studying multi-socket / cluster
systems with ARM CPUs.
Sascha Bischoff [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
mem: Auto-generate CommMonitor trace file names
Splits the CommMonitor trace_file parameter into three parameters. Previously,
the trace was only enabled if the trace_file parameter was set, and would be
written to this file. This patch adds in a trace_enable and trace_compress
parameter to the CommMonitor.
No trace is generated if trace_enable is set to False. If it is set to True, the
trace is written to a file based on the name of the SimObject in the simulation
hierarchy. For example, system.cluster.il1_commmonitor.trc. This filename can be
overridden by additionally specifying a file name to the trace_file parameter
(more on this later).
The trace_compress parameter will append .gz to any filename if set to True.
This enables compression of the generated traces. If the file name already ends
in .gz, then no changes are made.
The trace_file parameter will override the name set by the trace_enable
parameter. In the case that the specified name does not end in .gz but
trace_compress is set to true, .gz is appended to the supplied file name.
Geoffrey Blake [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
arm: Panics in miscreg read functions can be tripped by O3 model
Unimplemented miscregs for the generic timer were guarded by panics
in arm/isa.cc which can be tripped by the O3 model if it speculatively
executes a wrong path containing a mrs instruction with a bad miscreg
index. These registers were flagged as implemented and accessible.
This patch changes the miscreg info bit vector to flag them as
unimplemented and inaccessible. In this case, and UndefinedInst
fault will be generated if the register access is not trapped
by a hypervisor.
Chris Emmons [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
dev: Set HDLCD default pixel clock for 1080p @ 60Hz
This patch changes the default pixel clock to effectively generate
1080p resolution at 60 frames per second. It is dependent upon the
kernel device tree file using the specified resolution / display
string in the comments.
Matt Evans [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
arm: quick hack to allow a greater number of CPUs to a guest OS
This is a quick hack to communicate a greater number of CPUs to a guest OS via
the ARM A9 SCU config register. Some OSes (Linux) just look at the bottom field
to count CPUs and with a small change can look at bits [3:0] to learn about up
to 16 CPUs.
Very much unsupported (and contains warning messages as such) but useful for
running 8 core sims without hardwiring CPU count in the guest OS.
Eric Van Hensbergen [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
arm: Add Makefile for aarch64 build of util/m5
Curtis Dunham [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
arch: remove inline specifiers on all inst constrs, all ISAs
With (upcoming) separate compilation, they are useless. Only
link-time optimization could re-inline them, but ideally
feedback-directed optimization would choose to do so only for
profitable (i.e. common) instructions.
Curtis Dunham [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
arm: cleanup ARM ISA definition
Curtis Dunham [Thu, 20 Mar 2014 00:18:43 +0000 (19:18 -0500)]
ext: disable PLY debugging
Very rarely does anyone ever mess with PLY code, and when
such a need arises, the developer can reenable this flag in
their working tree.
This will eliminate the "generating LALR tables" message
during compilation and temporary parser.out file as well.
Curtis Dunham [Fri, 9 May 2014 22:58:46 +0000 (18:58 -0400)]
scons: Require SWIG >= 2.0.4 and remove vector typemaps
SWIG commit
fd666c1 (*) made it unnecessary for gem5 to have these
typemaps to handle Vector types.
* https://github.com/swig/swig/commit/
fd666c1440628a847793bbe1333c27dfa2f757f0
Curtis Dunham [Wed, 23 Apr 2014 09:18:30 +0000 (05:18 -0400)]
arm: Correctly display disassembly of vldmia/vstmia
The MicroMemOp class generates the disassembly for both integer
and floating point instructions, but it would always print its
first operand as an integer register without considering that the
op may be a floating instruction in which case a float register
should be displayed instead.
Mitch Hayenga [Wed, 23 Apr 2014 09:18:29 +0000 (05:18 -0400)]
util: Valgrind suppression addition
Adds a suppression rule to util/valgrind-suppressions due to a minor bug
present in zlib that has no impact on simulation.
Andreas Hansson [Wed, 23 Apr 2014 09:18:27 +0000 (05:18 -0400)]
sim: Use correct unit for abort message
This patch fixes the unit in the abort printout.
Mitchell Hayenga [Wed, 23 Apr 2014 09:18:26 +0000 (05:18 -0400)]
cpu: Fix setTranslateLatency() bug for squashed instructions
setTranslateLatency could sometimes improperly access a deleted request
packet after an instruction was squashed.
Sascha Bischoff [Wed, 23 Apr 2014 09:18:25 +0000 (05:18 -0400)]
misc: Proper type check and import for PortRef
Rewriting the type checking around PortRef, which was interacting strangely
with other Python scripts.
Tested-by: stephan.diestelhorst@arm.com
Mitch Hayenga [Tue, 1 Apr 2014 19:22:06 +0000 (14:22 -0500)]
cpu: Fix case where o3 lsq could print out uninitialized data
In the O3 LSQ, data read/written is printed out in DPRINTFs. However,
the data field is treated as a character string with a null terminated.
However the data field is not encoded this way. This patch removes
that possibility by removing the data part of the print.
Mitch Hayenga [Tue, 1 Apr 2014 19:24:36 +0000 (14:24 -0500)]
mem: Don't print out the data of a cache block
This never actually worked since it was printing out only a word
of the cache block and not the entire thing and doubly didn't work
csprintf overrides the %#x specifier and assumes a char* array is
actually a string.
Mitchell Hayenga [Wed, 23 Apr 2014 09:18:20 +0000 (05:18 -0400)]
arm: Don't use a stack allocated mnemonic
FailUnimplemented passed a stack created mnemonic as a const char * which
causes some grief when the stack goes away.
Dam Sunwoo [Wed, 23 Apr 2014 09:18:18 +0000 (05:18 -0400)]
cpu: Add O3 CPU width checks
O3CPU has a compile-time maximum width set in o3/impl.hh, but checking
the configuration against this limit was not implemented anywhere
except for fetch. Configuring a wider pipe than the limit can silently
cause various issues during the simulation. This patch adds the proper
checking in the constructor of the various pipeline stages.
Curtis Dunham [Wed, 23 Apr 2014 09:17:59 +0000 (05:17 -0400)]
base: explicitly suggest potential use of 'All' debug flags
Without this declaration, new clangs will complain about this value
being unused. It has no explicit use in the codebase, but it can be
useful to turn on all debugging flags while in a debugger to greatly
increase simulator verbosity.
Curtis Dunham [Wed, 23 Apr 2014 09:17:57 +0000 (05:17 -0400)]
arch: remove 'null update' check in isa-parser
SCons already does this for all build steps.
Curtis Dunham [Tue, 11 Feb 2014 00:24:20 +0000 (18:24 -0600)]
stats: better error message for uninitialized statistic
As suggested by Nathan Binkert in 2008:
http://permalink.gmane.org/gmane.comp.emulators.m5.users/2676
Andreas Hansson [Tue, 22 Apr 2014 07:12:15 +0000 (03:12 -0400)]
stats: updates for pc-switcheroo-full due to o3 smt fix
Nilay Vaish [Sat, 19 Apr 2014 14:16:14 +0000 (09:16 -0500)]
stats: updates due to o3 smt fix
+ changes to one ruby regression config.ini file.
Nilay Vaish [Sat, 19 Apr 2014 14:00:31 +0000 (09:00 -0500)]
ruby: slicc: remove old documentation
Has not been maintained at all. Since there is alternate documentation
available on gem5.org, no need to have this separately.
Nilay Vaish [Sat, 19 Apr 2014 14:00:31 +0000 (09:00 -0500)]
ruby: slicc: slight change to rule for transitions
It had an unnecessary pairs token which is being removed.
Faissal Sleiman [Sat, 19 Apr 2014 14:00:30 +0000 (09:00 -0500)]
o3: Fix occupancy checks for SMT
A number of calls to isEmpty() and numFreeEntries()
should be thread-specific.
In cpu.cc, the fact that tid is /*commented*/ out is a bug. Say the rob
has instructions from thread 0 (isEmpty() returns false), and none from
thread 1. If we are trying to squash all of thread 1, then
readTailInst(thread 1) will be called because rob->isEmpty() returns
false. The result is end_it is not in the list and the while
statement loops indefinitely back over the cpu's instList.
In iew_impl.hh, all threads are told they have the entire remaining IQ, when
each thread actually has a certain allocation. The result is extra stalls at
the iew dispatch stage which the rename stage usually takes care of.
In commit_impl.hh, rob->readHeadInst(thread 1) can be called if the rob only
contains instructions from thread 0. This returns a dummyInst (which may work
since we are trying to squash all instructions, but hardly seems like the right
way to do it).
In rob_impl.hh this fix skips the rest of the function more frequently and is
more efficient.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Marco Elver [Sat, 19 Apr 2014 14:00:30 +0000 (09:00 -0500)]
ruby: recorder: Fix (de-)serializing with different cache block-sizes
Upon aggregating records, serialize system's cache-block size, as the
cache-block size can be different when restoring from a checkpoint. This way,
we can correctly read all records when restoring from a checkpoints, even if
the cache-block size is different.
Note, that it is only possible to restore from a checkpoint if the
desired cache-block size is smaller or equal to the cache-block size
when the checkpoint was taken; we can split one larger request into
multiple small ones, but it is not reliable to do the opposite.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 19 Apr 2014 14:00:30 +0000 (09:00 -0500)]
config: ruby: remove memory controller from network test
It is not in use and not required as such.
Anthony Gutierrez [Mon, 14 Apr 2014 23:30:24 +0000 (19:30 -0400)]
arm: set default kernels for VExpress_EMM and VExpress_EMM64
Andreas Hansson [Sun, 13 Apr 2014 14:07:55 +0000 (10:07 -0400)]
scons: Fix python-config parsing by adding strip()
This patch fixes an issue with the way the python-config path is
parsed, as it caused issues on systems where a newline ended up being
included in the path.
Gedare Bloom [Thu, 10 Apr 2014 18:43:33 +0000 (13:43 -0500)]
config: add num-work-ids command line option
Adds the parameter --num-work-ids to Options.py and reads the parameter
into the System params in Simulation.py. This parameter enables setting
the number of possible work items to different than 16. Support for this
parameter already exists in src/sim/System.py, so this changeset only
affects the Python config files.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Stian Hvatum [Thu, 10 Apr 2014 18:40:15 +0000 (13:40 -0500)]
scons: compile on systems where python2 and python3 co-exist
Compile gem5 on systems where python2 and python3 co-exists without any
changes in path. python2-config is chosen over python-config if it exists.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andreas Sandberg [Wed, 9 Apr 2014 14:01:58 +0000 (16:01 +0200)]
kvm, x86: Add initial support for multicore simulation
Simulating a SMP or multicore requires devices to be shared between
multiple KVM vCPUs. This means that locking is required when accessing
devices. This changeset adds the necessary locking to allow devices to
execute correctly. It is implemented by temporarily migrating the KVM
CPU to the VM's (and devices) event queue when handling
MMIO. Similarly, the VM migrates to the interrupt controller's event
queue when delivering an interrupt.
The support for fast-forwarding of multicore simulations added by this
changeset assumes that all devices in a system are simulated in the
same thread and each vCPU has its own thread. Special care must be
taken to ensure that devices living under the CPU in the object
hierarchy (e.g., the interrupt controller) do not inherit the parent
CPUs thread and are assigned to device thread. The KvmVM object is
assumed to live in the same thread as the other devices in the system.
Andreas Sandberg [Wed, 9 Apr 2014 14:01:43 +0000 (16:01 +0200)]
dev: Protect PollEvent processing when running in parallel mode
The calling thread is undefined when the PollQueue services events.
This implies that PollEvents need to handle the case where they are
processed from a different thread than the thread that created the
event. This changeset adds temporary event queue migrations to the VNC
server, the ethernet tap device, and the terminal to protect them from
inter-thread calls.
Nilay Vaish [Tue, 8 Apr 2014 18:26:30 +0000 (13:26 -0500)]
ruby: slicc: change enqueue statement
As of now, the enqueue statement can take in any number of 'pairs' as
argument. But we only use the pair in which latency is the key. This
latency is allowed to be either a fixed integer or a member variable of
controller in which the expression appears. This patch drops the use of pairs
in an enqueue statement. Instead, an expression is allowed which will be
interpreted to be the latency of the enqueue. This expression can anything
allowed by slicc including a constant integer or a member variable.
Nilay Vaish [Tue, 8 Apr 2014 18:26:29 +0000 (13:26 -0500)]
ruby: coherence protocols: drop the phrase IntraChip
The phrase is no longer valid since we do not distinguish between
inter and intra chip communication.
Andreas Sandberg [Thu, 3 Apr 2014 09:22:49 +0000 (11:22 +0200)]
sim: Add the ability to lock and migrate between event queues
We need the ability to lock event queues to enable device accesses
across threads. The serviceOne() method now takes a service lock prior
to handling a new event. By locking an event queue, a different
thread/eq can effectively execute in the context of the locked event
queue. To simplify temporary event queue migrations, this changeset
introduces the EventQueue::ScopedMigration class that unlocks the
current event queue, locks a new event queue, and updates the current
event queue variable.
In order to prevent deadlocks, event queues need to be released when
waiting on barriers. This is implemented using the
EventQueue::ScopedRelease class. An instance of this class is, for
example, used in the BaseGlobalEvent class to release the event queue
when waiting on the synchronization barrier.
The intended use for this functionality is when devices need to be
accessed across thread boundaries. For example, when fast-forwarding,
it might be useful to run devices and CPUs in separate threads. In
such a case, the CPU locks the device queue whenever it needs to
perform IO. This functionality is primarily intended for KVM.
Note: Migrating between event queues can lead to non-deterministic
timing. Use with extreme care!
--HG--
extra : rebase_source :
23e3a741a1fd73861d1339782dbbe1bc76285315
Anthony Gutierrez [Tue, 1 Apr 2014 16:44:30 +0000 (12:44 -0400)]
ext: add McPAT source
this patch adds the source for mcpat, a power, area, and timing modeling
framework.
Anthony Gutierrez [Tue, 1 Apr 2014 16:35:31 +0000 (12:35 -0400)]
arm: fix typos in makefile for ARM m5 util and link statically
1) fixes a typo for clean target libgemOpJni.so -> libgem5OpJni.so
2) addes jni_gem5Op.h to clean since it is added during make
3) links the m5 utility statically since it won't work on some images otherwise
Nilay Vaish [Tue, 1 Apr 2014 16:17:46 +0000 (11:17 -0500)]
configs: use SimpleMemory when using ruby in se mode
A recent changeset altered the default memory class to DRAMCtrl. In se mode,
ruby uses the physical memory to check if a given address is within the bounds
of the physical memory. SimpleMemory is enough for this. Moreover,
SimpleMemory does not check whether it is connected or not, something which
DRAMCtrl does.
Marco Elver [Tue, 25 Mar 2014 18:15:04 +0000 (13:15 -0500)]
cpu: o3: lsq: Fix TSO implementation
This patch fixes violation of TSO in the O3CPU, as all loads must be
ordered with all other loads. In the LQ, if a snoop is observed, all
subsequent loads need to be squashed if the system is TSO.
Prior to this patch, the following case could be violated:
P0 | P1 ;
MOV [x],mail=/usr/spool/mail/nilay | MOV EAX,[y] ;
MOV [y],mail=/usr/spool/mail/nilay | MOV EBX,[x] ;
exists (1:EAX=1 /\ 1:EBX=0) [is a violation]
The problem was found using litmus [http://diy.inria.fr].
Committed by: Nilay Vaish <nilay@cs.wisc.edu
Andreas Hansson [Sun, 23 Mar 2014 15:12:19 +0000 (11:12 -0400)]
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Andreas Hansson [Sun, 23 Mar 2014 15:12:14 +0000 (11:12 -0400)]
mem: Track DRAM read/write switching and add hysteresis
This patch adds stats for tracking the number of reads/writes per bus
turn around, and also adds hysteresis to the write-to-read switching
to ensure that the queue does not oscilate around the low threshold.
Andreas Hansson [Sun, 23 Mar 2014 15:12:12 +0000 (11:12 -0400)]
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).
As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.
--HG--
rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py
rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc
rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
Andreas Hansson [Sun, 23 Mar 2014 15:12:10 +0000 (11:12 -0400)]
mem: Change memory defaults to be more representative
Make the default memory type DDR3-1600 x64, and use the open-adaptive
page policy. This change is aiming to ensure that users by default are
using a realistic memory system.
Wendy Elsasser [Sun, 23 Mar 2014 15:12:08 +0000 (11:12 -0400)]
mem: Add close adaptive paging policy to DRAM controller model
This patch adds a second adaptive page policy to the DRAM controller,
closing the page unless there are already queued accesses to the open
page.
Andreas Hansson [Sun, 23 Mar 2014 15:12:06 +0000 (11:12 -0400)]
mem: DRAM controller tidying up
Minor tidying up and removing of redundant code, including the
printing of queue state every million accesses.
Andreas Hansson [Sun, 23 Mar 2014 15:12:05 +0000 (11:12 -0400)]
mem: Fix bug in DRAM bytes per activate
This patch ensures that we do not sample the bytes per activate when
the row has already been closed.
Andreas Hansson [Sun, 23 Mar 2014 15:12:03 +0000 (11:12 -0400)]
mem: Limit the accesses to a page before forcing a precharge
This patch adds a basic starvation-prevention mechanism where a DRAM
page is forced to close after a certain number of accesses. The limit
is combined with the open and open-adaptive page policy and if reached
causes an auto-precharge.
Andreas Hansson [Sun, 23 Mar 2014 15:12:01 +0000 (11:12 -0400)]
mem: Make DRAM write queue draining more aggressive
This patch changes the triggering condition for the write draining
such that we grab the opportunity to issue writes if there are no
reads waiting (as opposed to waiting for the writes to reach the high
threshold). As a result, we potentially drain some of the writes in read
idle periods (if any).
A low threshold is added to be able to control how many write bursts
are kept in the memory controller queue (acting as on-chip storage).
The high and low thresholds are updated to sensible values for a 32/64
size write buffer. Note that the thresholds should be adjusted along
with the queue sizes.
This patch also adds some basic initialisation sanity checks and moves
part of the initialisation to the constructor.
Andreas Hansson [Sun, 23 Mar 2014 15:12:00 +0000 (11:12 -0400)]
config: Add a DRAM efficiency-sweep script
This patch adds a configuration that simplifies evaluation of DRAM
controller configurations by automating a sweep of stride size and
bank parallelism. It works in a rather unconventional way, as it needs
to print the traffic generator stimuli based on the memory
organisation. Hence, it starts by configuring the memory, then it
prints a traffic-generator config file, and loads it.
The resulting stats have one period per data point, identified by the
stride size, and the number of banks being used.
Neha Agarwal [Sun, 23 Mar 2014 15:11:58 +0000 (11:11 -0400)]
cpu: DRAM Traffic Generator
This patch enables a new 'DRAM' mode to the existing traffic
generator, catered to generate specific requests to DRAM based on
required hit length (stride size) and bank utilization. It is an add on
to the Random mode.
The basic idea is to control how many successive packets target the
same page, and how many banks are being used in parallel. This gives a
two-dimensional space that stresses different aspects of the DRAM
timing.
The configuration file needed to use this patch has to be changed as
follow: (reference to Random Mode, LPDDR3 memory type)
'STATE 0
10000000000 RANDOM 50 0
134217728 64 3004 5002 0'
-> 'STATE 0
10000000000 DRAM 50 0
134217728 32 3004 5002 0 96 1024 8 6 1'
The last 4 parameters to be added are:
<stride size (bytes), page size(bytes), number of banks available in DRAM,
number of banks to be utilized, address mapping scheme>
The address mapping information is used to get the stride address
stream of the specified size and to know where to find the bank
bits. The configuration file has a parameter where '0'-> RoCoRaBaCh,
'1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the
generator currently assumes a single channel and a single rank. This
is to avoid overwhelming the traffic generator with information about
the memory organisation.
Neha Agarwal [Sun, 23 Mar 2014 15:11:56 +0000 (11:11 -0400)]
mem: DDR3 config for comparing with DRAMSim2
This patch adds a new DDR3 configuration to match with the parameters
that are specified in one of the DDR3 configs used in DRAMSim2.
Andreas Hansson [Sun, 23 Mar 2014 15:11:53 +0000 (11:11 -0400)]
mem: More descriptive address-mapping scheme names
This patch adds the row bits to the name of the address mapping
schemes to make it more clear that all the current schemes places the
row bits as the most significant bits.
Curtis Dunham [Sun, 23 Mar 2014 15:11:51 +0000 (11:11 -0400)]
scons: Shush scons
make 'scons -s' actually silent.
Stan Czerniawski [Sun, 23 Mar 2014 15:11:49 +0000 (11:11 -0400)]
misc: Fix -q (quiet) flag
Check the right flag.
Andreas Hansson [Sun, 23 Mar 2014 15:11:48 +0000 (11:11 -0400)]
ruby: Move Ruby debug flags to ruby dir and remove stale options
This patch moves the Ruby-related debug flags to the ruby
sub-directory, and also removes the state SConsopts that add the
no-longer-used NO_VECTOR_BOUNDS_CHECK.