yosys.git
7 years agoFix EDIF: portRef member 0 is always the MSB bit
Clifford Wolf [Sun, 19 Mar 2017 13:53:28 +0000 (14:53 +0100)]
Fix EDIF: portRef member 0 is always the MSB bit

7 years agoAdd simple EDIF test case generator and checker
Clifford Wolf [Sat, 18 Mar 2017 14:00:03 +0000 (15:00 +0100)]
Add simple EDIF test case generator and checker

7 years agoFix verilog pre-processor for multi-level relative includes
Clifford Wolf [Tue, 14 Mar 2017 16:27:28 +0000 (17:27 +0100)]
Fix verilog pre-processor for multi-level relative includes

7 years agoImprove smt2 encodings of assert/assume/cover, better wire_smt2 help msg
Clifford Wolf [Sat, 4 Mar 2017 22:41:54 +0000 (23:41 +0100)]
Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg

7 years agoAdd write_aiger $anyseq support
Clifford Wolf [Thu, 2 Mar 2017 15:39:48 +0000 (16:39 +0100)]
Add write_aiger $anyseq support

7 years agoAllow $anyconst, etc. in non-formal SV mode
Clifford Wolf [Wed, 1 Mar 2017 09:47:05 +0000 (10:47 +0100)]
Allow $anyconst, etc. in non-formal SV mode

7 years agoDisable opt_merge for $anyseq and $anyconst
Clifford Wolf [Tue, 28 Feb 2017 21:17:00 +0000 (22:17 +0100)]
Disable opt_merge for $anyseq and $anyconst

7 years agoUse hex addresses in smtbmc vcd mem traces
Clifford Wolf [Tue, 28 Feb 2017 12:54:50 +0000 (13:54 +0100)]
Use hex addresses in smtbmc vcd mem traces

7 years agoAdd "chformal -assert2assume" and friends
Clifford Wolf [Mon, 27 Feb 2017 22:59:59 +0000 (23:59 +0100)]
Add "chformal -assert2assume" and friends

7 years agoAdd "chformal" pass
Clifford Wolf [Mon, 27 Feb 2017 12:25:28 +0000 (13:25 +0100)]
Add "chformal" pass

7 years agoAdd smtbmc support for memory vcd dumping
Clifford Wolf [Sun, 26 Feb 2017 20:26:32 +0000 (21:26 +0100)]
Add smtbmc support for memory vcd dumping

7 years agoFix extra newline bug in write_smt2
Clifford Wolf [Sun, 26 Feb 2017 13:41:27 +0000 (14:41 +0100)]
Fix extra newline bug in write_smt2

7 years agoFix bug in smtio unroll code
Clifford Wolf [Sun, 26 Feb 2017 13:39:07 +0000 (14:39 +0100)]
Fix bug in smtio unroll code

7 years agoFix assert checking in "yosys-smtbmc -c --append"
Clifford Wolf [Sun, 26 Feb 2017 10:06:26 +0000 (11:06 +0100)]
Fix assert checking in "yosys-smtbmc -c --append"

7 years agoImprove (and fix for stbv mode) SMT2 memory API
Clifford Wolf [Sun, 26 Feb 2017 09:58:34 +0000 (10:58 +0100)]
Improve (and fix for stbv mode) SMT2 memory API

7 years agoAdd support for "yosys-smtbmc -c --append"
Clifford Wolf [Sat, 25 Feb 2017 22:41:40 +0000 (23:41 +0100)]
Add support for "yosys-smtbmc -c --append"

7 years agoUpdate ABC to hg rev 3a95bfa55df7
Clifford Wolf [Sat, 25 Feb 2017 21:59:34 +0000 (22:59 +0100)]
Update ABC to hg rev 3a95bfa55df7

7 years agoMerge branch 'klammerj-master'
Clifford Wolf [Sat, 25 Feb 2017 15:36:23 +0000 (16:36 +0100)]
Merge branch 'klammerj-master'

7 years agoImprove "write_edif" help message
Clifford Wolf [Sat, 25 Feb 2017 15:35:53 +0000 (16:35 +0100)]
Improve "write_edif" help message

7 years agoMove EdifNames out of double-private namespace
Clifford Wolf [Sat, 25 Feb 2017 15:29:27 +0000 (16:29 +0100)]
Move EdifNames out of double-private namespace

7 years agoClean up edif code, swap bit indexing of "upto" ports
Clifford Wolf [Sat, 25 Feb 2017 15:28:34 +0000 (16:28 +0100)]
Clean up edif code, swap bit indexing of "upto" ports

7 years agoMerge branch 'master' of https://github.com/klammerj/yosys into klammerj-master
Clifford Wolf [Sat, 25 Feb 2017 14:59:02 +0000 (15:59 +0100)]
Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master

7 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sat, 25 Feb 2017 12:08:27 +0000 (13:08 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys

7 years agoAdd $live and $fair support to AIGER back-end.
Clifford Wolf [Sat, 25 Feb 2017 12:07:15 +0000 (13:07 +0100)]
Add $live and $fair support to AIGER back-end.

7 years agoAdd $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf [Sat, 25 Feb 2017 09:36:39 +0000 (10:36 +0100)]
Add $live and $fair cell types, add support for s_eventually keyword

7 years agoMerge pull request #322 from azonenberg/master
Clifford Wolf [Fri, 24 Feb 2017 18:23:29 +0000 (19:23 +0100)]
Merge pull request #322 from azonenberg/master

Add POUT to GP_COUNTx cells

7 years agoAdd "write_smt2 -stbv"
Clifford Wolf [Fri, 24 Feb 2017 17:24:53 +0000 (18:24 +0100)]
Add "write_smt2 -stbv"

7 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Fri, 24 Feb 2017 16:12:45 +0000 (08:12 -0800)]
Merge https://github.com/cliffordwolf/yosys

7 years agoAdd SMT2 statebv mode (inactive for now)
Clifford Wolf [Fri, 24 Feb 2017 13:04:52 +0000 (14:04 +0100)]
Add SMT2 statebv mode (inactive for now)

7 years agoDid as you requested, /but/...
Johann Klammer [Fri, 24 Feb 2017 12:18:49 +0000 (13:18 +0100)]
Did as you requested, /but/...

Now the nets are wired in reverse again because the netlister still uses zero-based indices.

7 years agoMerge pull request #320 from joshhead/uninstall-binpath-fix
Clifford Wolf [Fri, 24 Feb 2017 11:48:12 +0000 (12:48 +0100)]
Merge pull request #320 from joshhead/uninstall-binpath-fix

Add missing slashes in paths for make uninstall

7 years agoAdd missing slashes in paths for make uninstall
Josh Headapohl [Fri, 24 Feb 2017 01:21:03 +0000 (20:21 -0500)]
Add missing slashes in paths for make uninstall

Running make uninstall used to fail to remove binaries:
rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc

Fix Makefile so that it runs a command like this:
rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc

7 years agoadd options for edif flavors
Johann Klammer [Thu, 23 Feb 2017 18:42:37 +0000 (19:42 +0100)]
add options for edif flavors

*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices

7 years agoAdd support for SystemVerilog unique, unique0, and priority case
Clifford Wolf [Thu, 23 Feb 2017 15:33:19 +0000 (16:33 +0100)]
Add support for SystemVerilog unique, unique0, and priority case

7 years agoPreserve string parameters
Clifford Wolf [Thu, 23 Feb 2017 14:39:13 +0000 (15:39 +0100)]
Preserve string parameters

7 years agoFix mingw compile issue (2nd attempt)
Clifford Wolf [Thu, 23 Feb 2017 13:21:02 +0000 (14:21 +0100)]
Fix mingw compile issue (2nd attempt)

7 years agoFix mingw compile issue (maybe.. I can't test it)
Clifford Wolf [Thu, 23 Feb 2017 12:59:02 +0000 (13:59 +0100)]
Fix mingw compile issue (maybe.. I can't test it)

7 years agoAdded SystemVerilog support for ++ and --
Clifford Wolf [Thu, 23 Feb 2017 10:21:33 +0000 (11:21 +0100)]
Added SystemVerilog support for ++ and --

7 years agoUpdate ABC to hg rev 8da4dc435b9f
Clifford Wolf [Wed, 22 Feb 2017 18:20:47 +0000 (19:20 +0100)]
Update ABC to hg rev 8da4dc435b9f

7 years agoAdd "yosys-smtbmc -S <opt>"
Clifford Wolf [Sun, 19 Feb 2017 21:51:29 +0000 (22:51 +0100)]
Add "yosys-smtbmc -S <opt>"

7 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Thu, 16 Feb 2017 15:48:44 +0000 (07:48 -0800)]
Merge https://github.com/cliffordwolf/yosys

7 years agoCopy attributes to _TECHMAP_REPLACE_ cells
Clifford Wolf [Thu, 16 Feb 2017 11:28:42 +0000 (12:28 +0100)]
Copy attributes to _TECHMAP_REPLACE_ cells

7 years agoFix eval implementation of $_NOR_
Clifford Wolf [Thu, 16 Feb 2017 11:17:03 +0000 (12:17 +0100)]
Fix eval implementation of $_NOR_

7 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Tue, 14 Feb 2017 16:29:37 +0000 (08:29 -0800)]
Merge https://github.com/cliffordwolf/yosys

7 years agoFix incorrect "incompatible re-declaration of wire" error in tasks/functions
Clifford Wolf [Tue, 14 Feb 2017 14:10:59 +0000 (15:10 +0100)]
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions

7 years agoAdd warning about x/z bits left unconnected in EDIF output
Clifford Wolf [Tue, 14 Feb 2017 11:49:35 +0000 (12:49 +0100)]
Add warning about x/z bits left unconnected in EDIF output

7 years agoFix double-call of log_pop() in synth_greenpak4
Clifford Wolf [Tue, 14 Feb 2017 10:57:54 +0000 (11:57 +0100)]
Fix double-call of log_pop() in synth_greenpak4

7 years agoMerge pull request #313 from azidar/bugfix-assign-wmask
Clifford Wolf [Tue, 14 Feb 2017 10:49:14 +0000 (11:49 +0100)]
Merge pull request #313 from azidar/bugfix-assign-wmask

More progress on Firrtl backend.

7 years agoMore progress on Firrtl backend.
Adam Izraelevitz [Tue, 22 Nov 2016 01:28:17 +0000 (17:28 -0800)]
More progress on Firrtl backend.

Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.

7 years agoDo not fix port widths on any blackbox instances
Clifford Wolf [Mon, 13 Feb 2017 16:07:38 +0000 (17:07 +0100)]
Do not fix port widths on any blackbox instances

7 years agoFix techmap for inout ports connected to inout ports
Clifford Wolf [Mon, 13 Feb 2017 15:55:25 +0000 (16:55 +0100)]
Fix techmap for inout ports connected to inout ports

7 years agoDo not eagerly fix port widths on parameterized cells
Clifford Wolf [Sun, 12 Feb 2017 16:42:57 +0000 (17:42 +0100)]
Do not eagerly fix port widths on parameterized cells

7 years agoAdd "yosys -w" for suppressing warnings
Clifford Wolf [Sun, 12 Feb 2017 10:11:00 +0000 (11:11 +0100)]
Add "yosys -w" for suppressing warnings

7 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Sat, 11 Feb 2017 19:25:16 +0000 (11:25 -0800)]
Merge https://github.com/cliffordwolf/yosys

7 years agoAdd support for verific mem initialization
Clifford Wolf [Sat, 11 Feb 2017 14:57:36 +0000 (15:57 +0100)]
Add support for verific mem initialization

7 years agoFix another stupid bug in the same line
Clifford Wolf [Sat, 11 Feb 2017 10:47:51 +0000 (11:47 +0100)]
Fix another stupid bug in the same line

7 years agoAdd verific support for initialized variables
Clifford Wolf [Sat, 11 Feb 2017 10:40:18 +0000 (11:40 +0100)]
Add verific support for initialized variables

7 years agoImprove handling of Verific warnings and error messages
Clifford Wolf [Sat, 11 Feb 2017 10:39:50 +0000 (11:39 +0100)]
Improve handling of Verific warnings and error messages

7 years agoFix extremely stupid typo
Clifford Wolf [Sat, 11 Feb 2017 10:09:07 +0000 (11:09 +0100)]
Fix extremely stupid typo

7 years agoAdd log_wire() API
Clifford Wolf [Sat, 11 Feb 2017 10:08:12 +0000 (11:08 +0100)]
Add log_wire() API

7 years agoFixed some "used uninitialized" warnings in opt_expr
Clifford Wolf [Sat, 11 Feb 2017 09:50:48 +0000 (10:50 +0100)]
Fixed some "used uninitialized" warnings in opt_expr

7 years agoEvaluate all the $(shell ...) stuff for CXXFLAGS et al only once
Clifford Wolf [Sat, 11 Feb 2017 09:28:13 +0000 (10:28 +0100)]
Evaluate all the $(shell ...) stuff for CXXFLAGS et al only once

7 years agoMerge branch 'stv0g-master'
Clifford Wolf [Sat, 11 Feb 2017 09:20:10 +0000 (10:20 +0100)]
Merge branch 'stv0g-master'

7 years agoMake MacOS Makefile stuff more compact
Clifford Wolf [Sat, 11 Feb 2017 09:19:21 +0000 (10:19 +0100)]
Make MacOS Makefile stuff more compact

7 years agoMerge branch 'master' of https://github.com/stv0g/yosys into stv0g-master
Clifford Wolf [Sat, 11 Feb 2017 09:12:17 +0000 (10:12 +0100)]
Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master

7 years agoAdd optimization of (a && 1'b1) and (a || 1'b0)
Clifford Wolf [Sat, 11 Feb 2017 09:01:17 +0000 (10:01 +0100)]
Add optimization of (a && 1'b1) and (a || 1'b0)

7 years agoMerge pull request #308 from C-Elegans/opt_compare_fix_pr
Clifford Wolf [Sat, 11 Feb 2017 09:04:48 +0000 (10:04 +0100)]
Merge pull request #308 from C-Elegans/opt_compare_fix_pr

Fix issue #306, "Bug in opt -full"

7 years agoFix issue #306, "Bug in opt -full"
C-Elegans [Fri, 10 Feb 2017 15:28:19 +0000 (10:28 -0500)]
Fix issue #306, "Bug in opt -full"

Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0

7 years agoUse pkg-config for linking tcl-tk
Steffen Vogel [Fri, 10 Feb 2017 13:06:54 +0000 (10:06 -0300)]
Use pkg-config for linking tcl-tk

Both MacPorts and Homebrew have a pkg-config file for TCL. So lets use it.

7 years agoDont mix Homebrew and MacPorts build options
Steffen Vogel [Fri, 10 Feb 2017 13:04:42 +0000 (10:04 -0300)]
Dont mix Homebrew and MacPorts build options

7 years agoRemove space after backslash
Steffen Vogel [Thu, 9 Feb 2017 22:08:21 +0000 (19:08 -0300)]
Remove space after backslash

7 years agoApplied fixes from @joshhead (thanks for your effors!)
Steffen Vogel [Thu, 9 Feb 2017 21:53:37 +0000 (18:53 -0300)]
Applied fixes from @joshhead (thanks for your effors!)

7 years agoFix handling of init attributes with strange width
Clifford Wolf [Thu, 9 Feb 2017 15:06:58 +0000 (16:06 +0100)]
Fix handling of init attributes with strange width

7 years agoAdd checker support to verilog front-end
Clifford Wolf [Thu, 9 Feb 2017 12:51:44 +0000 (13:51 +0100)]
Add checker support to verilog front-end

7 years agoAdd "rand" and "rand const" verific support
Clifford Wolf [Thu, 9 Feb 2017 11:53:46 +0000 (12:53 +0100)]
Add "rand" and "rand const" verific support

7 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Thu, 9 Feb 2017 06:12:29 +0000 (22:12 -0800)]
Merge https://github.com/cliffordwolf/yosys

7 years agoAdd SV "rand" and "const rand" support
Clifford Wolf [Wed, 8 Feb 2017 13:38:15 +0000 (14:38 +0100)]
Add SV "rand" and "const rand" support

7 years agoAdd PSL parser mode to verific front-end
Clifford Wolf [Wed, 8 Feb 2017 09:40:33 +0000 (10:40 +0100)]
Add PSL parser mode to verific front-end

7 years agoAdded notes for compilation on OS X
Steffen Vogel [Tue, 7 Feb 2017 14:12:31 +0000 (11:12 -0300)]
Added notes for compilation on OS X

7 years agoFix compilation on OS X in order to support both MacPorts and Homebrew
Steffen Vogel [Tue, 7 Feb 2017 14:12:12 +0000 (11:12 -0300)]
Fix compilation on OS X in order to support both MacPorts and Homebrew

7 years agoAllow standard tools to be overwritten in make invocation
Steffen Vogel [Tue, 7 Feb 2017 14:09:15 +0000 (11:09 -0300)]
Allow standard tools to be overwritten in make invocation

7 years agoAdd "read_blif -wideports"
Clifford Wolf [Mon, 6 Feb 2017 13:48:03 +0000 (14:48 +0100)]
Add "read_blif -wideports"

7 years agoFix undef propagation bug in $pmux SAT model
Clifford Wolf [Sun, 5 Feb 2017 21:43:33 +0000 (22:43 +0100)]
Fix undef propagation bug in $pmux SAT model

7 years agoUpdate ABC to hg rev a2fcd1cc61a6
Clifford Wolf [Sun, 5 Feb 2017 19:04:17 +0000 (20:04 +0100)]
Update ABC to hg rev a2fcd1cc61a6

7 years agoMerge pull request #304 from esden/gsed-darwin
Clifford Wolf [Sun, 5 Feb 2017 11:00:21 +0000 (12:00 +0100)]
Merge pull request #304 from esden/gsed-darwin

Use gsed vs sed on Darwin.

7 years agoUse -E sed parameter instead of -r.
Piotr Esden-Tempski [Wed, 1 Feb 2017 00:00:17 +0000 (16:00 -0800)]
Use -E sed parameter instead of -r.

BSD sed equivalent to -r parameter is -E and it is also supported in GNU
sed thus using -E results in support on both platforms.

7 years agoAdd assert check in "yosys-smtbmc -c"
Clifford Wolf [Sat, 4 Feb 2017 20:22:17 +0000 (21:22 +0100)]
Add assert check in "yosys-smtbmc -c"

7 years agoImprove yosys-smtbmc cover() support
Clifford Wolf [Sat, 4 Feb 2017 20:10:24 +0000 (21:10 +0100)]
Improve yosys-smtbmc cover() support

7 years agoPartially implement cover() support in yosys-smtbmc
Clifford Wolf [Sat, 4 Feb 2017 17:17:08 +0000 (18:17 +0100)]
Partially implement cover() support in yosys-smtbmc

7 years agoFurther improve cover() support
Clifford Wolf [Sat, 4 Feb 2017 16:02:13 +0000 (17:02 +0100)]
Further improve cover() support

7 years agoAdd $cover cell type and SVA cover() support
Clifford Wolf [Sat, 4 Feb 2017 13:14:26 +0000 (14:14 +0100)]
Add $cover cell type and SVA cover() support

7 years agoAdd assert/assume support to verific front-end
Clifford Wolf [Sat, 4 Feb 2017 12:36:00 +0000 (13:36 +0100)]
Add assert/assume support to verific front-end

7 years agoUpdate ABC to hg rev fe96921e5d50
Clifford Wolf [Wed, 1 Feb 2017 10:15:37 +0000 (11:15 +0100)]
Update ABC to hg rev fe96921e5d50

7 years agoUpdate ABC scripts to use "&nf" instead of "map"
Clifford Wolf [Wed, 1 Feb 2017 10:14:20 +0000 (11:14 +0100)]
Update ABC scripts to use "&nf" instead of "map"

7 years agoMerge branch 'C-Elegans-opt_compare_pr'
Clifford Wolf [Tue, 31 Jan 2017 15:21:23 +0000 (16:21 +0100)]
Merge branch 'C-Elegans-opt_compare_pr'

7 years agoFix indenting and log messages in code merged from opt_compare_pr
Clifford Wolf [Tue, 31 Jan 2017 15:20:56 +0000 (16:20 +0100)]
Fix indenting and log messages in code merged from opt_compare_pr

7 years agoMerge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans...
Clifford Wolf [Tue, 31 Jan 2017 14:54:41 +0000 (15:54 +0100)]
Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr

7 years agouse Homebrew only if installed
Steffen Vogel [Tue, 31 Jan 2017 13:06:06 +0000 (10:06 -0300)]
use Homebrew only if installed

7 years agoImprove opt_rmdff support for $dlatch cells
Clifford Wolf [Tue, 31 Jan 2017 09:15:04 +0000 (10:15 +0100)]
Improve opt_rmdff support for $dlatch cells

7 years agoRefactor and generalize the comparision optimization
C-Elegans [Mon, 30 Jan 2017 22:52:16 +0000 (17:52 -0500)]
Refactor and generalize the comparision optimization

Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a