Ali Saidi [Thu, 25 Jan 2007 18:43:46 +0000 (13:43 -0500)]
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision :
50a23837fd888393a5c2aa35cbd1abeebb7f55d4
Ali Saidi [Tue, 23 Jan 2007 20:50:03 +0000 (15:50 -0500)]
use pstate.am to mask off PC/NPC where it needs to +be
check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
--HG--
extra : convert_revision :
02a51c141ee3f9a2600c28eac018ea7216f3655c
Ali Saidi [Tue, 23 Jan 2007 02:57:01 +0000 (21:57 -0500)]
fix compiling on x86/Solaris
--HG--
extra : convert_revision :
f7d21fc277dd7172c244d83fb012883dc8b67895
Ali Saidi [Tue, 23 Jan 2007 02:55:43 +0000 (21:55 -0500)]
clean up fault code a little bit
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc:
make AsiIsLittle() be all the little asis.
Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
clean up the do*Fault code.... Make it work like legion, in particular
pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
implement some more twin ASIs
src/arch/sparc/tlb.cc:
All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
softint is supported now, no more need to
--HG--
extra : convert_revision :
aef2a1b93719235edff830a17a8ec52f23ec9f8b
Ali Saidi [Tue, 23 Jan 2007 02:45:29 +0000 (21:45 -0500)]
we decided to check for .interp instead of .dynamic
--HG--
extra : convert_revision :
4f5c7f9c7653e1e9ebbd488c07426d9f944bb25f
Ali Saidi [Mon, 22 Jan 2007 21:17:11 +0000 (16:17 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
Ali Saidi [Mon, 22 Jan 2007 21:14:06 +0000 (16:14 -0500)]
check if an executable is dynamic and die if it is
Only implemented for ELf. Someone might want to implement it for ecoff and some point
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add a function to check if an executable is dynamic
src/sim/process.cc:
check if an executable is dynamic and die if it is
--HG--
extra : convert_revision :
830b1b50b08a5abaf895ce6251bbc702c986eebf
Ali Saidi [Mon, 22 Jan 2007 21:11:49 +0000 (16:11 -0500)]
use writeTagAccess() function to unify writing of Tag access registers
Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)
--HG--
extra : convert_revision :
5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
Ali Saidi [Mon, 22 Jan 2007 01:02:41 +0000 (20:02 -0500)]
make sure that page bits of VA on tlb insert are 0
--HG--
extra : convert_revision :
f04af884687e9b8631e910cf62cd4a58d035c744
Ali Saidi [Sun, 21 Jan 2007 23:04:40 +0000 (18:04 -0500)]
add dumb time of day device
--HG--
extra : convert_revision :
52e51ff49f7ed73065f04707ded06dc7254292c4
Ali Saidi [Sun, 21 Jan 2007 04:12:32 +0000 (23:12 -0500)]
fix InterruptLevel code to return the correct level
(the bit positition that is set in softint)
--HG--
extra : convert_revision :
ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
Ali Saidi [Sun, 21 Jan 2007 04:10:43 +0000 (23:10 -0500)]
atually set all 64 bits of the retun value to 0
--HG--
extra : convert_revision :
77bfdf07a49d41a2392f429fdc632c1461ac504c
Ali Saidi [Sun, 21 Jan 2007 04:09:28 +0000 (23:09 -0500)]
fix flushw implementation
--HG--
extra : convert_revision :
136b2bddc7cb70cde30e930ad3a13bd56c7162e1
Ali Saidi [Sat, 20 Jan 2007 17:37:02 +0000 (12:37 -0500)]
Rearange tlb code to remove some duplicate
Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0
--HG--
extra : convert_revision :
fb4ef4b90270c8db676ffe53578acfa3c244526e
Ali Saidi [Sat, 20 Jan 2007 17:34:00 +0000 (12:34 -0500)]
Spill and Fill handlers are actually n*4 + the start address
--HG--
extra : convert_revision :
a42f01a84e4b7ba9e6029df50e1612d410a8ba22
Lisa Hsu [Sat, 20 Jan 2007 02:34:21 +0000 (21:34 -0500)]
Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
--HG--
extra : convert_revision :
9b8567bb775ed6fcc30096f1ab4cc37058bc7376
Lisa Hsu [Sat, 20 Jan 2007 02:33:36 +0000 (21:33 -0500)]
some hstick and hintp changes.
src/arch/sparc/interrupts.hh:
condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
implement HINTP
src/arch/sparc/ua2005.cc:
don't post interrupt unless it is enabled.
--HG--
extra : convert_revision :
f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
Ali Saidi [Wed, 17 Jan 2007 23:36:12 +0000 (18:36 -0500)]
Allow ASI_LDTX_REAL
--HG--
extra : convert_revision :
ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
Ali Saidi [Wed, 17 Jan 2007 22:59:22 +0000 (17:59 -0500)]
do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry
--HG--
extra : convert_revision :
5a14fbcdcfc13156c63fa41ddeca474660143b32
Ali Saidi [Wed, 17 Jan 2007 18:09:26 +0000 (13:09 -0500)]
Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision :
c2f60e49683446bcc3afdf911da172de0422b8ad
Ali Saidi [Wed, 17 Jan 2007 00:12:33 +0000 (19:12 -0500)]
In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null
This way we'll jump immediately to the handler
--HG--
extra : convert_revision :
36218d3a5c2342337e66e1229ea2219533efd41e
Ali Saidi [Wed, 17 Jan 2007 00:09:27 +0000 (19:09 -0500)]
Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
--HG--
extra : convert_revision :
4d2c1bb72c0344d78d9c3d5958feb3de247102a0
Ali Saidi [Wed, 17 Jan 2007 00:08:21 +0000 (19:08 -0500)]
Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion
Only print TLB if there is a tlb difference
--HG--
extra : convert_revision :
f3baf667ca466d6b8efcaccd186ecec14498229d
Ali Saidi [Wed, 17 Jan 2007 00:06:33 +0000 (19:06 -0500)]
In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision :
e7b21c56eadf4603ab03364741b00c9689492423
Ali Saidi [Wed, 17 Jan 2007 00:06:05 +0000 (19:06 -0500)]
Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last
src/arch/sparc/isa/decoder.isa:
Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
Add IsFirstMicroop flag to static insts
--HG--
extra : convert_revision :
02bea93d38c03bbafe4570665eb4c01c11caa2fc
Lisa Hsu [Thu, 11 Jan 2007 14:48:15 +0000 (09:48 -0500)]
Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge between ali and me.
--HG--
extra : convert_revision :
810d63fb484ab26fc30f8130ef32390ba149b267
Lisa Hsu [Thu, 11 Jan 2007 14:41:34 +0000 (09:41 -0500)]
ua2005.cc:
formatting/indentation for case statements
src/arch/sparc/ua2005.cc:
formatting/indentation for case statements
--HG--
extra : convert_revision :
aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
Lisa Hsu [Thu, 11 Jan 2007 14:29:03 +0000 (09:29 -0500)]
ua2005.cc:
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
src/arch/sparc/ua2005.cc:
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
--HG--
extra : convert_revision :
e66fac9c63088c0fc1a62bd0fac92df305beadff
Lisa Hsu [Thu, 11 Jan 2007 14:18:31 +0000 (09:18 -0500)]
Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision :
74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
Ali Saidi [Thu, 11 Jan 2007 03:19:13 +0000 (22:19 -0500)]
bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
legion always returns du and dl set, so we need to emulate that for now at least
--HG--
extra : convert_revision :
82f9276340888f1e43071c69504486efdcfdb3a8
Ali Saidi [Wed, 10 Jan 2007 03:20:38 +0000 (22:20 -0500)]
quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis
src/arch/sparc/miscregfile.cc:
get rid of some warnings
fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
make warning less verbose
--HG--
extra : convert_revision :
442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
Ali Saidi [Wed, 10 Jan 2007 03:16:49 +0000 (22:16 -0500)]
add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
--HG--
extra : convert_revision :
d8df4a455cf48000042d0ff93a274985f4dbe905
Lisa Hsu [Tue, 9 Jan 2007 01:50:45 +0000 (20:50 -0500)]
pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile
src/arch/alpha/interrupts.hh:
small fix for alpha compile
src/arch/alpha/pagetable.hh:
small fix so ALPHA_FS will build on macs
--HG--
extra : convert_revision :
5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
Lisa Hsu [Mon, 8 Jan 2007 23:18:28 +0000 (18:18 -0500)]
the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
fill in how we do interrupts on sparc a little bit.
1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
2) fill in getInterrupts() a little bit.
also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
1) update formatting
2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.
--HG--
extra : convert_revision :
9074a003eff37a40dcce78f56d20f6cbcc453eb5
Lisa Hsu [Mon, 8 Jan 2007 23:07:17 +0000 (18:07 -0500)]
some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
1) s/Resumeable/Resumable/gc
2) s/if(/if (/gc
3) keep variables lowercase
4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
add bitfield masks for some important ASRs (HPSTATE, PSTATE).
--HG--
extra : convert_revision :
f0ffaf48de298758685266dfb90f43aff42e0a2c
Ali Saidi [Mon, 8 Jan 2007 22:11:10 +0000 (17:11 -0500)]
change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.
--HG--
extra : convert_revision :
f237363eababb2aad67e5b41670cf40be048a042
Ali Saidi [Mon, 8 Jan 2007 22:09:48 +0000 (17:09 -0500)]
fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
fix softint and fprs in miscregfile
--HG--
extra : convert_revision :
cf98bd9c172e20f328f18e07dd05f63f37f14c87
Ali Saidi [Fri, 5 Jan 2007 20:04:17 +0000 (15:04 -0500)]
set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.cc:
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
correct protection defines
src/arch/sparc/ua2005.cc:
set the softint appropriately on an timer compare interrupt
--HG--
extra : convert_revision :
f41c10ec78db973b3f856c70b58a17f83b60bbe2
Ali Saidi [Fri, 5 Jan 2007 01:22:56 +0000 (20:22 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
e8ac13e1222796ab362fabb9b19694682538da29
Ali Saidi [Fri, 5 Jan 2007 01:22:45 +0000 (20:22 -0500)]
Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs
src/arch/sparc/miscregfile.cc:
turn dprintfn into dprintfs
--HG--
extra : convert_revision :
cd313e9037c8f040d837de4c7ddbcf98534e60ad
Nathan Binkert [Wed, 3 Jan 2007 18:16:22 +0000 (10:16 -0800)]
set __name__ in the root m5 script to __m5_main__ so we can
tell if the script is run from m5 as the m5 script
--HG--
extra : convert_revision :
06f646cbb8c82444ef345115aa49324a4d3a2c9f
Nathan Binkert [Wed, 3 Jan 2007 18:13:45 +0000 (10:13 -0800)]
Formatting
--HG--
extra : convert_revision :
bf1eae73995f772a4343c8ebcb254818eeb5d949
Nathan Binkert [Wed, 3 Jan 2007 18:12:55 +0000 (10:12 -0800)]
Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
--HG--
extra : convert_revision :
28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
Kevin Lim [Sat, 30 Dec 2006 18:21:25 +0000 (13:21 -0500)]
Fix up previous commit to proper logic.
src/cpu/o3/commit_impl.hh:
Oops, changed the logic a little bit. Fix it up to how it used to be.
--HG--
extra : convert_revision :
df7f69b0997207b611374c3c92880f3a405e88be
Nathan Binkert [Sat, 30 Dec 2006 00:58:08 +0000 (16:58 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/m5/incoming
--HG--
extra : convert_revision :
dad5311afaaf40c1378017514c8b3f73852f13f5
Nathan Binkert [Sat, 30 Dec 2006 00:57:45 +0000 (16:57 -0800)]
Formatting
--HG--
extra : convert_revision :
f5a940a8b9aaba0703781b398cf29be581907c21
Ali Saidi [Wed, 27 Dec 2006 19:38:22 +0000 (14:38 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
afd4266bd494bb8f127c06985f343219ded4f637
Ali Saidi [Wed, 27 Dec 2006 19:38:07 +0000 (14:38 -0500)]
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
--HG--
extra : convert_revision :
1b5cb3597091e3cfe293e94f6f2219b1e621c35f
Ali Saidi [Wed, 27 Dec 2006 19:35:23 +0000 (14:35 -0500)]
Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads
src/cpu/exetrace.cc:
Compare the legion and m5 tlbs and printout any differences
Only show differences if the instruction isn't a trap and isn't a memory
operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
update the m5<->legion interface to add tlb data
--HG--
extra : convert_revision :
6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
Ali Saidi [Wed, 27 Dec 2006 19:32:26 +0000 (14:32 -0500)]
Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision :
51336fffa5e51a810ad2f6eb29b91c1bfd67824b
Nathan Binkert [Wed, 27 Dec 2006 18:52:25 +0000 (10:52 -0800)]
No need to use NULL, just use 0
The result of operator= cannot be an l-value
--HG--
extra : convert_revision :
df97a57f466e3498bd5a29638cb9912c7f3e1bd4
Kevin Lim [Tue, 26 Dec 2006 06:43:18 +0000 (01:43 -0500)]
Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG--
extra : convert_revision :
5c334ec806305451b3883c7fd0ed9cd695c038bc
Nathan Binkert [Sun, 24 Dec 2006 23:15:12 +0000 (15:15 -0800)]
Make sure that all of the bits in the result are set
to some value.
--HG--
extra : convert_revision :
1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
Nathan Binkert [Sun, 24 Dec 2006 22:06:56 +0000 (14:06 -0800)]
remove some output formatting stuff that we don't use
--HG--
extra : convert_revision :
367917499d3d7aebd0a91dad28c915bc85def624
Nathan Binkert [Sat, 23 Dec 2006 05:51:19 +0000 (21:51 -0800)]
Add options for setting the kernel to run and the
script to run
--HG--
extra : convert_revision :
32ad8e08ca74edf042d8606ca4876cbe1193e932
Nathan Binkert [Fri, 22 Dec 2006 06:41:08 +0000 (22:41 -0800)]
Fix copyright
--HG--
extra : convert_revision :
8ad7824885a5c4da80175c47ba5288aab55b06ca
Nathan Binkert [Fri, 22 Dec 2006 06:38:50 +0000 (22:38 -0800)]
Expose the C++ event queue to python via the python function
m5.internal.event.create(). It takes a python object and a
Tick and calls process() when the Tick occurs.
--HG--
extra : convert_revision :
5e4c9728982b206163ff51e6850a1497d85ad7a3
Nathan Binkert [Fri, 22 Dec 2006 06:34:19 +0000 (22:34 -0800)]
style
--HG--
extra : convert_revision :
6bbaaa88a608081eebf706ff30293f38729415aa
Nathan Binkert [Thu, 21 Dec 2006 23:58:38 +0000 (15:58 -0800)]
Create a wrapper function to more easily add swig stuff to the build
--HG--
extra : convert_revision :
3aaf540a9e314a88a8945579398f0d79aa85d5cf
Nathan Binkert [Thu, 21 Dec 2006 23:49:16 +0000 (15:49 -0800)]
move the swig initialization calls from src/sim/main.cc to
src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.
--HG--
extra : convert_revision :
5cc4ec0838e636aa761901effb8986de58d23e03
Nathan Binkert [Thu, 21 Dec 2006 06:20:11 +0000 (22:20 -0800)]
don't use (*activeThreads).begin(), use activeThreads->blah().
Also don't call (*activeThreads).end() over and over. Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.
--HG--
extra : convert_revision :
d769d8ed52da99532d57a9bbc93e92ddf22b7e58
Nathan Binkert [Thu, 21 Dec 2006 05:46:39 +0000 (21:46 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/m5/incoming
--HG--
extra : convert_revision :
c1724538f27091e16ca495c8fdf2df06f55f7668
Nathan Binkert [Thu, 21 Dec 2006 05:46:16 +0000 (21:46 -0800)]
<scold> Make sure that variables are always initalized! </scold>
--HG--
extra : convert_revision :
1e946d9b1e1def36f9b8a73986dabf1b77096327
Steve Reinhardt [Tue, 19 Dec 2006 07:11:48 +0000 (02:11 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
Ali Saidi [Tue, 19 Dec 2006 07:11:47 +0000 (02:11 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
fa8ce7149973245a73bb562b9378db13be647a14
Ali Saidi [Tue, 19 Dec 2006 07:11:33 +0000 (02:11 -0500)]
fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision :
1e156dead6ebd58b257213625ed63c3793ef4b71
Steve Reinhardt [Tue, 19 Dec 2006 07:07:52 +0000 (23:07 -0800)]
Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.
--HG--
extra : convert_revision :
171018aa6e331d98399c4e5ef24e173c95eaca28
Steve Reinhardt [Tue, 19 Dec 2006 05:53:06 +0000 (21:53 -0800)]
No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision :
56c0b51e424a3a6590332dba4866e69a1ad19598
Steve Reinhardt [Tue, 19 Dec 2006 04:47:12 +0000 (20:47 -0800)]
Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision :
8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
Nathan Binkert [Mon, 18 Dec 2006 22:08:42 +0000 (14:08 -0800)]
Fix unittest compiles
--HG--
extra : convert_revision :
1163437081e1f1eab3f4512d04317dc94a673b9b
Nathan Binkert [Mon, 18 Dec 2006 22:07:52 +0000 (14:07 -0800)]
cast chars to int when we want to print integers so we get a number
instead of a character
--HG--
extra : convert_revision :
7bfa88ba23ad057b751eb01a80416d9f72cfe81a
Ali Saidi [Mon, 18 Dec 2006 08:37:52 +0000 (03:37 -0500)]
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision :
2a44d1c9e4edb627079fc05776c28d918c8508ce
Nathan Binkert [Mon, 18 Dec 2006 02:58:50 +0000 (18:58 -0800)]
Nate's utility for compiling m5
--HG--
extra : convert_revision :
84b21f667736dfe07891323dcc810437ccb3c7c0
Nathan Binkert [Mon, 18 Dec 2006 02:58:05 +0000 (18:58 -0800)]
Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace. For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.
--HG--
extra : convert_revision :
d0591663c028a388635fc71c6c1d31f700748cf6
Gabe Black [Sun, 17 Dec 2006 16:16:04 +0000 (11:16 -0500)]
Compilation fixes.
--HG--
extra : convert_revision :
4932ab507580e0c9f7012398e71921ce58fc3c4e
Gabe Black [Sun, 17 Dec 2006 16:15:37 +0000 (11:15 -0500)]
Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision :
5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
Gabe Black [Sat, 16 Dec 2006 17:55:55 +0000 (12:55 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
c8718b3df72b8c951c24742e8ce517a93bc23fe9
Gabe Black [Sat, 16 Dec 2006 17:55:15 +0000 (12:55 -0500)]
Merge zizzer:/bk/sparcfs/
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
2764b356ef01d1fcb6ed272e4ef96179cd651d4e
Gabe Black [Sat, 16 Dec 2006 17:54:28 +0000 (12:54 -0500)]
Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision :
ad42821a97dcda17744875b1e5dc00a9642e59b7
Gabe Black [Sat, 16 Dec 2006 17:53:01 +0000 (12:53 -0500)]
Compiler error fix.
--HG--
extra : convert_revision :
39e2638a10bf3e821e8f3d4d8c664008c98fc921
Lisa Hsu [Fri, 15 Dec 2006 23:07:39 +0000 (18:07 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a6a40a3bc2e07bc7828de08fa2ce1c847105483d
Lisa Hsu [Fri, 15 Dec 2006 23:02:23 +0000 (18:02 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
Lisa Hsu [Fri, 15 Dec 2006 22:58:20 +0000 (17:58 -0500)]
small change to eliminate address range overlap.
--HG--
extra : convert_revision :
c8309a8774265a707c87c4f516bec1f81aff4a79
Lisa Hsu [Fri, 15 Dec 2006 22:55:47 +0000 (17:55 -0500)]
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
--HG--
extra : convert_revision :
d385521fcfe58f8dffc8622260937e668a47a948
Lisa Hsu [Fri, 15 Dec 2006 18:27:53 +0000 (13:27 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
Lisa Hsu [Fri, 15 Dec 2006 18:06:37 +0000 (13:06 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
92a865a90a7c3e251ed1443f79640f761b359c1d
Lisa Hsu [Fri, 15 Dec 2006 18:05:46 +0000 (13:05 -0500)]
some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision :
c5b9d56ab99018a91d04de47ba1d5ca7768590bb
Lisa Hsu [Fri, 15 Dec 2006 18:01:06 +0000 (13:01 -0500)]
loadstore.isa:
this privilegedString is never used
--HG--
extra : convert_revision :
5e6881d467792b670e0009cee8d5e96bc7a79a95
Lisa Hsu [Fri, 15 Dec 2006 17:58:02 +0000 (12:58 -0500)]
tlb.cc:
fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
--HG--
extra : convert_revision :
327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
Ali Saidi [Fri, 15 Dec 2006 06:49:41 +0000 (01:49 -0500)]
Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision :
ba0a68bd378d68e4ebd80a101b965d36c8be1db9
Ali Saidi [Fri, 15 Dec 2006 06:48:09 +0000 (01:48 -0500)]
Optimized the TLB translations with some caching
--HG--
extra : convert_revision :
f79f863393f918ff9363b2c261f8c0dfec64312e
Ali Saidi [Fri, 15 Dec 2006 00:01:21 +0000 (19:01 -0500)]
flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
--HG--
extra : convert_revision :
1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
Steve Reinhardt [Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)]
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision :
cb1b88246c95b36aa0cf26d534127d3714ddb774
Lisa Hsu [Wed, 13 Dec 2006 22:52:24 +0000 (17:52 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
8cf3e824e4892249b12ed0fd92bb310748b18fa2
Lisa Hsu [Wed, 13 Dec 2006 22:51:28 +0000 (17:51 -0500)]
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision :
4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
Lisa Hsu [Wed, 13 Dec 2006 19:33:59 +0000 (14:33 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
Lisa Hsu [Wed, 13 Dec 2006 19:33:32 +0000 (14:33 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
c6d174716641f0b8286b8478bcb9053b3eec54e3
Lisa Hsu [Wed, 13 Dec 2006 02:19:51 +0000 (21:19 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
6e58629b1e51f1fc493a89f16c3f2e676dc5d191
Kevin Lim [Tue, 12 Dec 2006 22:55:50 +0000 (17:55 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
--HG--
extra : convert_revision :
d420ee86454b72b0e5d3a98bac3b496f172c1788
Ali Saidi [Tue, 12 Dec 2006 22:55:27 +0000 (17:55 -0500)]
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
--HG--
extra : convert_revision :
70604a8b5d0553aa0b0bd7649f775a0cfa8267a5