Tao Zhang [Tue, 8 Jan 2013 13:54:11 +0000 (08:54 -0500)]
sim: Fix early termination in multi-core simulation under SE mode.
When "-I" (maximum instruction number) and "-F" (fastforward instruction
number) are applied together, gem5 immediately exits after the cpu switching.
The reason is that multiple exit events may be generated in the same cycle by
Atomic CPU and inserted to mainEventQueue. However, mainEventQueue can only
serve one exit event in one cycle. Therefore, the rest exit events are left in
mainEventQueue without being descheduled or deleted, which causes gem5 exits
immediately after the system resumes by cpu switching.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)]
arm: add access syscall for ARM SE mode
This patch adds the "access" syscall for ARM SE as required by some spec2006
benchmarks.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)]
mem: Make LL/SC locks fine grained
The current implementation in gem5 just keeps a list of locks per cacheline.
Due to this, a store to a non-overlapping portion of the cacheline can cause an
LL/SC pair to fail. This patch simply adds an address range to the lock
structure, so that the lock is only invalidated if the store overlaps the lock
range.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:06 +0000 (08:54 -0500)]
mem: Fix use-after-free bug
Running with valgrind I noticed a use after free originating from
simple_mem.cc. It looks like this is a known issue and this additional call
site was missed in an earlier patch.
Andreas Sandberg [Mon, 7 Jan 2013 21:56:39 +0000 (16:56 -0500)]
dev: Fix infinite recursion in DMA devices
The DMA device sometimes calls the process() method on a completion
event directly instead of scheduling it on the current tick. This
breaks some devices that assume that the completion handler won't be
called until the current event handler has returned. Specifically, it
causes infinite recursion in the IdeDisk component because it does not
advance its chunk generator until after a dmaRead()/dmaWrite() has
returned. This changeset removes this mico-optimization and schedules
the event in the current tick instead. This way the semantics event
handling stay the same even when the delay is 0.
Andreas Sandberg [Mon, 7 Jan 2013 21:56:37 +0000 (16:56 -0500)]
util: Fix stack corruption in the m5 util
The number of arguments specified when calling parse_int_args() in
do_exit() is incorrect. This leads to stack corruption since it causes
writes past the end of the ints array.
Sascha Bischoff [Mon, 7 Jan 2013 21:56:36 +0000 (16:56 -0500)]
stats: Fix swig wrapping for Tick in stats
Tick was not correctly wrapped for the stats system, and therefore it was not
possible to configure the stats dumping from the python scripts without
defining Ticks as long long. This patch fixes the wrapping of Tick by copying
the typemap of uint64_t to Tick.
Ali Saidi [Mon, 7 Jan 2013 18:05:54 +0000 (13:05 -0500)]
stats: update stats for previous changes.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:52 +0000 (13:05 -0500)]
cpu: Unify the serialization code for all of the CPU models
Cleanup the serialization code for the simple CPUs and the O3 CPU. The
CPU-specific code has been replaced with a (un)serializeThread that
serializes the thread state / context of a specific thread. Assuming
that the thread state class uses the CPU-specific thread state uses
the base thread state serialization code, this allows us to restore a
checkpoint with any of the CPU models.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:52 +0000 (13:05 -0500)]
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:48 +0000 (13:05 -0500)]
cpu: Flush TLBs on switchOut()
This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching. Additionally, the
TLB flushing functionality is exported to the Python to make debugging
of switching/checkpointing easier.
A simulation script will typically use the TLB flushing functionality
to generate a reference trace. The following sequence can be used to
simulate a handover (this depends on how drain is implemented, but is
generally the case) between identically configured CPU models:
m5.drain(test_sys)
[ cpu.flushTLBs() for cpu in test_sys.cpu ]
m5.resume(test_sys)
The generated trace should normally be identical to a trace generated
when switching between identically configured CPU models or
checkpointing and resuming.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:47 +0000 (13:05 -0500)]
mem: Fix guest corruption when caches handle uncacheable accesses
When the classic gem5 cache sees an uncacheable memory access, it used
to ignore it or silently drop the cache line in case of a
write. Normally, there shouldn't be any data in the cache belonging to
an uncacheable address range. However, since some architecture models
don't implement cache maintenance instructions, there might be some
dirty data in the cache that is discarded when this happens. The
reason it has mostly worked before is because such cache lines were
most likely evicted by normal memory activity before a TLB flush was
requested by the OS.
Previously, the cache model would invalidate cache lines when they
were accessed by an uncacheable write. This changeset alters this
behavior so all uncacheable memory accesses cause a cache flush with
an associated writeback if necessary. This is implemented by reusing
the cache flushing machinery used when draining the cache, which
implies that writebacks are performed using functional accesses.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Rewrite O3 draining to avoid stopping in microcode
Previously, the O3 CPU could stop in the middle of a microcode
sequence. This patch makes sure that the pipeline stops when it has
committed a normal instruction or exited from a microcode
sequence. Additionally, it makes sure that the pipeline has no
instructions in flight when it is drained, which should make draining
more robust.
Draining is controlled in the commit stage, which checks if the next
PC after a committed instruction is in microcode. If this isn't the
case, it requests a squash of all instructions after that the
instruction that just committed and immediately signals a drain stall
to the fetch stage. The CPU then continues to execute until the
pipeline and all associated buffers are empty.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Make sure that a drained atomic CPU isn't executing ucode
Currently, the atomic CPU can be in the middle of a microcode sequence
when it is drained. This leads to two problems:
* When switching to a hardware virtualized CPU, we obviously can't
execute gem5 microcode.
* Since curMacroStaticInst is populated when executing microcode,
repeated switching between CPUs executing microcode leads to
incorrect execution.
After applying this patch, the CPU will be on a proper instruction
boundary, which means that it is safe to switch to any CPU model
(including hardware virtualized ones). This changeset fixes a bug
where the multiple switches to the same atomic CPU sometimes corrupts
the target state because of dangling pointers to the currently
executing microinstruction.
Note: This changeset moves tick event descheduling from switchOut() to
drain(), which makes timing consistent between just draining a system
and draining /and/ switching between two atomic CPUs. This makes
debugging quite a lot easier (execution traces get the same timing),
but the latency of the last instruction before a drain will not be
accounted for correctly (it will always be 1 cycle).
Note 2: This changeset removes so_state variable, the locked variable,
and the tickEvent from checkpoints since none of them contain state
that needs to be preserved across checkpoints. The so_state is made
redundant because we don't use the drain state variable anymore, the
lock variable should never be set when the system is drained, and the
tick event isn't scheduled.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Make sure that a drained timing CPU isn't executing ucode
Currently, the timing CPU can be in the middle of a microcode sequence
or multicycle (stayAtPC is true) instruction when it is drained. This
leads to two problems:
* When switching to a hardware virtualized CPU, we obviously can't
execute gem5 microcode.
* If stayAtPC is true we might execute half of an instruction twice
when restoring a checkpoint or switching CPUs, which leads to an
incorrect execution.
After applying this patch, the CPU will be on a proper instruction
boundary, which means that it is safe to switch to any CPU model
(including hardware virtualized ones). This changeset also fixes a bug
where the timing CPU sometimes switches out with while stayAtPC is
true, which corrupts the target state after a CPU switch or
checkpoint.
Note: This changeset removes the so_state variable from checkpoints
since the drain state isn't used anymore.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Fix broken thread context handover
The thread context handover code used to break when multiple handovers
were performed during the same quiesce period. Previously, the thread
contexts would assign the TC pointer in the old quiesce event to the
new TC. This obviously broke in cases where multiple switches were
performed within the same quiesce period, in which case the TC pointer
in the quiesce event would point to an old CPU.
The new implementation deschedules pending quiesce events in the old
TC and schedules a new quiesce event in the new TC. The code has been
refactored to remove most of the code duplication.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Fix O3 LSQ debug dumping constness and formatting
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
arm: Invalidate cached TLB configuration in drainResume
Currently, we invalidate the cached miscregs in
TLB::unserialize(). The intended use of the drainResume() method is to
invalidate cached state and prepare the system to resume after a CPU
handover or (un)serialization. This patch moves the TLB miscregs
invalidation code to the drainResume() method to avoid surprising
behavior.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
arm: Fix draining of the pagetable walker when squashing
Since the page table walker only checks if a drain has completed in
doL1DescriptorWrapper() and doL2DescriptorWrapper(), it sometimes
looses track of a drain request if there is a squash. This changeset
adds a completeDrain() call after squashing requests in the pending
queue, which fixes this issue.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
cpu: Fix broken squashAfter implementation in O3 CPU
Commit can currently both commit and squash in the same cycle. This
confuses other stages since the signals coming from the commit stage
can only signal either a squash or a commit in a cycle. This changeset
changes the behavior of squashAfter so that it commits all
instructions, including the instruction that requested the squash, in
the first cycle and then starts to squash in the next cycle.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
o3 cpu: Remove unused variables
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
tests: Update the ignore regexps to reflect the M5->gem5 name change
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
sim: Remove unused variables
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
cpu: Rename defer_registration->switched_out
The defer_registration parameter is used to prevent a CPU from
initializing at startup, leaving it in the "switched out" mode. The
name of this parameter (and the help string) is confusing. This patch
renames it to switched_out, which should be more descriptive.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
cpu: Remove unused params.hh header file in inorder CPU
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the
ARM architecture model uses the magic MISCREG_CPSR_MODE register to
change the register mappings without actually updating the CPU
mode. This hack is no longer needed since the thread context now
provides a flat interface to the register file. This patch replaces
the CPSR_MODE hack with the flat register interface.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
cpu: Introduce sanity checks when switching between CPUs
This patch introduces the following sanity checks when switching
between CPUs:
* Check that the set of new and old CPUs do not overlap. Having an
overlap between the set of new CPUs and the set of old CPUs is
currently not supported. Doing such a switch used to result in the
following assertion error:
BaseCPU::takeOverFrom(BaseCPU*): \
Assertion `!new_itb_port->isConnected()' failed.
* Check that all new CPUs are in the switched out state.
* Check that all old CPUs are in the switched in state.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
cpu: Correctly call parent on switchOut() and takeOverFrom()
This patch cleans up the CPU switching functionality by making sure
that CPU models consistently call the parent on switchOut() and
takeOverFrom(). This has the following implications that might alter
current functionality:
* The call to BaseCPU::switchout() in the O3 CPU is moved from
signalDrained() (!) to switchOut().
* A call to BaseSimpleCPU::switchOut() is introduced in the simple
CPUs.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
cpu: Unify SimpleCPU and O3 CPU serialization code
The O3 CPU used to copy its thread context to a SimpleThread in order
to do serialization. This was a bit of a hack involving two static
SimpleThread instances and a magic constructor that was only used by
the O3 CPU.
This patch moves the ThreadContext serialization code into two global
procedures that, in addition to the normal serialization parameters,
take a ThreadContext reference as a parameter. This allows us to reuse
the serialization code in all ThreadContext implementations.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
cpu: Initialize the O3 pipeline from startup()
The entire O3 pipeline used to be initialized from init(), which is
called before initState() or unserialize(). This causes the pipeline
to be initialized from an incorrect thread context. This doesn't
currently lead to correctness problems as instructions fetched from
the incorrect start PC will be squashed a few cycles after
initialization.
This patch will affect the regressions since the O3 CPU now issues its
first instruction fetch to the correct PC instead of 0x0.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:44 +0000 (13:05 -0500)]
cpu: Implement a flat register interface in thread contexts
Some architectures map registers differently depending on their mode
of operations. There is currently no architecture independent way of
accessing all registers. This patch introduces a flat register
interface to the ThreadContext class. This interface is useful, for
example, when serializing or copying thread contexts.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:42 +0000 (13:05 -0500)]
arch: Move the ISA object to a separate section
After making the ISA an independent SimObject, it is serialized
automatically by the Python world. Previously, this just resulted in
an empty ISA section. This patch moves the contents of the ISA to that
section and removes the explicit ISA serialization from the thread
contexts, which makes it behave like a normal SimObject during
serialization.
Note: This patch breaks checkpoint backwards compatibility! Use the
cpt_upgrader.py utility to upgrade old checkpoints to the new format.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:41 +0000 (13:05 -0500)]
cpu: Check that the memory system is in the correct mode
This patch adds checks to all CPU models to make sure that the memory
system is in the correct mode at startup and when resuming after a
drain. Previously, we only checked that the memory system was in the
right mode when resuming. This is inadequate since this is a
configuration error that should be detected at startup as well as when
resuming. Additionally, since the check was done using an assert, it
wasn't performed when NDEBUG was set (e.g., the fast target).
Andreas Sandberg [Mon, 7 Jan 2013 18:05:40 +0000 (13:05 -0500)]
arch: Add support for invalidating TLBs when draining
This patch adds support for the memInvalidate() drain method. TLB
flushing is requested by calling the virtual flushAll() method on the
TLB.
Note: This patch renames invalidateAll() to flushAll() on x86 and
SPARC to make the interface consistent across all supported
architectures.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
mem: Remove the IIC replacement policy
The IIC replacement policy seems to be unused and has probably
gathered too much bit rot to be useful. This patch removes the IIC and
its associated cache parameters.
Andreas Hansson [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
dev: Do not serialize timer parameters
This patch removes the intNum and clock from the serialized scalars as
these are set by the Python parameters and should not be part of the
checkpoint.
Andreas Hansson [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x support
This patch checks that the compiler in use is either gcc >= 4.4 or
clang >= 2.9. and enables building with --std=c++0x in all cases. As a
consequence, we can tidy up the hashmap and always have static_assert
available. If anyone wants to use alternative compilers, icc for
example supports c++0x to a similar level and could be added if
needed.
This patch opens up for a more elaborate use of c++0x features that
are present in gcc 4.4 and clang 2.9, e.g. auto typed variables,
variadic templates, rvalues and move semantics, and strongly typed
enums. There will be no going back on this one...
Andreas Hansson [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
scons: Remove stale compiler options
This patch simply prunes the SUNCC and ICC compiler options as they
are both sufficiently stale that they would have to be re-written from
scratch anyhow. The patch serves to clean things up before shifting to
a build environment that enforces basic c++11 compliance as done in
the following patch.
Andreas Hansson [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
sim: Fatal if a clocked object is set to have a clock of 0
This patch adds a check to the clocked object constructor to ensure it
is not configured to have a clock period of 0.
Andreas Hansson [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
dev: Make the ethernet devices use a non-zero clock
This patch changes the NS gige controller to have a non-clock, and
sets the default to 500 MHz. The blocks that could prevoiusly be
by-passed with a zero clock are now always present, and the user is
left with the option of setting a very high clock frequency to achieve
a similar performance.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
scons: Whitelist useful environment variables
Scons normally removes all environment variables that aren't
whitelisted from the build environment. This messes up things like
ccache, distcc, and the clang static analyzer. This changeset adds the
DISTCC_, CCACHE_, and CCC_ prefixes to the environment variable
whitelist.
Chander Sudanthi [Mon, 7 Jan 2013 18:05:39 +0000 (13:05 -0500)]
ARM: pl111/LCD framebuffer checkpointing fix
Fixed check pointing of the framebuffer. Previously, the pixel size was not
considered in determining the size of the buffer to checkpoint. This patch
checkpoints the entire framebuffer instead of the first quarter.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
arch: Fix broken M5VarArgsFault initialization
At least gcc 4.4.3 seems to get confused by the use of func both as a
template parameter and a member variable in the M5VarArgsFault
class. This causes the value of the member variable func to be
unpredictable in M5VarArgsFault objects. This changeset renames the
template parameter to remove this ambiguity.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
mem: Merge ranges that are part of the conf table
This patch adds basic merging of address ranges when determining which
address ranges should be reported in the configuration table. By
performing this merging it is possible to distribute an address range
across many memory channels (controllers). This is essential to enable
address interleaving.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
base: Add support for merging of interleaved address ranges
This patch adds support for merging a vector of interleaved address
ranges into a contigous range. The functionality will be used in the
interconnect and the PhysicalMemory to transform interleaved memory
ranges to contigous ranges before passing them on.
The actual use of the merging is appearing in future patches.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
mem: Add interleaving bits to the address ranges
This patch adds support for interleaving bits for the address
ranges. What was previously just a start and end address, now has an
additional three fields, for the high bit, and number of bits to use
for interleaving, and a match value to compare against. If the number
of interleaving bits is set to zero it is effectively disabled.
A number of convenience functions are added to the range to enquire
about the interleaving, its granularity and the number of stripes it
is part of.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
config: Traverse lists when visiting children in all proxy
This patch makes the all proxy traverse any potential list that is
encountered in the object hierarchy instead of only looking at
children that are SimObjects. An example of where this is useful is
when creating a multi-channel memory system as a list of controllers,
whilst ensuring that the memories are still visible in the system.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
base: Simplify the AddrRangeMap by removing unused code
This patch cleans up the AddrRangeMap in preparation for the addition
of interleaving by removing unused code. The non-const editions of
find are never used, and hence the duplication is not needed.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.
The change is needed to allow interleaved memory controllers in the
system.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
mem: Tidy up bus addr range debug messages
This patch tidies up a number of the bus DPRINTFs related to range
manipulation. In particular, it shifts the message about range changes
to the start of the member function, and also adds information about
when all ranges are received.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
mem: Skip address mapper range checks to allow more flexibility
This patch makes the address mapper less stringent about checking the
before and after ranges, i.e. the original and remapped ranges. The
checks were not really necessary, and there are situations when the
previous checks were too strict.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
base: Encapsulate the underlying fields in AddrRange
This patch makes the start and end address private in a move to
prevent direct manipulation and matching of ranges based on these
fields. This is done so that a transition to ranges with interleaving
support is possible.
As a result of hiding the start and end, a number of member functions
are needed to perform the comparisons and manipulations that
previously took place directly on the members. An accessor function is
provided for the start address, and a function is added to test if an
address is within a range. As a result of the latter the != and ==
operator is also removed in favour of the member function. A member
function that returns a string representation is also created to allow
debug printing.
In general, this patch does not add any functionality, but it does
take us closer to a situation where interleaving (and more cleverness)
can be added under the bonnet without exposing it to the user. More on
that in a later patch.
Andreas Hansson [Mon, 7 Jan 2013 18:05:38 +0000 (13:05 -0500)]
mem: Remove the joining of neighbouring ranges
This patch temporarily removes the joining of ranges when creating the
backing store, to reserve this functionality for the interleaved
ranges that are about to be introduced.
When creating the mmaps for the backing store, there is no point in
creating larger contigous chunks that what is necessary. The larger
chunks will only make life more difficult for the host.
Merging will be re-added later, but then only for interleaved ranges.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
cpu: Share the send functionality between traffic generators
This patch moves the packet creating and sending to a member function
in the shared base class to avoid code duplication.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
cpu: Add support for protobuf input for the trace generator
This patch adds support for reading input traces encoded using
protobuf according to what is done in the CommMonitor.
A follow-up patch adds a Python script that can be used to convert the
previously used ASCII traces to protobuf equivalents. The appropriate
regression input is updated as part of this patch.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
tests: Add support for skipping tests, skip EIO tests if not enabled
The EIO tests depend on the EIO support from the "encumbered"
repository, which means that they are not normally built with
gem5. This causes all EIO related tests to fail, which is both
annoying and confusing. This patch addresses this by adding support
for skipping tests if certain conditions (e.g., the presence of a
SimObject) can not be met. It introduces the following Python
functions that can be called from within a test case:
* skip_test -- Skip a test and optionally print why the test was
skipped.
* has_sim_object -- Test if a SimObject exists.
* require_sim_object -- Test if a SimObject exists and skip, or
optionally fail, the test if not.
Additionally, this patch updates the EIO tests to check for the
presence of EioProcess.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
cpu: Encapsulate traffic generator input in a stream
This patch encapsulates the traffic generator input in a stream class
such that the parsing is not visible to the trace generator. The
change takes us one step closer to using protobuf-based input traces
for the trace replay.
The functionality of the current input stream is identical to what it
was, and the ASCII format remains the same for now.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
base: Add wrapped protobuf input stream
This patch adds support for inputting protobuf messages through a
ProtoInputStream which hides the internal streams used by the
library. The stream is created based on the name of an input file and
optionally includes decompression using gzip.
The input stream will start by getting a magic number from the file,
and also verify that it matches with the expected value. Once opened,
messages can be read incrementally from the stream, returning
true/false until an error occurs or the end of the file is reached.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
mem: Add tracing support in the communication monitor
This patch adds packet tracing to the communication monitor using a
protobuf as the mechanism for creating the trace.
If no file is specified, then the tracing is disabled. If a file is
specified, then for every packet that is successfully sent, a protobuf
message is serialized to the file.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
base: Add wrapped protobuf output streams
This patch adds support for outputting protobuf messages through a
ProtoOutputStream which hides the internal streams used by the
library. The stream is created based on the name of an output file and
optionally includes compression using gzip.
The output stream will start by putting a magic number in the file,
and then for every message that is serialized prepend the size such
that the stream can be written and read incrementally. At this point
this merely serves as a proof of concept.
Andreas Hansson [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
scons: Add support for google protobuf building
This patch enables the use of protobuf input files in the build
process, thus allowing .proto files to be added to input. Each .proto
file is compiled using the protoc tool and the newly created C++
source is added to the list of sources.
The first location where the protobufs will be used is in the
capturing and replay of memory traces, involving the communication
monitor and the trace-generator state of the traffic generator. This
will follow in the next patch.
This patch does add a dependency on the availability of the BSD
licensed protobuf library (and headers), and the protobuf compiler,
protoc. These dependencies are checked in the SConstruct, similar to
e.g. swig. The user can override the use of protoc from the PATH by
specifying the PROTOC environment variable.
Although the dependency on libprotobuf and protoc might seem like a
big step, they add significant value to the project going
forward. Execution traces and other types of traces could easily be
added and parsers for C++ and Python are automatically generated. We
could also envision using protobufs for the checkpoints, description
of the traffic-generator behaviour etc. The sky is the limit. We could
also use the GzipOutputStream from the protobuf library instead of the
current GPL gzstream.
Currently, only the C++ source and header is generated. Going forward
we might want to add the Python output to support simple command-line
tools for displaying and editing the traces.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:37 +0000 (13:05 -0500)]
arm: Fix DMA event handling bug in the PL111 model
The PL111 model currently maintains a list of pre-allocated
DmaDoneEvents to prevent unnecessary heap allocations. This list
effectively works like a stack where the top element is the latest
scheduled event. When an event triggers, the top pointer is moved down
the stack. This obviously breaks since events usually retire from the
bottom (events don't necessarily have to retire in order), which
triggers the following assertion:
gem5.debug: build/ARM/dev/arm/pl111.cc:460: void Pl111::fillFifo(): \
Assertion `!dmaDoneEvent[dmaPendingNum-1].scheduled()' failed.
This changeset adds a vector listing the currently unused events. This
vector acts like a stack where the an element is popped off the stack
when a new event is needed an pushed on the stack when they trigger.
Andreas Hansson [Mon, 7 Jan 2013 18:05:36 +0000 (13:05 -0500)]
dev: Fix the Pl111 timings by separating pixel and DMA clock
This patch fixes the Pl111 timings by creating a separate clock for
the pixel timings. The device clock is used for all interactions with
the memory system, just like the AHB clock on the actual module.
The result without this patch is that the module only is allowed to
send one request every tick of the 24MHz clock which causes a huge
backlog.
Andreas Hansson [Mon, 7 Jan 2013 18:05:36 +0000 (13:05 -0500)]
stats: Update DRAM regression stats to match new config
This patch updates the regression stats to reflect the change in the
traffic gen configuration.
Andreas Hansson [Mon, 7 Jan 2013 18:05:36 +0000 (13:05 -0500)]
config: Reduce DRAM controller regression traffic rate
This patch changes the traffic generator period such that it does not
completely saturate the DRAM controller and create an ever-growing
backlog in the queued port.
A separate patch updates the stats.
Andreas Hansson [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
cpu: Fix the traffic gen read percentage
This patch fixes the computation that determines whether to perform a
read or a write such that the two corner cases (0 and 100) are both
more efficient and handled correctly.
Andreas Hansson [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
mem: Add sanity check to packet queue size
This patch adds a basic check to ensure that the packet queue does not
grow absurdly large. The queue should only be used to store packets
that were delayed due to blocking from the neighbouring port, and not
for actual storage. Thus, a limit of 100 has been chosen for now
(which is already quite substantial).
Andreas Hansson [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
ruby: Fix missing cxx_header in Switch
This patch addresses a warning related to the swig interface
generation for the Switch class. The cxx_header is now specified
correctly, and the header in question has got a few includes added to
make it all compile.
Andreas Hansson [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
scons: Fix libelf linking errors when using clang/llvm
This patch fixes a linking error that occurs when using clang/llvm in
combination with older versions of glibc. The fix involves adding
-std=gnu89 to the command line when compiling libelf as clang defaults
to c99, causing issues with the symbols in sysmacros.h being defined
multiple times.
Chris Emmons [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
config: Replace second keyboard with a mouse.
The platform has two KMI devices that are both setup to be keyboards. This
patch changes the second keyboard to a mouse. This patch will allow keyboard
input as usual and additionally provide mouse support.
Andreas Hansson [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
mem: Fix a bug in the memory serialization file naming
This patch fixes a bug that caused multiple systems to overwrite each
other physical memory. The system name is now included in the filename
such that this is avoided.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable
as ISA parameter values. Additionally, setMiscReg now ignores writes
to all of the ID registers.
Note: This moves the MIDR parameter from ArmSystem to ArmISA for
consistency.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:35 +0000 (13:05 -0500)]
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
Ali Saidi [Mon, 7 Jan 2013 18:05:33 +0000 (13:05 -0500)]
o3: Fix issue with LLSC ordering and speculation
This patch unlocks the cpu-local monitor when the CPU sees a snoop to a locked
address. Previously we relied on the cache to handle the locking for us, however
some users on the gem5 mailing list reported a case where the cpu speculatively
executes a ll operation after a pending sc operation in the pipeline and that
makes the cache monitor valid. This should handle that case by invaliding the
local monitor.
Ali Saidi [Mon, 7 Jan 2013 18:05:33 +0000 (13:05 -0500)]
cpu: rename the misleading inSyscall to noSquashFromTC
isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
Ali Saidi [Mon, 7 Jan 2013 18:05:33 +0000 (13:05 -0500)]
tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:33 +0000 (13:05 -0500)]
tests: Create base classes to encapsulate common test configurations
Most of the test cases currently contain a large amount of duplicated
boiler plate code. This changeset introduces a set of classes that
encapsulates most of the functionality when setting up a test
configuration.
The following base classes are introduced:
* BaseSystem - Basic system configuration that can be used for both
SE and FS simulation.
* BaseFSSystem - Basic FS configuration uni-processor and multi-processor
configurations.
* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor
configurations. This is provided as a way
to make existing test cases backwards
compatible.
Architecture specific implementations are provided for ARM, Alpha, and
X86.
Ali Saidi [Mon, 7 Jan 2013 18:05:32 +0000 (13:05 -0500)]
cache: add note about where conflicts are handled
Nilay Vaish [Sat, 5 Jan 2013 01:00:48 +0000 (19:00 -0600)]
regressions: stats update due to decoder changes
Gabe Black [Sat, 5 Jan 2013 01:00:45 +0000 (19:00 -0600)]
Decoder: Remove the thread context get/set from the decoder.
This interface is no longer used, and getting rid of it simplifies the
decoders and code that sets up the decoders. The thread context had been used
to read architectural state which was used to contextualize the instruction
memory as it came in. That was changed so that the state is now sent to the
decoders to keep locally if/when it changes. That's significantly more
efficient.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Gabe Black [Sat, 5 Jan 2013 01:00:44 +0000 (19:00 -0600)]
X86: Move address based decode caching in front of the predecoder.
The predecoder in x86 does a lot of work, most of which can be skipped if the
decoder cache is put in front of it.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Gabe Black [Sat, 5 Jan 2013 00:09:45 +0000 (18:09 -0600)]
SPARC: Keep a copy of the current ASI in the decoder.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Gabe Black [Sat, 5 Jan 2013 00:09:35 +0000 (18:09 -0600)]
ARM: Keep a copy of the fpscr len and stride fields in the decoder.
Avoid reading them every instruction, and also eliminate the last use of the
thread context in the decoders.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sun, 30 Dec 2012 18:45:52 +0000 (12:45 -0600)]
x86 regressions: stats update due to new x87 instructions
Nilay Vaish [Sun, 30 Dec 2012 18:45:50 +0000 (12:45 -0600)]
x86: implement x87 fp instruction fnstsw
This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.
Nilay Vaish [Sun, 30 Dec 2012 18:45:45 +0000 (12:45 -0600)]
x86: implement x87 fp instruction fsincos
This patch implements the fsincos instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.
Nilay Vaish [Wed, 12 Dec 2012 15:51:55 +0000 (09:51 -0600)]
arm regressions: updates to config.ini, terminal files
Nathanael Premillieu [Wed, 12 Dec 2012 15:50:33 +0000 (09:50 -0600)]
arm: set uopSet_uop as conditional or unconditional control
uopSet_uop is microop instruction that has the IsControl flags set, but the
IsCondControl or IsUncondControl flags seems not to be set, neither in
the construction nor where the microop is used. This patch adds the the
flags in the constructor of the instruction (MicroUopSetPCCPSR).
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nathanael Premillieu [Wed, 12 Dec 2012 15:50:16 +0000 (09:50 -0600)]
arm: set movret_uop as conditional or unconditional control
A flag was missing for the movret_uop microop instruction. This patch adds
that flag when the instruction is used, not directly in the constructor of
the instruction.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 11 Dec 2012 16:06:01 +0000 (10:06 -0600)]
regressions: stats update due to stats from ruby prefetcher
Nilay Vaish [Tue, 11 Dec 2012 16:05:56 +0000 (10:05 -0600)]
ruby: add support for prefetching to MESI protocol
Nilay Vaish [Tue, 11 Dec 2012 16:05:55 +0000 (10:05 -0600)]
ruby: modify the directed tester to read/write streams
The directed tester supports only generating only read or only write accesses. The
patch modifies the tester to support streams that have both read and write accesses.
Nilay Vaish [Tue, 11 Dec 2012 16:05:55 +0000 (10:05 -0600)]
ruby: change slicc to allow for constructor args
The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.
Nilay Vaish [Tue, 11 Dec 2012 16:05:54 +0000 (10:05 -0600)]
ruby: add a prefetcher
This patch adds a prefetcher for the ruby memory system. The prefetcher
is based on a prefetcher implemented by others (well, I don't know
who wrote the original). The prefetcher does stride-based prefetching,
both unit and non-unit. It obseves the misses in the cache and trains on
these. After the training period is over, the prefetcher starts issuing
prefetch requests to the controller.
Nilay Vaish [Tue, 11 Dec 2012 16:05:53 +0000 (10:05 -0600)]
ruby: add functions for computing next stride/page address
Nilay Vaish [Thu, 6 Dec 2012 16:26:12 +0000 (10:26 -0600)]
regression test: update a couple of config.ini files
Erik Tomusk [Thu, 6 Dec 2012 15:31:06 +0000 (09:31 -0600)]
TournamentBP: Fix some bugs with table sizes and counters
globalHistoryBits, globalPredictorSize, and choicePredictorSize are decoupled.
globalHistoryBits controls how much history is kept, global and choice
predictor sizes control how much of that history is used when accessing
predictor tables. This way, global and choice predictors can actually be
different sizes, and it is no longer possible to walk off the predictor arrays
and cause a seg fault.
There are now individual thresholds for choice, global, and local saturating
counters, so that taken/not taken decisions are correct even when the
predictors' counters' sizes are different.
The interface for localPredictorSize has been removed from TournamentBP because
the value can be calculated from localHistoryBits.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Malek Musleh [Thu, 6 Dec 2012 11:25:40 +0000 (05:25 -0600)]
inorder cpu: add missing DPRINTF argument
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nathanael Premillieu [Thu, 6 Dec 2012 10:36:51 +0000 (04:36 -0600)]
o3 cpu: remove some unused buggy functions in the lsq
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andreas Hansson [Mon, 19 Nov 2012 16:21:09 +0000 (11:21 -0500)]
config: Fix description of checkpoint option from cycle to tick
This patch merely updates the description of the "take-checkpoints"
option to reflect that it is specified in ticks and not in cycles.