Yehowshua [Tue, 5 May 2020 05:20:01 +0000 (06:20 +0100)]
Add getting started instruction. A bit redundant, but I think it makes sense.
Yehowshua [Tue, 5 May 2020 05:03:02 +0000 (06:03 +0100)]
Yehowshua [Tue, 5 May 2020 05:02:19 +0000 (06:02 +0100)]
Link to SOC Documentation
Yehowshua [Tue, 5 May 2020 05:01:19 +0000 (06:01 +0100)]
Yehowshua [Tue, 5 May 2020 04:51:38 +0000 (05:51 +0100)]
Add Link To Documentation
Yehowshua [Tue, 5 May 2020 04:50:19 +0000 (05:50 +0100)]
Yehowshua [Tue, 5 May 2020 04:49:20 +0000 (05:49 +0100)]
Michael Nolan [Tue, 5 May 2020 02:48:29 +0000 (22:48 -0400)]
Revert ""
This reverts commit
d238c6db23b9a250f6d5150533ebe053227161c0.
Revert Yehowshua's commits at his request
Michael Nolan [Tue, 5 May 2020 02:47:51 +0000 (22:47 -0400)]
Revert ""
This reverts commit
c1e27ffa722c0450bbae843c1cf5e86ccdf758fa.
Revert Yehowshua's commits at his request
Michael Nolan [Tue, 5 May 2020 02:47:38 +0000 (22:47 -0400)]
Revert ""
This reverts commit
a309f4427c2ce1ebd1892ff8ea04adb083998834.
Revert Yehowshua's commits at his request
Michael Nolan [Tue, 5 May 2020 02:47:22 +0000 (22:47 -0400)]
Revert ""
This reverts commit
cc43959e87b0a36294ca9ea9df2b38d32515264f.
Revert Yehowshua's commits at his request
Yehowshua [Tue, 5 May 2020 00:39:24 +0000 (01:39 +0100)]
Yehowshua [Tue, 5 May 2020 00:38:19 +0000 (01:38 +0100)]
Yehowshua [Tue, 5 May 2020 00:34:51 +0000 (01:34 +0100)]
Yehowshua [Tue, 5 May 2020 00:19:21 +0000 (01:19 +0100)]
lkcl [Mon, 4 May 2020 21:18:25 +0000 (22:18 +0100)]
lkcl [Mon, 4 May 2020 21:07:31 +0000 (22:07 +0100)]
lkcl [Mon, 4 May 2020 17:28:56 +0000 (18:28 +0100)]
Yehowshua [Mon, 4 May 2020 15:29:56 +0000 (16:29 +0100)]
Yehowshua [Mon, 4 May 2020 14:25:40 +0000 (15:25 +0100)]
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:15:02 +0000 (09:15 +0100)]
clarify see how can i learn
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:14:04 +0000 (09:14 +0100)]
split out developer how-can-i-help, also reference coriolis2 page
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:09:32 +0000 (09:09 +0100)]
update priorities
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:02:42 +0000 (09:02 +0100)]
linebreak
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:02:11 +0000 (09:02 +0100)]
missed two brs
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:01:45 +0000 (09:01 +0100)]
move example to separate section, cleanup HTML
Yehowshua [Mon, 4 May 2020 01:25:25 +0000 (02:25 +0100)]
Yehowshua [Mon, 4 May 2020 00:12:04 +0000 (01:12 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:33:12 +0000 (23:33 +0100)]
describe concurrent computational unit
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:16:14 +0000 (23:16 +0100)]
correct image name
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:15:33 +0000 (23:15 +0100)]
add FU-FU and FU-Regs vectors
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:53:00 +0000 (22:53 +0100)]
add additional images
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:31:03 +0000 (22:31 +0100)]
whitespace
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:29:40 +0000 (22:29 +0100)]
whitespace
lkcl [Sun, 3 May 2020 21:26:54 +0000 (22:26 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:59:20 +0000 (15:59 +0100)]
mention concurrent units, update regfile image to double-up the pipelines
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:06:03 +0000 (15:06 +0100)]
mention that the 4x4 crossbar is a major data bottleneck
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:00:51 +0000 (15:00 +0100)]
update diagram and include text on regfile arrangement
lkcl [Sun, 3 May 2020 13:21:23 +0000 (14:21 +0100)]
lkcl [Sun, 3 May 2020 13:21:01 +0000 (14:21 +0100)]
lkcl [Sun, 3 May 2020 13:20:43 +0000 (14:20 +0100)]
lkcl [Sun, 3 May 2020 13:18:00 +0000 (14:18 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 13:16:41 +0000 (14:16 +0100)]
add regfile diagram
Luke Kenneth Casson Leighton [Sun, 3 May 2020 13:16:28 +0000 (14:16 +0100)]
add walkthrough video for memory and cache
Yehowshua [Sat, 2 May 2020 19:29:33 +0000 (20:29 +0100)]
Yehowshua [Sat, 2 May 2020 06:10:43 +0000 (07:10 +0100)]
Luke Kenneth Casson Leighton [Fri, 1 May 2020 11:18:46 +0000 (12:18 +0100)]
whitespace
programmerjake [Fri, 1 May 2020 02:45:07 +0000 (03:45 +0100)]
add load-store unit ideas
programmerjake [Fri, 1 May 2020 00:40:37 +0000 (01:40 +0100)]
add prefix sum
lkcl [Thu, 30 Apr 2020 18:56:58 +0000 (19:56 +0100)]
Luke Kenneth Casson Leighton [Thu, 30 Apr 2020 17:30:23 +0000 (18:30 +0100)]
add walk-through videos for LD/ST CompUnit
Luke Kenneth Casson Leighton [Thu, 30 Apr 2020 17:23:16 +0000 (18:23 +0100)]
update new version of LD/ST which can do "update" mode and indexed
lkcl [Wed, 29 Apr 2020 14:07:54 +0000 (15:07 +0100)]
lkcl [Wed, 29 Apr 2020 09:03:07 +0000 (10:03 +0100)]
lkcl [Wed, 29 Apr 2020 09:02:22 +0000 (10:02 +0100)]
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 22:28:29 +0000 (23:28 +0100)]
update wr-any signal in ldstcomp
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 17:06:51 +0000 (18:06 +0100)]
update ld/st diagram to deal with ST-with-update
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 16:20:54 +0000 (17:20 +0100)]
missing signals on SR Latches
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:36:52 +0000 (16:36 +0100)]
add discussion links for LD/ST Comp Unit
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:29:09 +0000 (16:29 +0100)]
corrections to firing WR latch
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:15:46 +0000 (16:15 +0100)]
add text to ld_st_comp_unit image
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:04:15 +0000 (16:04 +0100)]
update LD/ST comp unit simplify explanation for now
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:55:18 +0000 (15:55 +0100)]
add new update-capable ld/st comp unit
lkcl [Mon, 27 Apr 2020 20:50:12 +0000 (21:50 +0100)]
lkcl [Mon, 27 Apr 2020 20:47:00 +0000 (21:47 +0100)]
lkcl [Mon, 27 Apr 2020 20:37:59 +0000 (21:37 +0100)]
lkcl [Mon, 27 Apr 2020 20:36:59 +0000 (21:36 +0100)]
lkcl [Mon, 27 Apr 2020 20:36:06 +0000 (21:36 +0100)]
lkcl [Mon, 27 Apr 2020 20:35:21 +0000 (21:35 +0100)]
lkcl [Mon, 27 Apr 2020 20:31:06 +0000 (21:31 +0100)]
lkcl [Mon, 27 Apr 2020 20:30:15 +0000 (21:30 +0100)]
lkcl [Mon, 27 Apr 2020 20:25:40 +0000 (21:25 +0100)]
lkcl [Mon, 27 Apr 2020 20:25:23 +0000 (21:25 +0100)]
lkcl [Mon, 27 Apr 2020 20:22:32 +0000 (21:22 +0100)]
lkcl [Mon, 27 Apr 2020 20:21:24 +0000 (21:21 +0100)]
lkcl [Mon, 27 Apr 2020 20:19:23 +0000 (21:19 +0100)]
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:45:07 +0000 (11:45 +0100)]
update text description to match diagram on L0 cache/buffer
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:37:35 +0000 (11:37 +0100)]
update image size
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:34:32 +0000 (11:34 +0100)]
revise diagram to include twin-l0-port
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:28:03 +0000 (11:28 +0100)]
add memory interface requirements section
lkcl [Mon, 27 Apr 2020 05:28:37 +0000 (06:28 +0100)]
lkcl [Mon, 27 Apr 2020 05:27:43 +0000 (06:27 +0100)]
lkcl [Mon, 27 Apr 2020 05:14:48 +0000 (06:14 +0100)]
lkcl [Sat, 25 Apr 2020 16:53:22 +0000 (17:53 +0100)]
lkcl [Fri, 24 Apr 2020 14:40:34 +0000 (15:40 +0100)]
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 13:46:46 +0000 (14:46 +0100)]
add link to list
programmerjake [Thu, 23 Apr 2020 05:45:09 +0000 (06:45 +0100)]
add placeholder alternative memory interface design idea
programmerjake [Thu, 23 Apr 2020 05:43:23 +0000 (06:43 +0100)]
add link to alternative memory interface idea
lkcl [Thu, 23 Apr 2020 00:35:09 +0000 (01:35 +0100)]
lkcl [Thu, 23 Apr 2020 00:32:15 +0000 (01:32 +0100)]
lkcl [Thu, 23 Apr 2020 00:28:59 +0000 (01:28 +0100)]
lkcl [Wed, 22 Apr 2020 22:23:11 +0000 (23:23 +0100)]
lkcl [Wed, 22 Apr 2020 22:14:14 +0000 (23:14 +0100)]
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 13:08:06 +0000 (14:08 +0100)]
mention misaligned exception;
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:52:59 +0000 (13:52 +0100)]
add link to comp.arch
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:31:24 +0000 (13:31 +0100)]
write-up on twin L0 cache/buffer
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:11:42 +0000 (13:11 +0100)]
add twin L0 cache/buffer diagram
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:09:13 +0000 (13:09 +0100)]
add twin L0 cache/buffer
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 10:41:58 +0000 (11:41 +0100)]
add memory and cache page for 180nm ASIC
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 10:11:16 +0000 (11:11 +0100)]
add 180nm memory layout diagram
projects / libreriscv.git / log