mesa.git
10 years agoRevert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Jordan Justen [Wed, 3 Sep 2014 21:28:59 +0000 (14:28 -0700)]
Revert 5 i965 patches: 8e27a4d2373143edc5bdf9be6f56e14288e3d404

Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
   8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
   373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
   c5bdf9be1eca190417998d548fd140c1eca37a54
   Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
   6f56e1424d923fd80c84090fbf4506c9eaaffea1
   Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
   88e3d404dad009d8cff5124cf8acee7daeaceb64

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agofreedreno/ir3: fix constlen with relative addressing
Rob Clark [Thu, 4 Sep 2014 17:48:05 +0000 (13:48 -0400)]
freedreno/ir3: fix constlen with relative addressing

We can't rely on the value from the assembler if relative addressing is
used.  So instead use the max of declared-consts (which does not include
compiler immediates) and what we get from the assembler (which does).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/ir3: fix error in bail logic
Rob Clark [Wed, 3 Sep 2014 23:45:19 +0000 (19:45 -0400)]
freedreno/ir3: fix error in bail logic

all_delayed will also be true if we didn't attempt to schedule anything
due to no more instructions using current addr/pred.  We rely on coming
in to block_sched_undelayed() to detect and clean up when there are no
more uses of the current addr/pred, which isn't necessarily an error.

This fixes a regression introduced in b823abed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/ir3: bit of debug
Rob Clark [Wed, 3 Sep 2014 22:45:55 +0000 (18:45 -0400)]
freedreno/ir3: bit of debug

Make it easier to figure out which compiler stage failed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agovc4: Merge qcompile and tgsi_to_qir
Eric Anholt [Wed, 13 Aug 2014 20:41:22 +0000 (13:41 -0700)]
vc4: Merge qcompile and tgsi_to_qir

The split between these two didn't make much sense.  I'm going to want the
chance to look at uniform contents in optimization passes, and the QPU
emit I think is going to end up rewriting the uniforms stream.

10 years agoi965/fs: Use prog rather than fp->Base in fs_visitor
Jordan Justen [Fri, 29 Aug 2014 00:34:29 +0000 (17:34 -0700)]
i965/fs: Use prog rather than fp->Base in fs_visitor

Reduce fs_visitor's dependence on gl_fragment_program.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/fs: Use stage_prog_data instead of prog_data->base in fs_visitor
Jordan Justen [Thu, 21 Aug 2014 22:56:21 +0000 (15:56 -0700)]
i965/fs: Use stage_prog_data instead of prog_data->base in fs_visitor

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/fs: Add init function to fs_visitor
Jordan Justen [Sun, 31 Aug 2014 02:10:27 +0000 (19:10 -0700)]
i965/fs: Add init function to fs_visitor

This common init routine can be used by constructors for multiple program
types.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agovc4: Add a CSE optimization pass.
Eric Anholt [Mon, 25 Aug 2014 07:12:21 +0000 (00:12 -0700)]
vc4: Add a CSE optimization pass.

Debugging a regression in discard support was just too full of duplicate
instructions, so I decided to remove them instead of re-analyzing each of
them as I dumped their outputs in simulation.

10 years agovc4: Switch to using native integers.
Eric Anholt [Sun, 24 Aug 2014 21:05:37 +0000 (14:05 -0700)]
vc4: Switch to using native integers.

There were troubles with bools without using native integers
(st_glsl_to_tgsi seemed to think bool true was 1.0f sometimes, when as a
uniform it's stored as ~0), and since I've got native integers other than
divide, I might as well just support them.

10 years agovc4: Expose compares at a lower level in QIR.
Eric Anholt [Sun, 24 Aug 2014 23:51:32 +0000 (16:51 -0700)]
vc4: Expose compares at a lower level in QIR.

Before, we had some special opcodes like CMP and SNE that emitted multiple
instructions.  Now, we reduce those operations significantly, giving
optimization more to look at for reducing redundant operations.

The downside is that QOP_SF is pretty special -- we're going to have to
track it separately when we're doing instruction scheduling, and we want
to peephole it into the instruction generating the destination write in
most cases (and not allocate the destination reg, probably.  Unless it's
used for some other purpose, as well).

10 years agovc4: Stop being so clever in CMP handling.
Eric Anholt [Mon, 25 Aug 2014 01:00:44 +0000 (18:00 -0700)]
vc4: Stop being so clever in CMP handling.

This kind of cleverness should be in a general merging-of-ADD-and-MUL
instruction scheduler, rather than individual opcodes.

10 years agostate_tracker: Fix bug in conditional discards with native ints.
Eric Anholt [Wed, 3 Sep 2014 18:57:47 +0000 (11:57 -0700)]
state_tracker: Fix bug in conditional discards with native ints.

A bool is 0 or ~0, and KILL_IF takes a float arg that's <0 for discard or
>= 0 for not.  By negating it, we ended up doing a floating point subtract
of (0 - ~0), which ended up as an inf.  To make this actually work, we
need to convert the bool to a float.

Reviewed-by: Brian Paul <brianp@vmware.com>
10 years agoswrast: s/INLINE/inline/
Brian Paul [Thu, 4 Sep 2014 15:21:08 +0000 (09:21 -0600)]
swrast: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoosmesa: s/INLINE/inline/
Brian Paul [Thu, 4 Sep 2014 15:20:58 +0000 (09:20 -0600)]
osmesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoxlib: s/INLINE/inline/
Brian Paul [Thu, 4 Sep 2014 15:20:50 +0000 (09:20 -0600)]
xlib: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agometa: s/INLINE/inline/
Brian Paul [Thu, 4 Sep 2014 15:20:20 +0000 (09:20 -0600)]
meta: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agomesa: s/INLINE/inline/
Brian Paul [Thu, 4 Sep 2014 15:20:08 +0000 (09:20 -0600)]
mesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agor600g,radeonsi: make sure there's enough CS space before resuming queries
Marek Olšák [Wed, 3 Sep 2014 11:58:57 +0000 (13:58 +0200)]
r600g,radeonsi: make sure there's enough CS space before resuming queries

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83432

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agomesa: invalidate draw state in glPopClientAttrib
Marek Olšák [Mon, 1 Sep 2014 18:01:03 +0000 (20:01 +0200)]
mesa: invalidate draw state in glPopClientAttrib

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82538

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
10 years agoRevert "r600g,radeonsi: initialize HTILE to fully-expanded state"
Marek Olšák [Thu, 4 Sep 2014 13:24:45 +0000 (15:24 +0200)]
Revert "r600g,radeonsi: initialize HTILE to fully-expanded state"

This reverts commit f05fe294e7e8dfb08be172f426252192c0ba17ab.

Apparently the hw doesn't like this. Revert to the "cleared" state.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83418

10 years agowinsys/svga: Fix incorrect type usage in IOCTL v2
Thomas Hellstrom [Wed, 3 Sep 2014 09:14:51 +0000 (11:14 +0200)]
winsys/svga: Fix incorrect type usage in IOCTL v2

While similar in layout, the size of the SVGA3dSize type may be smaller than
the struct drm_vmw_size type that is part of the ioctl interface. The kernel
driver could accordingly overwrite a memory area following the size variable
on the stack. Typically that would be another local variable, causing
breakage in, for example, ubuntu 12.04.5 where the handle local variable
becomes overwritten.

v2: Fix whitespace errors

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Cc: "10.1 10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agoglapi: Add KHR_debug functions to check_table test
Timothy Arceri [Fri, 4 Apr 2014 11:08:50 +0000 (22:08 +1100)]
glapi: Add KHR_debug functions to check_table test

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
10 years agoegl: Restrict multiplication in calloc arguments to use compile-time constants
Carl Worth [Wed, 3 Sep 2014 21:33:18 +0000 (14:33 -0700)]
egl: Restrict multiplication in calloc arguments to use compile-time constants

As explained in the previous commit, we want to avoid the possibility of
integer-multiplication overflow while allocating buffers.

In these two cases, the final allocation size is the product of three values:
one variable and two that are fixed constants at compile time.

In this commit, we move the explicit multiplication to involve only the
compile-time constants, preventing any overflow from that multiplication, (and
allowing calloc to catch any potential overflow from the remainining implicit
multiplication).

Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoEliminate several cases of multiplication in arguments to calloc
Carl Worth [Wed, 3 Sep 2014 21:18:18 +0000 (14:18 -0700)]
Eliminate several cases of multiplication in arguments to calloc

In commit 32f2fd1c5d6088692551c80352b7d6fa35b0cd09, several calls to
_mesa_calloc(x) were replaced with calls to calloc(1, x). This is strictly
equivalent to what the code was doing previously.

But for cases where "x" involves multiplication, now that we are explicitly
using the two-argument calloc, we can do one step better and replace:

calloc(1, A * B);

with:

calloc(A, B);

The advantage of the latter is that calloc will detect any overflow that would
have resulted from the multiplication and will fail the allocation, (whereas
the former would return a small allocation). So this fix can change
potentially exploitable buffer overruns into segmentation faults.

Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoglsl: Report progress from opt_copy_propagation_elements().
Kenneth Graunke [Thu, 28 Aug 2014 22:15:02 +0000 (15:15 -0700)]
glsl: Report progress from opt_copy_propagation_elements().

It's been altering the tree and reporting "false" since January 2011.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoglsl: Skip rewriting instructions in opt_cpe when unnecessary.
Kenneth Graunke [Thu, 28 Aug 2014 22:44:49 +0000 (15:44 -0700)]
glsl: Skip rewriting instructions in opt_cpe when unnecessary.

Previously, opt_copy_propagation_elements would always rewrite the
instruction stream, even if was the same thing as before.  In order to
report progress correctly, we'll need to bail if the suggested
replacement is identical (or equivalent) to the original code.

This also introduced unnecessary noop swizzles, as far as I can tell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoglsl: Initialize source_chan in opt_copy_propagation_elements.
Kenneth Graunke [Thu, 28 Aug 2014 22:33:56 +0000 (15:33 -0700)]
glsl: Initialize source_chan in opt_copy_propagation_elements.

Previously, if chans < 4, we passed uninitialized stack garbage to the
ir_swizzle constructor for the excess components.  Thankfully, it
ignores that data, as it's unnecessary, so no harm actually comes of it.

However, it's obviously better to initialize it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965: Handle ir_triop_csel in emit_bool_to_cond_code().
Kenneth Graunke [Fri, 22 Aug 2014 19:19:49 +0000 (12:19 -0700)]
i965: Handle ir_triop_csel in emit_bool_to_cond_code().

ir_triop_csel can return a boolean expression, so we need to handle it
here; we simply forgot when we added it.

Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
10 years agoi965: Move curb_read_length/total_scratch to brw_stage_prog_data.
Kenneth Graunke [Tue, 2 Sep 2014 18:38:29 +0000 (11:38 -0700)]
i965: Move curb_read_length/total_scratch to brw_stage_prog_data.

All shader stages have these fields, so it makes sense to store them in
the common base structure, rather than duplicating them in each.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agobuild: Rename md5 to checksums as part of .PHONY target
Carl Worth [Tue, 26 Aug 2014 23:13:14 +0000 (16:13 -0700)]
build: Rename md5 to checksums as part of .PHONY target

In commit 46d03d37bf3a75e86f9f8ab56c6a939d04f23383 I renamed a Makefile target
from md5 to checksums, (as we switched from MD5 checksums to SHA-256
checksums, so the more general name is more future proof).

But that commit missed one mention of "md5" as a dependency of the .PHONY
target. Rename that here as well.

10 years agoglsl: fix assertion which fails for unsigned array indices.
tiffany [Sat, 30 Aug 2014 18:30:00 +0000 (12:30 -0600)]
glsl: fix assertion which fails for unsigned array indices.

According to the GLSL 1.40 spec, section 5.7 Structure and Array Operations:

"Array elements are accessed using an expression whose type is int or uint."

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
10 years agoi965/copy_image: Divide the x offsets by block width when using the blitter
Jason Ekstrand [Tue, 2 Sep 2014 22:30:41 +0000 (15:30 -0700)]
i965/copy_image: Divide the x offsets by block width when using the blitter

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965/copy_image: Use the correct block dimension
Jason Ekstrand [Tue, 2 Sep 2014 22:28:39 +0000 (15:28 -0700)]
i965/copy_image: Use the correct block dimension

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agometa/copy_image: Use the correct texture level when creating views
Jason Ekstrand [Tue, 2 Sep 2014 21:08:31 +0000 (14:08 -0700)]
meta/copy_image: Use the correct texture level when creating views

Previously, we were accidentally assuming that the level of both textures
was 0.  Now we actually use the correct level in our hacked texture view.
This doesn't 100% fix the meta path because the texture type is getting
lost somewhere in the pipeline.  However, it actually copies to/from the
correct layer now.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965/copy_image: Use the correct texture level
Jason Ekstrand [Mon, 1 Sep 2014 11:38:28 +0000 (04:38 -0700)]
i965/copy_image: Use the correct texture level

Previously, we were using the source images level for both source and
destination.  Also, we weren't taking the MinLevel from a potential texture
view into account.  This commit fixes both problems.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agogallivm: Fix build against LLVM SVN >= r216982
Michel Dänzer [Wed, 3 Sep 2014 02:36:34 +0000 (11:36 +0900)]
gallivm: Fix build against LLVM SVN >= r216982

Only MCJIT is available anymore.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: fix alpha-test with HyperZ enabled, fixing L4D2 tree corruption
Marek Olšák [Tue, 2 Sep 2014 18:38:08 +0000 (20:38 +0200)]
r600g: fix alpha-test with HyperZ enabled, fixing L4D2 tree corruption

*_update_db_shader_control depends on the alpha test state. The problem was
it was in a block which is only entered if the pixel shader is changed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74863

Cc: mesa-stable@lists.freedesktop.org
Tested-by: Benjamin Bellec <b.bellec@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g,radeonsi: Preserve existing buffer flags
Michel Dänzer [Tue, 2 Sep 2014 08:52:30 +0000 (17:52 +0900)]
r600g,radeonsi: Preserve existing buffer flags

The default case was accidentally clearing RADEON_FLAG_CPU_ACCESS from the
previous fall-through cases.

Reported-by: Mathias Fröhlich <Mathias.Froehlich@gmx.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
10 years agomain: Don't leak temporary texture rows
Jason Ekstrand [Mon, 1 Sep 2014 08:33:36 +0000 (01:33 -0700)]
main: Don't leak temporary texture rows

Reviewed-by: Dave Airlie <airlied@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
10 years agor300g: pointless assignment of info.indexed
Dave Airlie [Mon, 1 Sep 2014 23:17:35 +0000 (09:17 +1000)]
r300g: pointless assignment of info.indexed

Did this code mean to do something else, you tell me!

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoomx/h264: remove stray semicolon after if
Dave Airlie [Mon, 1 Sep 2014 23:39:24 +0000 (09:39 +1000)]
omx/h264: remove stray semicolon after if

Coverity reported this, looks wrong to me.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agovdpau: unlock the mutex on error paths in attribute setting.
Dave Airlie [Mon, 1 Sep 2014 22:57:53 +0000 (08:57 +1000)]
vdpau: unlock the mutex on error paths in attribute setting.

Coverity pointed out we never dropped the lock here, so fix
it by using a common exit path.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agou_primconvert: Use u_upload_mgr for our little IB allocations.
Eric Anholt [Sat, 30 Aug 2014 01:03:36 +0000 (18:03 -0700)]
u_primconvert: Use u_upload_mgr for our little IB allocations.

tex-miplevel-selection was hammering my memory manager with primconverts
on individual quads.  This gets all those converted IBs packed into larger
IBs.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
10 years agou_primconvert: Shut up compiler warning.
Eric Anholt [Sat, 30 Aug 2014 01:02:23 +0000 (18:02 -0700)]
u_primconvert: Shut up compiler warning.

gcc isn't detecting that src is set before used, since both are under if
(info->indexed).

Reviewed-by: Rob Clark <robclark@freedesktop.org>
10 years agogbm: Fix gallium build when X11 is in a non-system directory
Eric Anholt [Fri, 18 Jul 2014 23:25:45 +0000 (16:25 -0700)]
gbm: Fix gallium build when X11 is in a non-system directory

pipe-loader.h will include Xlib.h when HAVE_PIPE_LOADER_XLIB is set in the
build.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
10 years agovc4: Handle a couple of the transfer map flags.
Eric Anholt [Fri, 22 Aug 2014 20:47:19 +0000 (13:47 -0700)]
vc4: Handle a couple of the transfer map flags.

This is part of fixing extremely long runtimes on some piglit tests that
involve streaming vertex reuploads due to format conversions, and will
similarly be important for X performance, which relies on these flags.

10 years agometa: Make MESA_META_DRAW_BUFFERS restore properly
Kristian Høgsberg [Sat, 16 Aug 2014 06:19:52 +0000 (23:19 -0700)]
meta: Make MESA_META_DRAW_BUFFERS restore properly

A meta begin/end pair with MESA_META_DRAW_BUFFERS will change visible GL
state.  We recreate the draw buffer enums from the buffer bitfield, which
changes GL_BACK to GL_BACK_LEFT (and GL_FRONT to GL_FRONT_LEFT).

This commit modifes the save/restore logic to instead copy the buffer enums
from the gl_framebuffer and then set them on restore using
_mesa_drawbuffers().

It's not clear how this breaks the benchmark in 82796, but fixing meta to not
leak the state change fixes the regression.

No piglit regressions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=82796
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org
10 years agoRevert "mesa: fix make tarballs"
Emil Velikov [Mon, 1 Sep 2014 11:04:12 +0000 (12:04 +0100)]
Revert "mesa: fix make tarballs"

This reverts commit 0fbb9a599df898d4e1166d6d6f00cb34a0524bea.

Rather than adding hacks around the issue drop the sources from the
final tarball, and re-add them back with 'make dist'. This fixes a
problem when running parallel 'make install' fails as it recreates
sources and triggers partial recompilation.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83355
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
10 years agomesa/program_cache: calloc the correct size for the cache.
Dave Airlie [Mon, 1 Sep 2014 23:21:18 +0000 (09:21 +1000)]
mesa/program_cache: calloc the correct size for the cache.

Coverity reported this, and I think this is the right solution,
since cache->items is struct cache_item ** not struct cache_item *,
we also realloc it using struct cache_item * at some point.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoradeonsi: Compile dummy pixel shader on demand
Michel Dänzer [Wed, 27 Aug 2014 08:29:08 +0000 (17:29 +0900)]
radeonsi: Compile dummy pixel shader on demand

It's never used under normal circumstances.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
10 years agou_blitter: Create all shaders on demand
Michel Dänzer [Wed, 27 Aug 2014 07:43:56 +0000 (16:43 +0900)]
u_blitter: Create all shaders on demand

Not all of these are used in every context, so this can make a
significant difference for short-lived contexts such as in piglit tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
10 years agor600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU
Michel Dänzer [Tue, 26 Aug 2014 09:06:49 +0000 (18:06 +0900)]
r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU

This allows the kernel to prevent such BOs from ever being stored in the
CPU inaccessible part of VRAM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
10 years agoglsl: free uniform_map on failure path.
Dave Airlie [Mon, 1 Sep 2014 23:54:36 +0000 (09:54 +1000)]
glsl: free uniform_map on failure path.

If we fails in reserve_explicit_locations, we leak uniform_map.

Reported-by: coverity scanner.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agomain/cs: Add gl_context::ComputeProgram
Paul Berry [Sat, 11 Jan 2014 05:39:25 +0000 (21:39 -0800)]
main/cs: Add gl_context::ComputeProgram

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agomesa: Convert NewDriverState to 64-bits
Jordan Justen [Thu, 7 Aug 2014 05:32:03 +0000 (22:32 -0700)]
mesa: Convert NewDriverState to 64-bits

i965 will have more than 32 bits when BRW_STATE_COMPUTE_PROGRAM is added.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
10 years agoi965: Modify state upload to allow 2 different sets of state atoms.
Paul Berry [Sat, 11 Jan 2014 00:37:09 +0000 (16:37 -0800)]
i965: Modify state upload to allow 2 different sets of state atoms.

The set of state atoms for compute shaders is currently empty; it will
be filled in by future patches.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965: Modify dirty bit handling to support 2 pipelines.
Paul Berry [Sat, 11 Jan 2014 00:05:11 +0000 (16:05 -0800)]
i965: Modify dirty bit handling to support 2 pipelines.

The hardware state for compute shaders is almost entirely orthogonal
to the hardware state for 3D rendering.  To avoid sending unnecessary
state to the hardware, we'll need to have a separate set of state
atoms for the compute pipeline and the 3D pipeline.  That means we
need to maintain two separate sets of dirty bits to determine which
state atoms need to be run.

But the dirty bits are not completely independent; for example, if
BRW_NEW_SURFACES is flagged while doing 3D rendering, then not only do
we need to re-run 3D state atoms that depend on BRW_NEW_SURFACES, but
we also need to re-run compute state atoms that depend on
BRW_NEW_SURFACES.  But we'll also need to re-run those state atoms the
next time the compute pipeline is run.

To accomplish this, we record two sets of dirty bits, one for each
pipeline.  When bits are dirtied (via SET_DIRTY_BIT() or
SET_DIRTY_ALL()) we set them to the dirty state in both pipelines.
When brw_state_upload() is run, we clear the dirty bits just for the
pipeline that was run.

Note that since the number of pipelines is known at compile time to be
2, the compiler should unroll the loops in SET_DIRTY_BIT() and
SET_DIRTY_ALL().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965: Create a macro for checking a dirty bit.
Paul Berry [Fri, 10 Jan 2014 23:40:57 +0000 (15:40 -0800)]
i965: Create a macro for checking a dirty bit.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965: Create a macro for setting all dirty bits.
Paul Berry [Fri, 10 Jan 2014 22:23:52 +0000 (14:23 -0800)]
i965: Create a macro for setting all dirty bits.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965: Create a macro for setting a dirty bit.
Paul Berry [Fri, 10 Jan 2014 21:00:51 +0000 (13:00 -0800)]
i965: Create a macro for setting a dirty bit.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965: add missing parens in vec4 visitor
Dave Airlie [Tue, 2 Sep 2014 00:13:02 +0000 (10:13 +1000)]
i965: add missing parens in vec4 visitor

coverity reported this, Matt said it look like missing parens,
not bad identing, so lets try that.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agonouveau: don't leak dec struct on error
Dave Airlie [Mon, 1 Sep 2014 23:07:55 +0000 (09:07 +1000)]
nouveau: don't leak dec struct on error

This one path doesn't goto fail, so it seems to leak dec.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoxvmc/tests: %C isn't a valid printf specifier.
Dave Airlie [Tue, 2 Sep 2014 00:03:00 +0000 (10:03 +1000)]
xvmc/tests: %C isn't a valid printf specifier.

Reported-by: Coverity scanner.
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agonouveau/nv40: quiten coverity warning in unused vertex texture code.
Dave Airlie [Mon, 1 Sep 2014 22:55:55 +0000 (08:55 +1000)]
nouveau/nv40: quiten coverity warning in unused vertex texture code.

This fixes the code, but we never run it anyways, so silence coverity.

Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agonv50: remove unused variables
Ilia Mirkin [Mon, 1 Sep 2014 22:47:01 +0000 (18:47 -0400)]
nv50: remove unused variables

Recent code changes have caused these to no longer be used. Remove them.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agomesa: force height of 1D textures to be 1 in texture views
Ilia Mirkin [Wed, 20 Aug 2014 06:42:30 +0000 (02:42 -0400)]
mesa: force height of 1D textures to be 1 in texture views

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
10 years agonv50: attach the buffer bo to the miptree structures
Ilia Mirkin [Mon, 1 Sep 2014 14:51:08 +0000 (10:51 -0400)]
nv50: attach the buffer bo to the miptree structures

The current code... makes no sense. Use nouveau_bo_ref to attach the bo
to the exposed resource so as to have the proper lifetime guarantees.

Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonv50: mt address may not be the underlying bo's start address
Ilia Mirkin [Mon, 1 Sep 2014 14:48:09 +0000 (10:48 -0400)]
nv50: mt address may not be the underlying bo's start address

With VP2, nv50_miptree is faked because the underlying bo's have to be
laid out in a certain way. This is done by adjusting the address. Make
sure that blits (and everything else for consistency) use the mt address
rather than the bo address as a base.

This fixes retrieving chroma plane with VDPAU.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82255
Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonv50: set the miptree address when clearing bo's in vp2 init
Ilia Mirkin [Mon, 1 Sep 2014 16:48:12 +0000 (12:48 -0400)]
nv50: set the miptree address when clearing bo's in vp2 init

The mt address is about to be used more, make sure it's set
appropriately.

Reported-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonv50/ir: avoid creating instructions that can't be emitted
Ilia Mirkin [Mon, 1 Sep 2014 14:55:27 +0000 (10:55 -0400)]
nv50/ir: avoid creating instructions that can't be emitted

When constant folding a MAD operation, we first fold the multiply and
generate an ADD. However we do so without making sure that the immediate
can be handled in the saturate case. If it can't, load the immediate in
a separate instruction.

Reported-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonvc0: don't make 1d staging textures linear
Ilia Mirkin [Mon, 1 Sep 2014 04:43:06 +0000 (00:43 -0400)]
nvc0: don't make 1d staging textures linear

Experimentally, the sampler doesn't appear to like these, neither as
buffer nor as rect textures. So remove 1D from the list of texture types
to make linear when used for staging.

This fixes the OSD in mplayer for VDPAU.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonv50: zero out unbound samplers
Ilia Mirkin [Sat, 30 Aug 2014 17:35:47 +0000 (13:35 -0400)]
nv50: zero out unbound samplers

Samplers are only defined up to num_samplers, so set all samplers above
nr to NULL so that we don't try to read them again later.

Tested-by: Christian Ruppert <idl0r@qasl.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agonvc0/ir: avoid infinite recursion when finding first uses of tex
Ilia Mirkin [Fri, 29 Aug 2014 03:05:49 +0000 (23:05 -0400)]
nvc0/ir: avoid infinite recursion when finding first uses of tex

In certain circumstances, findFirstUses could end up doubling back on
instructions it had already processed, resulting in an infinite
recursion. Avoid this by keeping track of already-visited instructions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83079
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
10 years agofreedreno/ir3: add DDX/DDY
Rob Clark [Mon, 1 Sep 2014 16:37:26 +0000 (12:37 -0400)]
freedreno/ir3: add DDX/DDY

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/ir3: don't keep IR around
Rob Clark [Mon, 1 Sep 2014 16:36:34 +0000 (12:36 -0400)]
freedreno/ir3: don't keep IR around

Once we've assembled the shader, no need to keep the intermediate
around.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agoi965/fs: Don't segfault when debug-logging a null program
Jason Ekstrand [Fri, 29 Aug 2014 18:23:55 +0000 (11:23 -0700)]
i965/fs: Don't segfault when debug-logging a null program

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/vec4: Don't segfault when debug-logging a null program
Jason Ekstrand [Thu, 28 Aug 2014 04:49:50 +0000 (21:49 -0700)]
i965/vec4: Don't segfault when debug-logging a null program

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoradeonsi: implement EXPCLEAR optimization for depth
Marek Olšák [Sat, 23 Aug 2014 14:46:53 +0000 (16:46 +0200)]
radeonsi: implement EXPCLEAR optimization for depth

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g,radeonsi: initialize HTILE to fully-expanded state
Marek Olšák [Sat, 23 Aug 2014 13:48:21 +0000 (15:48 +0200)]
r600g,radeonsi: initialize HTILE to fully-expanded state

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agoradeonsi: implement fast depth clear
Marek Olšák [Sat, 23 Aug 2014 01:39:08 +0000 (03:39 +0200)]
radeonsi: implement fast depth clear

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agoradeonsi: move DB_RENDER_CONTROL into draw_vbo
Marek Olšák [Sat, 23 Aug 2014 01:25:29 +0000 (03:25 +0200)]
radeonsi: move DB_RENDER_CONTROL into draw_vbo

So that I can add fast depth clear.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agoradeonsi: disable occlusion queries if they are not needed
Marek Olšák [Sat, 23 Aug 2014 09:12:01 +0000 (11:12 +0200)]
radeonsi: disable occlusion queries if they are not needed

We always left them enabled, which turned off HiZ in some cases.
This should improve performace with Hyper-Z.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g,radeonsi: force fast stencil and HTILE stencil off, fixing a Hyper-Z hang
Marek Olšák [Sat, 23 Aug 2014 00:03:58 +0000 (02:03 +0200)]
r600g,radeonsi: force fast stencil and HTILE stencil off, fixing a Hyper-Z hang

This should be as fast as no HTILE for stencil. I think we can still get full
performance with depth-only rendering even if stencil is present in the buffer
but not used, but I'm not 100% sure. This may be revisited when HiS and fast
stencil clear are implemented.

This fixes a hang in Brutal Legend.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64471

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: set VGT_ENHANCE=4 on R7xx
Marek Olšák [Wed, 20 Aug 2014 21:58:24 +0000 (23:58 +0200)]
r600g: set VGT_ENHANCE=4 on R7xx

This is a golden setting on RV740, but there is a hw bug which recommends
setting it on all R7xx chipsets.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: expose AMD_vertex_shader_layer and *_viewport_index on R600-R700
Marek Olšák [Wed, 20 Aug 2014 17:17:39 +0000 (19:17 +0200)]
r600g: expose AMD_vertex_shader_layer and *_viewport_index on R600-R700

already implemented

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: fix layered clear
Marek Olšák [Wed, 20 Aug 2014 17:17:09 +0000 (19:17 +0200)]
r600g: fix layered clear

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: some DB bug workarounds for R6xx DB flushing
Marek Olšák [Wed, 20 Aug 2014 15:22:41 +0000 (17:22 +0200)]
r600g: some DB bug workarounds for R6xx DB flushing

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: enable fast depth clear for array textures and cubemaps
Marek Olšák [Wed, 20 Aug 2014 12:36:53 +0000 (14:36 +0200)]
r600g: enable fast depth clear for array textures and cubemaps

I have a piglit test that hits this.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: use HTILE allocator from SI
Marek Olšák [Tue, 19 Aug 2014 23:34:37 +0000 (01:34 +0200)]
r600g: use HTILE allocator from SI

It's almost the same.

This enables tiling for HTILE. It also enables Hyper-Z for other texture
targets (1D, 1D_ARRAY, 2D_ARRAY, CUBE, CUBE_ARRAY, 3D, RECT).

2D array depth textures are tested by Unigine Sanctuary and my new piglit
test.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX for EG/CM, inline other fields
Marek Olšák [Wed, 20 Aug 2014 10:52:09 +0000 (12:52 +0200)]
r600g: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX for EG/CM, inline other fields

This fixes rendering to non-zero layer/face/slice with HTILE.

v2: added the assertion

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agoradeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fields
Marek Olšák [Tue, 19 Aug 2014 14:22:12 +0000 (16:22 +0200)]
radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fields

This fixes rendering to a non-zero layer/face/slice with HTILE.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72685

v2: added the assertion

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agor600g: Implement sm5 geometry shader instancing
Glenn Kennard [Mon, 25 Aug 2014 09:05:06 +0000 (11:05 +0200)]
r600g: Implement sm5 geometry shader instancing

Requires Evergreen or later hardware.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
10 years agoglsl_to_tgsi: allocate and enlarge arrays for temporaries on demand
Marek Olšák [Sat, 23 Aug 2014 22:56:12 +0000 (00:56 +0200)]
glsl_to_tgsi: allocate and enlarge arrays for temporaries on demand

This fixes crashes if the number of temporaries is greater than 4096.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66184

v2: added fail paths for realloc failures

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agogallium/pb_bufmgr_cache: limit the size of cache
Marek Olšák [Wed, 20 Aug 2014 21:53:40 +0000 (23:53 +0200)]
gallium/pb_bufmgr_cache: limit the size of cache

This should make a machine which is running piglit more responsive at times.
e.g. streaming-texture-leak can easily eat 600 MB because of how fast it
creates new textures.

10 years agopipe-loader: use the correct screen index
Marek Olšák [Tue, 19 Aug 2014 22:34:18 +0000 (00:34 +0200)]
pipe-loader: use the correct screen index

10 years agoegl/dri2: use the correct screen index
Marek Olšák [Tue, 19 Aug 2014 22:33:34 +0000 (00:33 +0200)]
egl/dri2: use the correct screen index

Required for multi-GPU configuration where each GPU has its own X screen.

10 years agodocs: Mark ARB_compute_shader as work in progress
Jordan Justen [Wed, 27 Aug 2014 20:22:12 +0000 (13:22 -0700)]
docs: Mark ARB_compute_shader as work in progress

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
10 years agoi965/fs: don't use ir->shadow_comparitor in emit_texture_*
Connor Abbott [Mon, 4 Aug 2014 22:20:37 +0000 (15:20 -0700)]
i965/fs: don't use ir->shadow_comparitor in emit_texture_*

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/fs: don't pass ir_variable * to emit_samplepos_setup()
Connor Abbott [Tue, 5 Aug 2014 18:10:07 +0000 (11:10 -0700)]
i965/fs: don't pass ir_variable * to emit_samplepos_setup()

We were only using it to get at its type, which we already know because
it's a builtin variable.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>