anv: Use framebuffer layers for implicit subpass transitions

Fixes: de3be618016 "anv/cmd_buffer: Rework aux tracking"
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv: Be more careful about fast-clear colors

Previously, we just used all the channels regardless of the format.
This is less than ideal because some channels may have undefined values
and this should be ok from the client's perspective.  Even though the
driver should do the correct thing regardless of what is in the
undefined value, it makes things less deterministic.  In particular, the
driver may choose to fast-clear or not based on undefined values.  This
level of nondeterminism is bad.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Add an isl_color_value_is_zero helper

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv/gpu_memcpy: CS Stall before a MI memcpy on gen7

This fixes a pile of hangs caused by the recent shuffling of resolves
and transitions.  The particularly problematic case is when you have at
least three attachments with load ops of CLEAR, LOAD, CLEAR.  In this
case, we execute the first CLEAR followed by a MI memcpy to copy the
clear values over for the LOAD followed by a second CLEAR.  The MI
commands cause the first CLEAR to hang which causes us to get stuck on
the 3DSTATE_MULTISAMPLE in the second CLEAR.

We also add guards for BLORP to fix the same issue.  These shouldn't
actually do anything right now because the only use of indirect clears
in BLORP today is for resolves which are already guarded by a render
cache flush and CS stall.  However, this will guard us against potential
issues in the future.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>

st/mesa: Factorize duplicate code for atomic buffer binding

Signed-off-by: Guillaume Charifi <guillaume.charifi@sfr.fr>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: Factorize duplicate code in st_update_framebuffer_state()

Signed-off-by: Guillaume Charifi <guillaume.charifi@sfr.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

freedreno/ir3: fix use_count refcnt'ing issue

Was hitting an assert with vs-varying-array-mat4-index-col-row-wr.shader_test

When eliminating a copy, we were dropping the use_count of the mov that
is skipped, but not increasing the use_count of it's src instruction.

Fixes: 76440fcca91 freedreno/ir3: clean up dangling false-dep's
Signed-off-by: Rob Clark <robdclark@gmail.com>

docs: fix patent url

Reported-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

svga: replaced 'unsigned' with proper enum types in shader code

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

configure.ac: pthread-stubs not present on OpenBSD

pthread-stubs is no longer required on OpenBSD and has been removed.
libpthread parts involved moved to libc.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: 17.3 18.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

swr: bump minimum supported LLVM version to 4.0

Since radv and radeonsi removed support for LLVM 3.9 the distcheck
target got broken because SWR distribution needed 3.9.x.

After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0
and above, which will solve this problem.

Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: George Kyriazis <george.kyriazis@intel.com>
Cc: Tim Rowley <timothy.o.rowley@intel.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

travis: radeonsi and radv need LLVM 4.0

Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

ac/nir: move ac_declare_lds_as_pointer() outside of the switch

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: allow to force family using RADV_FORCE_FAMILY

Useful for pipeline-db.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

loader_dri3/glx/egl: Reinstate the loader_dri3_vtable get_dri_screen callback

Removing this callback caused rendering corruption in some multi-screen cases,
so it is reinstated but without the drawable argument which was never used
by implementations and was confusing since the drawable could have been
created with another screen.

Cc: "17.3 18.0" mesa-stable@lists.freedesktop.org
Fixes: 5198e48a0d (loader_dri3/glx/egl: Remove the loader_dri3_vtable get_dri_screen callback)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105013
Reported-by: Daniel van Vugt <daniel.van.vugt@canonical.com>
Tested-by: Timo Aaltonen <tjaalton@ubuntu.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

svga: Fix a leftover debug hack

Fix what appears to be a leftover debug hack.
The hack would force the driver to take a different blit path; possibly,
although unverified, reverting to software blits.

Tested using piglit tests/quick. No related regressions.

Cc: "17.2 17.3 18.0" <mesa-stable@lists.freedesktop.org>
Fixes: 9d81ab7376 (svga: Relax the format checks for copy_region_vgpu10 somewhat)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104625
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

anv/entrypoints: make vkGetDeviceProcAddr return NULL for instance commands

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nv50,nvc0: mark ABGR format as displayable instead of ARGB format

This matches the hardware's capabilities.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/dri: only expose config formats that are display targets

In the case of NVIDIA hardware, ABGR is displayable but ARGB is not.
Only advertise the one set in the visuals list.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>

mesa: add xbgr support adjacent to xrgb

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Daniel Stone <daniels@collabora.com>

st/shader_cache: copy nir pointer to gl_program after deserializing

This fixes a crash when running the arb_get_program_binary-api-errors
piglit test twice.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add nir shader cache support

In future we might want to try avoid calling nir_serialize() but
this works for now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: rename variables tgsi_binary -> ir_binary

This better represents that the ir could be either tgsi or nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

docs: update calendar, add news and link release notes to 17.3.5

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.3.5

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 164a993112cc7278d46b7ec8f7f617eb683b212c)

docs: add release notes for 17.3.5

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 2529d77179065b983d69c620c7f71281aefe4f98)

radeonsi: fix regression from 32-bit pointers on CI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

radv: compact varyings after removing unused ones

It makes no sense to compact before, and the description of
nir_compact_varyings() confirms that.

Polaris10:
Totals from affected shaders:
SGPRS: 108528 -> 108128 (-0.37 %)
VGPRS: 74548 -> 74500 (-0.06 %)
Spilled SGPRs: 844 -> 814 (-3.55 %)
Code Size: 3007328 -> 2992932 (-0.48 %) bytes
Max Waves: 16019 -> 16009 (-0.06 %)

Vega10:
Totals from affected shaders:
SGPRS: 106088 -> 106232 (0.14 %)
VGPRS: 74652 -> 74700 (0.06 %)
Spilled SGPRs: 692 -> 658 (-4.91 %)
Code Size: 2967708 -> 2953028 (-0.49 %) bytes
Max Waves: 18178 -> 18162 (-0.09 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi/nir: fix gl_FragCoord for pixel_center_integer

Fixes piglit test glsl-arb-fragment-coord-conventions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/nir: add pixel_center_integer to shader info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gm107/ir: avoid using kepler instruction capabilities

Split up the op properties table into generation-specific bits, and only
use the kepler ones on kepler. Fixes some CTS images tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>

nvc0: add support for bindless on maxwell+

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: change how SUQ works in preparation for bindless

All this information can be retrieved from the TIC directly. Avoid
having to dip into the constbuf information about the image.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.

By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic
state base address.  This makes it unusable for pushing UBOs.

There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake)
which controls whether buffer 0 is relative to dynamic state base
address, or simply a normal pointer.  Setting that gives us full
flexibility.  This lets us push up to 4 UBO ranges.

We can't currently write this on Haswell and earlier, and will need
to update the kernel command parser, and then do the whole version
checking song and dance.  We also need a brand new kernel that supports
context isolation - on older kernels, newly created contexts inherit
register state from whatever happened to be running.  So, setting this
would have catastrophic impact on other drivers such as libva, Beignet,
or older Mesa.

See commit 8ec5a4e4a4a32f4de351c5fc2bf0eb615b6eef1b where we did this
once before, but had to revert it in commit 013d33122028f2492da90a03a.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Stop restoring the default L3 configuration on Kernel 4.16+.

Kernel 4.16 has proper context isolation, which means we can change
the L3 configuration without worrying about that leaking to other
newly created contexts, breaking the assumptions of other userspace.

So, disable our workaround to reprogram it back to the default.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

nvc0: Use GP100_COMPUTE_CLASS on GP10B

GP10B requires the use of GP100_COMPUTE_CLASS instead of
GP104_COMPUTE_CLASS as is used for other non-GP100 chips.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Fix aux-surface size check

The previous commit reworked the checks intel_from_planar() to check the
right individual cases for regular/planar/aux buffers, and do size
checks in all cases.

Unfortunately, the aux size check was broken, and required the aux
surface to be allocated with the correct aux stride, but full image
height (!).

As the ISL aux surface is not recorded in the DRIimage, we cannot easily
access it to check. Instead, store the aux size from when we do have the
ISL surface to hand, and check against that later when we go to access
the aux surface.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: c2c4e5bae3ba ("i965: Fix bugs in intel_from_planar")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: implement 32-bit pointers in user data SGPRs (v2)

User SGPRs changes:
    VS:     14 ->  9
    TCS:    14 -> 10
    TES:    10 ->  6
    GS:      8 ->  4
    GSCOPY:  2 ->  1
    PS:      9 ->  5
    Merged VS-TCS: 24 -> 16
    Merged VS-GS:  18 -> 11
    Merged TES-GS: 18 -> 11

SGPRS: 2170102 -> 2158430 (-0.54 %)
VGPRS: 1645656 -> 1641516 (-0.25 %)
Spilled SGPRs: 9078 -> 8810 (-2.95 %)
Spilled VGPRs: 130 -> 114 (-12.31 %)
Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread
Code Size: 52094872 -> 52692540 (1.15 %) bytes
Max Waves: 371848 -> 372723 (0.24 %)

v2: - the shader cache needs to take address32_hi into account
    - set amdgpu-32bit-address-high-bits

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)

radeonsi: disallow constant buffers with a 64-bit address in slot 0

State trackers must use a user buffer or const_uploader,
or set pipe_resource::flags same as const_uploader->flags.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: move const_uploader allocations to 32-bit address space

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

winsys/radeon: implement and enable 32-bit VM allocations

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

winsys/radeon: add struct radeon_vm_heap

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

winsys/amdgpu: enable 32-bit VM allocations

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/radeon: add 32-bit address space heaps

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac: query high bits of 32-bit address space

gallium: use PIPE_CAP_CONSTBUF0_FLAGS

gallium: allow drivers to impose BO flags restrictions on constant buffer 0

Required by radeonsi for optimal behavior.

meson: Add Haiku platform support v4

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

anv/icl: Add render target flush after uploading binding table

The PIPE_CONTROL command description says:

"Whenever a Binding Table Index (BTI) used by a Render Taget Message
points to a different RENDER_SURFACE_STATE, SW must issue a Render
Target Cache Flush by enabling this bit. When render target flush
is set due to new association of BTI, PS Scoreboard Stall bit must
be set in this packet."

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Enable float blend optimization

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Use gen11 functions

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Build anv libs for gen11

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Generate gen11 entry point functions

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Don't use DISPATCH_MODE_SIMD4X2

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Don't use SingleVertexDispatch

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Don't set ResetGatewayTimer

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Add #define genX

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/icl: Add gen11 mocs defines

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Implement GenerateMipmap directly, rather than using Meta.

Meta is awful and we'd like to stop using it.  Implementing this using
BLORP allows us to stop trashing a bunch of GL state every time.

This follows the structure of st_generate_mipmap().
compute_num_levels is lifted directly from there.

Improves performance in Gl41HdrBloom by about 11.794% +/- 1.01919% (n=3)
on Kabylake GT2 at 1280x720 (the difference seems much smaller at higher
resolutions).

v2 (idr): Don't try depth or depth-stencil blorp blits on Gen4 or Gen5
because it's not implemented yet.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

mesa: Move compute_num_levels from st_gen_mipmap.c to mipmap.c.

I want to use compute_num_levels inside i965.  Rather than duplicating
it, move it from mesa/st to core Mesa, and make it non-static.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

meson: freedreno depends on nir

This fixes a race condition in building targets that link in freedreno.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105120
Fixes: 0bbecc5a8548883f76a7 ("meson: define driver dependencies")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Mark Janes <mark.a.janes@intel.com>

swr/rast: blend_epi32() should return Integer, not Float

fix gcc8 compiler error for KNL.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105029
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Normalize path for debug metadata

in template gen_llvm.hpp

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Consolidate archrast Draw events

Consolidate archrst draw events into single draw event with an attribute
that represents the type of draw

- Add handlers for new private proto versions of DrawInstancedEvent,
  DrawIndexedInstancedEvent, DrawInstancedSplitEvent, and
  DrawIndexedInstancedSplitEvent
- Convert the draw events to generic DrawInfoEvents
- parse_proto_event_fields() replaces 'AR_DRAW_TYPE' as a field type with
  'uint32_t'. This draw type is actually an enum, but can be represented
  as an unsigned integer.
- is_draw_or_dispatch() recognizes DrawInfoEvent as a draw event

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add semantics for translating address

Added support for another full translation path in fetch jitter.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Convert C Sampler intrinsics

Convert portions of the C sampler to the rasty SIMD lib.

Also fix SRL call with a non-immediate.  Don't count on the compiler
automagically converting an srli call to srl if the shift count isn't
an immediate.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Make SIMDLib templated types easier to use

"typename SIMD_T::TypeName" --> "TypeName<SIMD_T>"

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Be more explicit when fetching next component

Use a new function to denote that we want to get offset to next component
and hide the fact that GEP is used underneath.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix bug related to passing AR handle

We were passing a garbage handle. Let's not do that.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix primitive replication issue in tesselation PA.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Use llvm intrinsic masked gather

Use llvm intrinsic masked.gather instead of manual unroll for the cases
where we have vector of pointers.  Improves llvm IR debug experience by
reducing a ton of IR to a single intrinsic call. Also seems to reduce
overall stack use considerably.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Misc cleanup

Together with correct detection of clipDistance NaNs when no cullDistance is set

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Renamed variable in vertexbufferstate

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix GATHERPS to avoid assertions.

With the pBase type change, LLVM was asserting because of wrong types.
Cast appropriately.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: More precise user clip distance interpolation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Cull prims when all verts have negative clip distances

Performance optimization, and fixes some clipping issues.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: whitespace and comment cleanup

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix invalid number of attributes

Fix invalid number of attributes passed into tesselation PA.
Needs to take into account any offsets from the shader.
Innocuous issue, but removes an assert firing in debug.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add clipper stats.

Clipper event is now:

event ClipperEvent
{
    uint32_t drawId;
    uint32_t trivialRejectCount;
    uint32_t trivialAcceptCount;
    uint32_t mustClipCount;
};

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Separate event types to public and private

Split into two proto files and modify appropriate build rules for
configure / scons / meson builds.

There are private internal events (proxy) that communicate information
from rasterizer to ArchRast. ArchRast can use these events to calculate
a final answer and then emit other public events which will be saved to
file. Users will use the public proto file and not the private one.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Clean up event types and remove BE events

Begin/End events not needed anymore.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Removed unused variable

Gets rid of zillions of unused variable warnings, made worse by templates.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Separate RDTSC code from archrast

Renamed rdstc defines more appropriately

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Cleanup of mpPrivateContext in Builder

Provide access functions for mpPrivateContext in Builder.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove some JIT debug code

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Don't include private context in gather args

Move mpPrivateContext to compensate

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Cleanup knob definitions

Rename some of the categories and move some options around.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add missing parameter to a few gather functions

We now pass pDrawContext as a default parameter

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

etnaviv: add useful information to BO import errors

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

egl/wayland: Always use in-tree wayland-egl-backend.h

A recent patchset to Wayland[0] migrated Mesa's libwayland-egl backend
into Wayland itself, so implementations could provide backends. Mesa
still uses its own, and the two have already diverged[1].

The include from egl_dri2.h could pick up either the installed Wayland
wayland-egl-backend.h (with a 'driver_private' member), or the Mesa
internal wayland-egl-backend.h (with a 'private' member), failing the
build in the first instance.

Add an explicit directory prefix to the include, so we always get our
in-tree version.

[0]: https://patchwork.freedesktop.org/series/31663/
[1]: https://cgit.freedesktop.org/wayland/wayland/commit/?id=9fa60983b579

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105103
Fixes: 198af27c679c ("wayland-egl: rename wayland-egl-{priv,backend}.h")

meson: Move Wayland dmabuf to wayland-drm

As the comment notes: linux-dmabuf has nothing to do with wayland-drm,
but we need a single place to build these files we can use from both EGL
and Vulkan, which is guaranteed to be included before both EGL and
Vulkan WSI.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>

egl/wayland: check for invalid format index

v2: just tell the compiler to assume the format will always be found, as
it comes from the table itself to begin with. (DanielS)

CID: 1429516
Fixes: d32b23f3830099a328b91 "egl/wayland: Add bpp to visual map"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>

glsl: fix sizeof(pointer) bug

Doesn't really change anything to the test though ¯\_(ツ)_/¯

CID: 1429511
Fixes: e8495646afb06a9dd7786 "glsl/tests: changes to test_disk_cache_create test"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

radeonsi/nir: set TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL correctly

We set this for post_depth_coverage in addition to early_fragment_tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

virgl: remap query types to hw support.

The gallium query types changed, so we need to remap from the
gallium ones to the virgl ones.

Fixes:
dEQP-GLES3.functional.transform_feedback.basic_types*

"This also fixes:

dEQP-GLES3.functional.transform_feedback.array.separate*
dEQP-GLES3.functional.transform_feedback.array_element*
dEQP-GLES3.functional.transform_feedback.interpolation.*

Gallium's p_defines.h and virglrenderer's p_defines.h have diverged
quite a bit, so not including
PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE there makes sense for now."
 - Gurchetan Singh

Fixes: 3f6b3d9db (gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965/icl: Add render target flush after uploading binding table

From PIPE_CONTROL command description in gfxspecs:

"Whenever a Binding Table Index (BTI) used by a Render Taget Message
 points to a different RENDER_SURFACE_STATE, SW must issue a Render
 Target Cache Flush by enabling this bit. When render target flush
 is set due to new association of BTI, PS Scoreboard Stall bit must
 be set in this packet."

V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
    brw_wm_surface_state.c (Ken).

Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/icl: Enable float blend optimization and Wa3DStateMode

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/common/icl: Add has_sample_with_hiz flag in gen_device_info

Sampling from hiz is enabled in i965 for GEN9+ but this feature has
been removed from gen11. So, this new flag will be useful to turn
the feature on/off for different gen h/w. It will be used later
in a patch adding device info for gen11.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/icl: Add assertions to check dispatch mode is SIMD8

SIMD4x2 dispatch mode has been removed in GEN11. We're not using
it anyways in Mesa. Adding few asserts to make it explicit.

Use GEN_GEN macro in place of devinfo->gen (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/icl: Update switch statements

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>