Clifford Wolf [Sun, 9 Aug 2015 11:35:44 +0000 (13:35 +0200)]
Use MEMID as name for $mem cell
Clifford Wolf [Thu, 6 Aug 2015 22:03:39 +0000 (00:03 +0200)]
Merge pull request #69 from zeldin/master
Added iCE40 WARMBOOT cell
Marcus Comstedt [Thu, 6 Aug 2015 20:58:17 +0000 (22:58 +0200)]
Added iCE40 WARMBOOT cell
Clifford Wolf [Wed, 5 Aug 2015 20:11:10 +0000 (22:11 +0200)]
Remove some very strange whitespace in btor.cc (by Larry Doolittle)
Clifford Wolf [Wed, 5 Aug 2015 09:36:26 +0000 (11:36 +0200)]
Bugfix in SMV back-end for partially unassigned wires
Clifford Wolf [Tue, 4 Aug 2015 18:25:26 +0000 (20:25 +0200)]
Added ENABLE_LIBYOSYS Makefile option
Clifford Wolf [Tue, 4 Aug 2015 18:05:37 +0000 (20:05 +0200)]
Added $assert support to SMV back-end
Clifford Wolf [Tue, 4 Aug 2015 11:22:49 +0000 (13:22 +0200)]
Added libyosys.so build
Clifford Wolf [Sat, 1 Aug 2015 10:52:10 +0000 (12:52 +0200)]
Merge pull request #68 from zeldin/master
Add -noautowire option to verilog frontend
Marcus Comstedt [Sat, 1 Aug 2015 10:16:54 +0000 (12:16 +0200)]
Add -noautowire option to verilog frontend
Clifford Wolf [Fri, 31 Jul 2015 08:40:09 +0000 (10:40 +0200)]
Added WORDS parameter to $meminit
Clifford Wolf [Thu, 30 Jul 2015 19:43:41 +0000 (21:43 +0200)]
Fixed flatten $meminit handling
Clifford Wolf [Wed, 29 Jul 2015 15:06:19 +0000 (17:06 +0200)]
Improvements in BLIF back-end
Clifford Wolf [Wed, 29 Jul 2015 14:37:08 +0000 (16:37 +0200)]
Fixed nested mem2reg
Clifford Wolf [Mon, 27 Jul 2015 20:44:01 +0000 (22:44 +0200)]
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
Clifford Wolf [Mon, 27 Jul 2015 07:54:58 +0000 (09:54 +0200)]
Fixed "check" command for inout ports
Clifford Wolf [Sat, 25 Jul 2015 10:01:25 +0000 (12:01 +0200)]
Some cleanups in opt_rmdff
Clifford Wolf [Sat, 25 Jul 2015 09:23:45 +0000 (11:23 +0200)]
Added "miter -assert"
Clifford Wolf [Sat, 25 Jul 2015 08:31:52 +0000 (10:31 +0200)]
Keep modules with $assume (like $assert)
Clifford Wolf [Fri, 24 Jul 2015 12:12:50 +0000 (14:12 +0200)]
Improved $adff simplification
Clifford Wolf [Mon, 20 Jul 2015 11:05:18 +0000 (13:05 +0200)]
iCE40 DFF sim models: init Q regs to 0
Clifford Wolf [Sat, 18 Jul 2015 10:16:27 +0000 (12:16 +0200)]
Fixed techmap processes error msg
Clifford Wolf [Sat, 18 Jul 2015 09:59:04 +0000 (11:59 +0200)]
Avoid tristate warning for blackbox ice40/cells_sim.v
Clifford Wolf [Thu, 16 Jul 2015 20:10:26 +0000 (22:10 +0200)]
Some fixes in "select" command
Clifford Wolf [Fri, 10 Jul 2015 11:20:57 +0000 (13:20 +0200)]
Fixed YosysJS.create_worker() usage of this.url_prefix
Clifford Wolf [Mon, 6 Jul 2015 15:45:56 +0000 (17:45 +0200)]
Improved liberty file test case
Clifford Wolf [Mon, 6 Jul 2015 15:45:40 +0000 (17:45 +0200)]
Updated ABC
Clifford Wolf [Mon, 6 Jul 2015 11:28:00 +0000 (13:28 +0200)]
Do not collect disabled $memwr cells
Clifford Wolf [Sat, 4 Jul 2015 15:08:44 +0000 (17:08 +0200)]
Improved YosysJS WebWorker API
Clifford Wolf [Fri, 3 Jul 2015 16:42:36 +0000 (18:42 +0200)]
Bugfix in fsm_extract
Clifford Wolf [Thu, 2 Jul 2015 13:25:38 +0000 (15:25 +0200)]
Added "synth -nofsm"
Clifford Wolf [Thu, 2 Jul 2015 09:14:30 +0000 (11:14 +0200)]
Fixed trailing whitespaces
Clifford Wolf [Wed, 1 Jul 2015 08:49:21 +0000 (10:49 +0200)]
Added opt_const -clkinv
Clifford Wolf [Tue, 30 Jun 2015 15:11:46 +0000 (17:11 +0200)]
Added logic-loop error handling to freduce
Clifford Wolf [Mon, 29 Jun 2015 23:49:55 +0000 (01:49 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Mon, 29 Jun 2015 23:38:34 +0000 (01:38 +0200)]
Bugfix in chparam
Clifford Wolf [Mon, 29 Jun 2015 23:37:59 +0000 (01:37 +0200)]
Added design->rename(module, new_name)
Clifford Wolf [Sun, 28 Jun 2015 15:47:58 +0000 (17:47 +0200)]
Added YosysJS.create_worker()
Clifford Wolf [Sat, 20 Jun 2015 07:31:19 +0000 (09:31 +0200)]
iCE40: set min bram efficiency to 2%
Clifford Wolf [Sat, 20 Jun 2015 06:58:02 +0000 (08:58 +0200)]
Using static mem size of 128 MB in emcc build
Clifford Wolf [Fri, 19 Jun 2015 14:43:02 +0000 (16:43 +0200)]
Added init support to SMV back-end
Clifford Wolf [Fri, 19 Jun 2015 14:26:53 +0000 (16:26 +0200)]
Progress in SMV back-end
Clifford Wolf [Fri, 19 Jun 2015 12:08:46 +0000 (14:08 +0200)]
Progress in SMV back-end
Clifford Wolf [Thu, 18 Jun 2015 14:29:11 +0000 (16:29 +0200)]
Progress in SMV back-end
Clifford Wolf [Wed, 17 Jun 2015 07:56:42 +0000 (09:56 +0200)]
Progress in SMV back-end
Clifford Wolf [Wed, 17 Jun 2015 07:38:56 +0000 (09:38 +0200)]
Added "rename -top new_name"
Clifford Wolf [Wed, 17 Jun 2015 05:24:27 +0000 (07:24 +0200)]
Progress in SMV back-end
Clifford Wolf [Tue, 16 Jun 2015 17:05:26 +0000 (19:05 +0200)]
Progress in SMV back-end
Clifford Wolf [Mon, 15 Jun 2015 15:07:40 +0000 (17:07 +0200)]
Added "synth -nordff -noalumacc"
Clifford Wolf [Mon, 15 Jun 2015 15:01:01 +0000 (17:01 +0200)]
Progress in SMV back-end
Clifford Wolf [Mon, 15 Jun 2015 11:24:17 +0000 (13:24 +0200)]
Progress in SMV back-end
Clifford Wolf [Sun, 14 Jun 2015 22:46:27 +0000 (00:46 +0200)]
Added "write_smv" skeleton
Clifford Wolf [Sun, 14 Jun 2015 14:22:06 +0000 (16:22 +0200)]
Removed debug code from write_smt2
Clifford Wolf [Sun, 14 Jun 2015 14:15:51 +0000 (16:15 +0200)]
Modernized memory_dff (and fixed a bug)
Clifford Wolf [Sun, 14 Jun 2015 13:47:11 +0000 (15:47 +0200)]
Added "memory -nordff"
Clifford Wolf [Sun, 14 Jun 2015 13:46:47 +0000 (15:46 +0200)]
Added write_smt2 -mem
Clifford Wolf [Thu, 11 Jun 2015 13:48:40 +0000 (15:48 +0200)]
Makefile fix for YosysJS build
Clifford Wolf [Thu, 11 Jun 2015 11:39:49 +0000 (13:39 +0200)]
Fixed cstr_buf for std::string with small string optimization
Clifford Wolf [Thu, 11 Jun 2015 08:48:16 +0000 (10:48 +0200)]
Improvements in cellaigs.cc and "json -aig"
Clifford Wolf [Wed, 10 Jun 2015 21:00:12 +0000 (23:00 +0200)]
AigMaker refactoring
Clifford Wolf [Wed, 10 Jun 2015 06:13:56 +0000 (08:13 +0200)]
Added "json -aig"
Clifford Wolf [Wed, 10 Jun 2015 05:24:26 +0000 (07:24 +0200)]
Renamed "aig" to "aigmap"
Clifford Wolf [Wed, 10 Jun 2015 05:16:30 +0000 (07:16 +0200)]
Fixed cellaigs port extending
Clifford Wolf [Tue, 9 Jun 2015 20:33:26 +0000 (22:33 +0200)]
Added "aig" pass
Clifford Wolf [Tue, 9 Jun 2015 18:28:17 +0000 (20:28 +0200)]
synth_ice40 now flattens by default
Clifford Wolf [Tue, 9 Jun 2015 07:54:22 +0000 (09:54 +0200)]
Added cellaigs API
Clifford Wolf [Tue, 9 Jun 2015 05:19:04 +0000 (07:19 +0200)]
Merge clock inverters in memory_dff
Clifford Wolf [Tue, 9 Jun 2015 04:42:07 +0000 (06:42 +0200)]
Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys
luke whittlesey [Mon, 8 Jun 2015 21:35:40 +0000 (17:35 -0400)]
$mem cell in verilog backend : grouped writes by clock
Clifford Wolf [Mon, 8 Jun 2015 12:49:34 +0000 (14:49 +0200)]
Fixed "avail_parameters" handling in module clone/copy
Clifford Wolf [Mon, 8 Jun 2015 12:49:02 +0000 (14:49 +0200)]
Added log_dump() support for IdStrings
Clifford Wolf [Mon, 8 Jun 2015 12:03:06 +0000 (14:03 +0200)]
Fixed handling of parameters with reversed range
luke whittlesey [Thu, 4 Jun 2015 18:56:13 +0000 (14:56 -0400)]
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
Clifford Wolf [Sun, 31 May 2015 12:24:34 +0000 (14:24 +0200)]
Added opt_share -share_all
Clifford Wolf [Sun, 31 May 2015 11:10:43 +0000 (13:10 +0200)]
Added iCE40 PLL cells
Clifford Wolf [Sun, 31 May 2015 05:51:12 +0000 (07:51 +0200)]
Added liberty dont_use support to dfflibmap
Clifford Wolf [Fri, 29 May 2015 18:08:00 +0000 (20:08 +0200)]
Fixed signedness of genvar expressions
Clifford Wolf [Tue, 26 May 2015 15:04:37 +0000 (17:04 +0200)]
Added output args to synth_ice40
Clifford Wolf [Sun, 24 May 2015 06:03:21 +0000 (08:03 +0200)]
Improvements in BLIF front-end
Clifford Wolf [Sat, 23 May 2015 08:17:03 +0000 (10:17 +0200)]
improved ice40 SB_IO sim model
Clifford Wolf [Sat, 23 May 2015 08:14:53 +0000 (10:14 +0200)]
Improved "flatten" handlings of inout ports
Clifford Wolf [Sat, 23 May 2015 07:45:48 +0000 (09:45 +0200)]
Added simple $dlatch support to opt_rmdff
Clifford Wolf [Sat, 23 May 2015 07:30:24 +0000 (09:30 +0200)]
Added ice40 SB_IO sim model
Clifford Wolf [Fri, 22 May 2015 06:23:03 +0000 (08:23 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 22 May 2015 06:20:29 +0000 (08:20 +0200)]
preserve used $-wires with init attribute in opt_clean
Clifford Wolf [Wed, 20 May 2015 11:55:50 +0000 (13:55 +0200)]
Some fixes for $mem in verilog back-end
Clifford Wolf [Mon, 18 May 2015 09:15:49 +0000 (11:15 +0200)]
bugfix in blif front-end
Clifford Wolf [Sun, 17 May 2015 17:54:00 +0000 (19:54 +0200)]
added vloghtb test_febe.sh
Clifford Wolf [Sun, 17 May 2015 16:58:24 +0000 (18:58 +0200)]
Improved .latch support in BLIF front-end
Clifford Wolf [Sun, 17 May 2015 13:25:03 +0000 (15:25 +0200)]
Added read_blif command
Clifford Wolf [Sun, 17 May 2015 13:10:37 +0000 (15:10 +0200)]
Generalized blifparse API
Clifford Wolf [Sun, 17 May 2015 12:44:28 +0000 (14:44 +0200)]
abc/blifparse files reorganization
Clifford Wolf [Sun, 17 May 2015 06:19:52 +0000 (08:19 +0200)]
Verific build fixes
Clifford Wolf [Wed, 13 May 2015 04:45:12 +0000 (06:45 +0200)]
Added .barbuf support to abc BLIF parser
Clifford Wolf [Mon, 11 May 2015 19:46:35 +0000 (21:46 +0200)]
changed file() to open() in python scripts
Clifford Wolf [Mon, 11 May 2015 19:38:06 +0000 (21:38 +0200)]
Merge pull request #63 from wluker/verilog-backend-mem
Fixed bug in $mem cell verilog code generation.
luke whittlesey [Mon, 11 May 2015 18:05:18 +0000 (14:05 -0400)]
Fixed bug in $mem cell verilog code generation.
Clifford Wolf [Sun, 10 May 2015 19:38:41 +0000 (21:38 +0200)]
Disabled broken $mem support in verilog backend
Clifford Wolf [Sun, 10 May 2015 19:23:59 +0000 (21:23 +0200)]
Merge pull request #62 from wluker/verilog-backend-mem
Added support for $mem cells in the verilog backend.
luke whittlesey [Sun, 10 May 2015 15:33:24 +0000 (11:33 -0400)]
Made changes recommended by Clifford Wolf ...
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.