yosys.git
4 years agorpc test: make frontend listen before launching yosys & introduce safeguard if yosys...
N. Engelhardt [Fri, 6 Mar 2020 14:29:01 +0000 (15:29 +0100)]
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

4 years agoMerge pull request #1739 from YosysHQ/eddie/issue1738
Eddie Hung [Thu, 5 Mar 2020 17:41:54 +0000 (09:41 -0800)]
Merge pull request #1739 from YosysHQ/eddie/issue1738

ice40: fix specify for -device {lp,u}

4 years agoice40: fix specify for ICE40_{LP,U}
Eddie Hung [Thu, 5 Mar 2020 16:11:49 +0000 (08:11 -0800)]
ice40: fix specify for ICE40_{LP,U}

4 years agotests: extend tests/arch/run-tests.sh for defines
Eddie Hung [Thu, 5 Mar 2020 16:08:32 +0000 (08:08 -0800)]
tests: extend tests/arch/run-tests.sh for defines

4 years agoice40: fix implicit signal in specify, also clamp negative times to 0
Eddie Hung [Wed, 4 Mar 2020 23:28:17 +0000 (15:28 -0800)]
ice40: fix implicit signal in specify, also clamp negative times to 0

4 years agoMerge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
Eddie Hung [Wed, 4 Mar 2020 21:37:09 +0000 (13:37 -0800)]
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1

 xilinx: cleanup DSP48E1 handling for abc9

4 years agoxilinx: consider DSP48E1.ADREG
Eddie Hung [Wed, 4 Mar 2020 20:04:02 +0000 (12:04 -0800)]
xilinx: consider DSP48E1.ADREG

4 years agoxilinx: cleanup DSP48E1 handling for abc9
Eddie Hung [Wed, 4 Mar 2020 19:28:14 +0000 (11:28 -0800)]
xilinx: cleanup DSP48E1 handling for abc9

4 years agoxilinx: improve specify for DSP48E1
Eddie Hung [Wed, 4 Mar 2020 18:51:33 +0000 (10:51 -0800)]
xilinx: improve specify for DSP48E1

4 years agoxilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Eddie Hung [Wed, 4 Mar 2020 18:32:51 +0000 (10:32 -0800)]
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v

4 years agoMerge pull request #1691 from ZirconiumX/use-flowmap-in-noabc
N. Engelhardt [Tue, 3 Mar 2020 18:15:41 +0000 (19:15 +0100)]
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc

Add -flowmap option to `synth{,_ice40}`

4 years agoFix bison warning for "pure-parser" option
Claire Wolf [Tue, 3 Mar 2020 16:41:55 +0000 (08:41 -0800)]
Fix bison warning for "pure-parser" option

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #1718 from boqwxp/precise_locations
Claire Wolf [Tue, 3 Mar 2020 16:38:32 +0000 (08:38 -0800)]
Merge pull request #1718 from boqwxp/precise_locations

Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

4 years agoMerge pull request #1681 from YosysHQ/eddie/fix1663
Claire Wolf [Tue, 3 Mar 2020 16:34:31 +0000 (08:34 -0800)]
Merge pull request #1681 from YosysHQ/eddie/fix1663

verilog: instead of modifying localparam size, extend init constant expr

4 years agoMerge pull request #1519 from YosysHQ/eddie/submod_po
Claire Wolf [Tue, 3 Mar 2020 16:19:06 +0000 (08:19 -0800)]
Merge pull request #1519 from YosysHQ/eddie/submod_po

submod: several bugfixes

4 years agoiopadmap: Look harder for already-present buffers. (#1731)
Marcelina Kościelnicka [Mon, 2 Mar 2020 20:40:09 +0000 (21:40 +0100)]
iopadmap: Look harder for already-present buffers. (#1731)

iopadmap: Look harder for already-present buffers.

Fixes #1720.

4 years agoMerge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung [Mon, 2 Mar 2020 20:32:27 +0000 (12:32 -0800)]
Merge pull request #1724 from YosysHQ/eddie/abc9_specify

abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries

4 years agoMerge pull request #1729 from rqou/coolrunner2
N. Engelhardt [Mon, 2 Mar 2020 11:31:05 +0000 (12:31 +0100)]
Merge pull request #1729 from rqou/coolrunner2

coolrunner2 buffer cell insertion fixes

4 years agocoolrunner2: Attempt to give wires/cells more meaningful names
R. Ou [Mon, 2 Mar 2020 09:40:57 +0000 (01:40 -0800)]
coolrunner2: Attempt to give wires/cells more meaningful names

4 years agocoolrunner2: Fix invalid multiple fanouts of XOR/OR gates
R. Ou [Mon, 2 Mar 2020 09:06:03 +0000 (01:06 -0800)]
coolrunner2: Fix invalid multiple fanouts of XOR/OR gates

In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule

4 years agocoolrunner2: Fix packed register+input buffer insertion
R. Ou [Mon, 2 Mar 2020 08:32:36 +0000 (00:32 -0800)]
coolrunner2: Fix packed register+input buffer insertion

The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.

4 years agocoolrunner2: Insert many more required feedthrough cells
R. Ou [Sun, 1 Mar 2020 14:54:07 +0000 (06:54 -0800)]
coolrunner2: Insert many more required feedthrough cells

4 years agoMerge pull request #1727 from YosysHQ/eddie/fix_write_smt2
Eddie Hung [Sat, 29 Feb 2020 16:15:24 +0000 (08:15 -0800)]
Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2

ystests: fix write_smt2_write_smt2_cyclic_dependency_fail

4 years agoystests: fix write_smt2_write_smt2_cyclic_dependency_fail
Eddie Hung [Fri, 28 Feb 2020 20:33:55 +0000 (12:33 -0800)]
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail

4 years agoMerge pull request #1726 from YosysHQ/eddie/fix1710
Eddie Hung [Fri, 28 Feb 2020 18:39:03 +0000 (10:39 -0800)]
Merge pull request #1726 from YosysHQ/eddie/fix1710

ast: fixes #1710; do not generate RTLIL for unreachable ternary branch

4 years agoAdd -flowmap to synth and synth_ice40
Dan Ravensloft [Fri, 28 Feb 2020 14:29:57 +0000 (14:29 +0000)]
Add -flowmap to synth and synth_ice40

4 years agoast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung [Fri, 28 Feb 2020 00:55:55 +0000 (16:55 -0800)]
ast: fixes #1710; do not generate RTLIL for unreachable ternary

4 years agoComment out log()
Eddie Hung [Fri, 28 Feb 2020 00:53:49 +0000 (16:53 -0800)]
Comment out log()

4 years agoRemove RAMB{18,36}E1 from cells_xtra.py
Eddie Hung [Thu, 27 Feb 2020 18:33:04 +0000 (10:33 -0800)]
Remove RAMB{18,36}E1 from cells_xtra.py

4 years agoSmall fixes
Eddie Hung [Thu, 27 Feb 2020 18:29:53 +0000 (10:29 -0800)]
Small fixes

4 years agoFixes for older compilers
Eddie Hung [Thu, 20 Feb 2020 15:52:08 +0000 (07:52 -0800)]
Fixes for older compilers

4 years agoRevert "Fix tests/arch/xilinx/fsm.ys to count flops only"
Eddie Hung [Wed, 19 Feb 2020 17:47:36 +0000 (09:47 -0800)]
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"

This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.

4 years agoast: quiet down when deriving blackbox modules
Eddie Hung [Tue, 18 Feb 2020 23:32:56 +0000 (15:32 -0800)]
ast: quiet down when deriving blackbox modules

4 years agoabc9_ops: suppress -prep_box warning for abc9_flop
Eddie Hung [Tue, 18 Feb 2020 22:31:24 +0000 (14:31 -0800)]
abc9_ops: suppress -prep_box warning for abc9_flop

4 years agoxilinx: Update RAMB* specify entries
Eddie Hung [Tue, 18 Feb 2020 22:28:52 +0000 (14:28 -0800)]
xilinx: Update RAMB* specify entries

4 years agoice40: add delays to SB_CARRY
Eddie Hung [Tue, 18 Feb 2020 19:03:59 +0000 (11:03 -0800)]
ice40: add delays to SB_CARRY

4 years agoxilinx: add delays to INV
Eddie Hung [Tue, 18 Feb 2020 19:03:38 +0000 (11:03 -0800)]
xilinx: add delays to INV

4 years agoMake TimingInfo::TimingInfo(SigBit) constructor explicit
Eddie Hung [Tue, 18 Feb 2020 19:02:28 +0000 (11:02 -0800)]
Make TimingInfo::TimingInfo(SigBit) constructor explicit

4 years agoTimingInfo: index by (port_name,offset)
Eddie Hung [Tue, 18 Feb 2020 16:41:48 +0000 (08:41 -0800)]
TimingInfo: index by (port_name,offset)

4 years agoFix spacing
Eddie Hung [Tue, 18 Feb 2020 16:30:41 +0000 (08:30 -0800)]
Fix spacing

4 years agoMore +/ice40/cells_sim.v fixes
Eddie Hung [Sat, 15 Feb 2020 17:13:21 +0000 (09:13 -0800)]
More +/ice40/cells_sim.v fixes

4 years agoCleanup tests
Eddie Hung [Sat, 15 Feb 2020 16:29:10 +0000 (08:29 -0800)]
Cleanup tests

4 years agoUpdate bug1630.ys to use -lut 4 instead of lut file
Eddie Hung [Sat, 15 Feb 2020 16:27:41 +0000 (08:27 -0800)]
Update bug1630.ys to use -lut 4 instead of lut file

4 years agoMake +/xilinx/cells_sim.v legal
Eddie Hung [Sat, 15 Feb 2020 02:56:10 +0000 (18:56 -0800)]
Make +/xilinx/cells_sim.v legal

4 years agoabc9_ops: still emit delay table even box has no timing
Eddie Hung [Fri, 14 Feb 2020 21:53:28 +0000 (13:53 -0800)]
abc9_ops: still emit delay table even box has no timing

4 years agowrite_xaiger: add comment about arrival times of flop outputs
Eddie Hung [Fri, 14 Feb 2020 21:43:34 +0000 (13:43 -0800)]
write_xaiger: add comment about arrival times of flop outputs

4 years agoabc9_ops: demote lack of box timing info to warning
Eddie Hung [Fri, 14 Feb 2020 21:26:00 +0000 (13:26 -0800)]
abc9_ops: demote lack of box timing info to warning

4 years agoGet rid of (* abc9_{arrival,required} *) entirely
Eddie Hung [Fri, 14 Feb 2020 20:54:47 +0000 (12:54 -0800)]
Get rid of (* abc9_{arrival,required} *) entirely

4 years agoabc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung [Fri, 14 Feb 2020 20:01:03 +0000 (12:01 -0800)]
abc9_ops: use TimingInfo for -prep_{lut,box} too

4 years agoabc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung [Fri, 14 Feb 2020 19:41:43 +0000 (11:41 -0800)]
abc9_ops: use TimingInfo for -prep_{lut,box} too

4 years agoabc9_ops: add and use new TimingInfo struct
Eddie Hung [Fri, 14 Feb 2020 19:11:34 +0000 (11:11 -0800)]
abc9_ops: add and use new TimingInfo struct

4 years agoFix tests/arch/xilinx/fsm.ys to count flops only
Eddie Hung [Fri, 14 Feb 2020 18:31:38 +0000 (10:31 -0800)]
Fix tests/arch/xilinx/fsm.ys to count flops only

4 years agoExpand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
Eddie Hung [Fri, 14 Feb 2020 17:17:53 +0000 (09:17 -0800)]
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy

4 years agoice40: fix specify for inverted clocks
Eddie Hung [Fri, 14 Feb 2020 17:17:20 +0000 (09:17 -0800)]
ice40: fix specify for inverted clocks

4 years agoFix tests by gating some specify constructs from iverilog
Eddie Hung [Thu, 13 Feb 2020 21:43:33 +0000 (13:43 -0800)]
Fix tests by gating some specify constructs from iverilog

4 years agoUpdate simple_abc9 tests
Eddie Hung [Thu, 13 Feb 2020 20:13:12 +0000 (12:13 -0800)]
Update simple_abc9 tests

4 years agoabc9_ops: ignore (* abc9_flop *) if not '-dff'
Eddie Hung [Thu, 13 Feb 2020 19:15:59 +0000 (11:15 -0800)]
abc9_ops: ignore (* abc9_flop *) if not '-dff'

4 years agoice40: specify fixes
Eddie Hung [Thu, 13 Feb 2020 18:30:56 +0000 (10:30 -0800)]
ice40: specify fixes

4 years agoabc9_ops: sort LUT delays to be ascending
Eddie Hung [Thu, 13 Feb 2020 18:30:29 +0000 (10:30 -0800)]
abc9_ops: sort LUT delays to be ascending

4 years agoice40: move over to specify blocks for -abc9
Eddie Hung [Thu, 13 Feb 2020 17:58:20 +0000 (09:58 -0800)]
ice40: move over to specify blocks for -abc9

4 years agosynth_ecp5: use +/abc9_model.v
Eddie Hung [Thu, 13 Feb 2020 17:56:52 +0000 (09:56 -0800)]
synth_ecp5: use +/abc9_model.v

4 years agoUpdate xilinx for ABC9
Eddie Hung [Thu, 13 Feb 2020 17:56:30 +0000 (09:56 -0800)]
Update xilinx for ABC9

4 years agoCreate +/abc9_model.v for $__ABC9_{DELAY,FF_}
Eddie Hung [Thu, 13 Feb 2020 17:56:00 +0000 (09:56 -0800)]
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}

4 years agoabc9_ops: output LUT area
Eddie Hung [Thu, 13 Feb 2020 17:54:40 +0000 (09:54 -0800)]
abc9_ops: output LUT area

4 years agoecp5: remove small LUT entries
Eddie Hung [Thu, 13 Feb 2020 17:50:17 +0000 (09:50 -0800)]
ecp5: remove small LUT entries

4 years agoabc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs
Eddie Hung [Thu, 13 Feb 2020 17:48:48 +0000 (09:48 -0800)]
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs

4 years agoFix commented out specify statement
Eddie Hung [Thu, 13 Feb 2020 00:06:24 +0000 (16:06 -0800)]
Fix commented out specify statement

4 years agoxilinx: improve specify functionality
Eddie Hung [Wed, 12 Feb 2020 23:25:30 +0000 (15:25 -0800)]
xilinx: improve specify functionality

4 years agoecp5: deprecate abc9_{arrival,required} and *.{lut,box}
Eddie Hung [Wed, 12 Feb 2020 19:30:37 +0000 (11:30 -0800)]
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}

4 years agoxilinx: use specify blocks in place of abc9_{arrival,required}
Eddie Hung [Tue, 11 Feb 2020 22:22:43 +0000 (14:22 -0800)]
xilinx: use specify blocks in place of abc9_{arrival,required}

4 years agoAuto-generate .box/.lut files from specify blocks
Eddie Hung [Tue, 11 Feb 2020 19:38:49 +0000 (11:38 -0800)]
Auto-generate .box/.lut files from specify blocks

4 years agoabc9_ops: assert on $specify2 properties
Eddie Hung [Tue, 11 Feb 2020 17:18:08 +0000 (09:18 -0800)]
abc9_ops: assert on $specify2 properties

4 years agoabc9_ops: -prep_box, to be called once
Eddie Hung [Tue, 11 Feb 2020 16:54:13 +0000 (08:54 -0800)]
abc9_ops: -prep_box, to be called once

4 years agoabc9_ops: -prep_lut and -write_lut to auto-generate LUT library
Eddie Hung [Tue, 11 Feb 2020 16:34:13 +0000 (08:34 -0800)]
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library

4 years agoMerge pull request #1709 from rqou/coolrunner2_counter
Claire Wolf [Thu, 27 Feb 2020 18:05:56 +0000 (19:05 +0100)]
Merge pull request #1709 from rqou/coolrunner2_counter

Improve CoolRunner-II optimization by using extract_counter pass

4 years agoMerge pull request #1708 from rqou/coolrunner2-buf-fix
Claire Wolf [Thu, 27 Feb 2020 18:03:59 +0000 (19:03 +0100)]
Merge pull request #1708 from rqou/coolrunner2-buf-fix

coolrunner2: Separate and improve buffer cell insertion pass

4 years agoxilinx: mark IOBUFDSE3 IOB pin as external
Piotr Binkowski [Thu, 27 Feb 2020 10:21:01 +0000 (11:21 +0100)]
xilinx: mark IOBUFDSE3 IOB pin as external

4 years agoMerge pull request #1705 from YosysHQ/logger_pass
Miodrag Milanović [Wed, 26 Feb 2020 12:32:49 +0000 (13:32 +0100)]
Merge pull request #1705 from YosysHQ/logger_pass

Logger pass

4 years agoRemove tests for now
Miodrag Milanovic [Wed, 26 Feb 2020 08:49:41 +0000 (09:49 +0100)]
Remove tests for now

4 years agoChange attribute search value to specify precise location instead of simple line...
Alberto Gonzalez [Mon, 24 Feb 2020 02:41:08 +0000 (02:41 +0000)]
Change attribute search value to specify precise location instead of simple line number.

4 years agoChange attribute search value to specify precise location instead of simple line...
Alberto Gonzalez [Mon, 24 Feb 2020 01:39:36 +0000 (01:39 +0000)]
Change attribute search value to specify precise location instead of simple line number.

4 years agoAdd tests for logger pass
Miodrag Milanovic [Sun, 23 Feb 2020 09:56:39 +0000 (10:56 +0100)]
Add tests for logger pass

4 years agoRemove duplicate warning detection
Miodrag Milanovic [Sun, 23 Feb 2020 09:56:27 +0000 (10:56 +0100)]
Remove duplicate warning detection

4 years agoFix line endings
Miodrag Milanovic [Sun, 23 Feb 2020 09:05:21 +0000 (10:05 +0100)]
Fix line endings

4 years agoCloses #1717. Add more precise Verilog source location information to AST and RTLIL...
Alberto Gonzalez [Sun, 23 Feb 2020 07:19:52 +0000 (07:19 +0000)]
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

4 years agoMerge pull request #1715 from boqwxp/master
Eddie Hung [Sat, 22 Feb 2020 19:29:22 +0000 (11:29 -0800)]
Merge pull request #1715 from boqwxp/master

Closes #1714. Fix make failure when NDEBUG=1.

4 years agoUpdate explanation for expect-no-warnings
Miodrag Milanovic [Sat, 22 Feb 2020 09:53:23 +0000 (10:53 +0100)]
Update explanation for expect-no-warnings

4 years agoHandle expect no warnings together with expected
Miodrag Milanovic [Sat, 22 Feb 2020 09:52:46 +0000 (10:52 +0100)]
Handle expect no warnings together with expected

4 years agoCheck other regex parameters
Miodrag Milanovic [Sat, 22 Feb 2020 09:31:56 +0000 (10:31 +0100)]
Check other regex parameters

4 years agoCloses #1714. Fix make failure when NDEBUG=1.
Alberto Gonzalez [Sat, 22 Feb 2020 06:29:11 +0000 (06:29 +0000)]
Closes #1714. Fix make failure when NDEBUG=1.

4 years agoMerge pull request #1703 from YosysHQ/eddie/specify_improve
Eddie Hung [Fri, 21 Feb 2020 17:15:17 +0000 (09:15 -0800)]
Merge pull request #1703 from YosysHQ/eddie/specify_improve

Improve specify parser

4 years agoMerge pull request #1642 from jjj11x/jjj11x/sv-enum
Claire Wolf [Thu, 20 Feb 2020 17:17:25 +0000 (18:17 +0100)]
Merge pull request #1642 from jjj11x/jjj11x/sv-enum

Enum support

4 years agocheck for regex errors
Miodrag Milanovic [Thu, 20 Feb 2020 10:41:37 +0000 (11:41 +0100)]
check for regex errors

4 years agoverilog: add support for more delays than just rise/fall
Eddie Hung [Wed, 19 Feb 2020 19:09:37 +0000 (11:09 -0800)]
verilog: add support for more delays than just rise/fall

4 years agoclean: ignore specify-s inside cells when determining whether to keep
Eddie Hung [Wed, 19 Feb 2020 18:45:10 +0000 (10:45 -0800)]
clean: ignore specify-s inside cells when determining whether to keep

4 years agoPrevent double error message
Miodrag Milanovic [Mon, 17 Feb 2020 15:46:34 +0000 (16:46 +0100)]
Prevent double error message

4 years agoOption to expect no warnings
Miodrag Milanovic [Mon, 17 Feb 2020 14:36:06 +0000 (15:36 +0100)]
Option to expect no warnings

4 years agoAdd to changelog
Miodrag Milanovic [Mon, 17 Feb 2020 14:08:35 +0000 (15:08 +0100)]
Add to changelog

4 years agoNo new error if already failing
Miodrag Milanovic [Mon, 17 Feb 2020 11:54:36 +0000 (12:54 +0100)]
No new error if already failing

4 years agocoolrunner2: Use extract_counter to optimize counters
R. Ou [Mon, 17 Feb 2020 11:07:16 +0000 (03:07 -0800)]
coolrunner2: Use extract_counter to optimize counters

This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC