Clifford Wolf [Fri, 20 May 2016 14:48:50 +0000 (16:48 +0200)]
Merge branch 'master' of https://github.com/Kmanfi/yosys
Clifford Wolf [Fri, 20 May 2016 14:43:13 +0000 (16:43 +0200)]
Also escape "=" in spice output
Clifford Wolf [Fri, 20 May 2016 14:21:35 +0000 (16:21 +0200)]
Small improvements in Verilog front-end docs
Kaj Tuomi [Thu, 19 May 2016 08:53:29 +0000 (11:53 +0300)]
Close opened dump file.
Kaj Tuomi [Thu, 19 May 2016 08:34:38 +0000 (11:34 +0300)]
Fix for Modelsim transcript line warp issue #164
Clifford Wolf [Sat, 14 May 2016 22:05:30 +0000 (00:05 +0200)]
Don't sign-extend memory bram initialization data
Clifford Wolf [Sat, 14 May 2016 09:43:20 +0000 (11:43 +0200)]
Added missing "#define HASHLIB_H"
Clifford Wolf [Sat, 14 May 2016 09:35:39 +0000 (11:35 +0200)]
Minor presentation fixes
Clifford Wolf [Wed, 11 May 2016 07:31:53 +0000 (09:31 +0200)]
Updated min GCC requirement to GCC 4.8
Clifford Wolf [Mon, 9 May 2016 10:43:49 +0000 (12:43 +0200)]
Added manual download link to README
Clifford Wolf [Sun, 8 May 2016 08:50:39 +0000 (10:50 +0200)]
Include <cmath> in yosys.h
Clifford Wolf [Sun, 8 May 2016 08:22:01 +0000 (10:22 +0200)]
Merge pull request #162 from azonenberg/master
Added GP_DELAY cell. Fixed several errors in simulation models.
Andrew Zonenberg [Sun, 8 May 2016 04:29:26 +0000 (21:29 -0700)]
Added GP_DELAY cell
Andrew Zonenberg [Sun, 8 May 2016 04:14:42 +0000 (21:14 -0700)]
Fixed typo in port name
Andrew Zonenberg [Sun, 8 May 2016 04:14:18 +0000 (21:14 -0700)]
Fixed extra semicolon
Andrew Zonenberg [Sun, 8 May 2016 04:14:00 +0000 (21:14 -0700)]
Fixed typo in parameter name
Andrew Zonenberg [Sun, 8 May 2016 04:13:47 +0000 (21:13 -0700)]
Added simulation timescale declaration
Clifford Wolf [Sat, 7 May 2016 08:53:18 +0000 (10:53 +0200)]
Fixes for MXE build
Clifford Wolf [Sat, 7 May 2016 07:33:16 +0000 (09:33 +0200)]
Added support for "keep" attribute to shregmap
Clifford Wolf [Fri, 6 May 2016 21:02:37 +0000 (23:02 +0200)]
Added synth_ice40 support for latches via logic loops
Clifford Wolf [Fri, 6 May 2016 13:05:53 +0000 (15:05 +0200)]
Added "write_blif -noalias"
Clifford Wolf [Fri, 6 May 2016 12:32:32 +0000 (14:32 +0200)]
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
Clifford Wolf [Fri, 6 May 2016 11:59:30 +0000 (13:59 +0200)]
Fixed preservation of important attributes in techmap
Clifford Wolf [Thu, 5 May 2016 16:18:48 +0000 (18:18 +0200)]
Merge pull request #159 from azonenberg/master
Fixes to use new I/O pad techmapping, renamed ports for GP_SHREG
Andrew Zonenberg [Thu, 5 May 2016 00:13:54 +0000 (17:13 -0700)]
Changed order of passes for better handling of INIT attributes on "output reg" FFs
Andrew Zonenberg [Thu, 5 May 2016 00:04:50 +0000 (17:04 -0700)]
Changed port names in greenpak shregmap
Andrew Zonenberg [Thu, 5 May 2016 00:03:45 +0000 (17:03 -0700)]
Renamed module parameter
Andrew Zonenberg [Wed, 4 May 2016 22:55:16 +0000 (15:55 -0700)]
Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract
Clifford Wolf [Wed, 4 May 2016 20:48:02 +0000 (22:48 +0200)]
Added tristate buffer support to iopadmap
Clifford Wolf [Wed, 4 May 2016 17:12:59 +0000 (19:12 +0200)]
Merge pull request #157 from azonenberg/master
Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak
Andrew Zonenberg [Wed, 4 May 2016 15:06:18 +0000 (08:06 -0700)]
Fixed incorrect signal naming in GP_IOBUF
Andrew Zonenberg [Wed, 4 May 2016 14:23:27 +0000 (07:23 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Wed, 4 May 2016 08:48:42 +0000 (10:48 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 4 May 2016 08:48:23 +0000 (10:48 +0200)]
Fixed iopadmap attribute handling
Andrew Zonenberg [Wed, 4 May 2016 05:53:29 +0000 (22:53 -0700)]
Added tri-state I/O extraction for GreenPak
Andrew Zonenberg [Wed, 4 May 2016 05:03:04 +0000 (22:03 -0700)]
Added GreenPak I/O buffer cells
Andrew Zonenberg [Tue, 3 May 2016 03:29:39 +0000 (20:29 -0700)]
Added comment to clarify GP_ABUF cell
Andrew Zonenberg [Tue, 3 May 2016 03:27:41 +0000 (20:27 -0700)]
Added GP_ABUF cell
Clifford Wolf [Mon, 2 May 2016 07:49:07 +0000 (09:49 +0200)]
Merge pull request #154 from azonenberg/master
Add GP_PGA cell
Andrew Zonenberg [Sun, 1 May 2016 17:07:21 +0000 (10:07 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Fri, 29 Apr 2016 08:26:22 +0000 (10:26 +0200)]
Improved TCL_VERSION detection so it does not read .tclshrc
Andrew Zonenberg [Fri, 29 Apr 2016 07:57:37 +0000 (00:57 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Thu, 28 Apr 2016 21:17:30 +0000 (23:17 +0200)]
Added "qwp -v"
Andrew Zonenberg [Thu, 28 Apr 2016 06:07:21 +0000 (23:07 -0700)]
Added GP_PGA cell
Clifford Wolf [Tue, 26 Apr 2016 17:49:05 +0000 (19:49 +0200)]
Connections between inputs and inouts are driven by the input
Clifford Wolf [Mon, 25 Apr 2016 14:37:11 +0000 (16:37 +0200)]
Fixed test_autotb for modules with many cell ports
Clifford Wolf [Mon, 25 Apr 2016 08:43:04 +0000 (10:43 +0200)]
Fixed proc_mux performance bug
Clifford Wolf [Mon, 25 Apr 2016 08:33:18 +0000 (10:33 +0200)]
Merge pull request #150 from azonenberg/master
GreenPak analog comparator support
Andrew Zonenberg [Mon, 25 Apr 2016 05:11:56 +0000 (22:11 -0700)]
Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Mon, 25 Apr 2016 00:01:21 +0000 (17:01 -0700)]
Removed VIN_BUF_EN
Clifford Wolf [Sun, 24 Apr 2016 17:29:56 +0000 (19:29 +0200)]
Fixed performance bug in proc_dlatch
Clifford Wolf [Sun, 24 Apr 2016 15:12:34 +0000 (17:12 +0200)]
Added "yosys -D ALL"
Andrew Zonenberg [Sun, 24 Apr 2016 05:53:49 +0000 (22:53 -0700)]
Renamed VOUT to OUT on GP_ACMP cell
Andrew Zonenberg [Sun, 24 Apr 2016 05:33:36 +0000 (22:33 -0700)]
Added GP_ACMP cell
Clifford Wolf [Sat, 23 Apr 2016 22:48:33 +0000 (00:48 +0200)]
Added "prep -flatten" and "synth -flatten"
Clifford Wolf [Sat, 23 Apr 2016 22:48:06 +0000 (00:48 +0200)]
Converted "prep" to ScriptPass
Clifford Wolf [Sat, 23 Apr 2016 21:10:13 +0000 (23:10 +0200)]
Improvements in greenpak4 shreg mapping
Clifford Wolf [Sat, 23 Apr 2016 21:09:45 +0000 (23:09 +0200)]
Run clean after splitnets in synth_greenpak4
Andrew Zonenberg [Sat, 23 Apr 2016 19:22:08 +0000 (12:22 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sat, 23 Apr 2016 18:20:21 +0000 (20:20 +0200)]
Added "shregmap -zinit" for greenpak4 tech
Andrew Zonenberg [Sat, 23 Apr 2016 17:18:15 +0000 (10:18 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sat, 23 Apr 2016 08:33:32 +0000 (10:33 +0200)]
Merge https://github.com/azonenberg/yosys
Clifford Wolf [Sat, 23 Apr 2016 08:31:19 +0000 (10:31 +0200)]
Added "shregmap" to synth_greenpak4
Clifford Wolf [Sat, 23 Apr 2016 08:27:33 +0000 (10:27 +0200)]
Converted synth_greenpak4 to ScriptPass
Andrew Zonenberg [Sat, 23 Apr 2016 06:01:39 +0000 (23:01 -0700)]
Fixed typo in help text
Andrew Zonenberg [Sat, 23 Apr 2016 02:08:19 +0000 (19:08 -0700)]
Fixed typo
Andrew Zonenberg [Sat, 23 Apr 2016 02:07:55 +0000 (19:07 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Fri, 22 Apr 2016 17:42:08 +0000 (19:42 +0200)]
Added "shregmap -tech greenpak4"
Clifford Wolf [Fri, 22 Apr 2016 16:02:55 +0000 (18:02 +0200)]
Added support for "active high" and "active low" latches in BLIF front-end
Clifford Wolf [Fri, 22 Apr 2016 16:00:46 +0000 (18:00 +0200)]
Added support for "active high" and "active low" latches in BLIF back-end
Clifford Wolf [Fri, 22 Apr 2016 10:13:06 +0000 (12:13 +0200)]
More flexible handling of initialization values
Clifford Wolf [Thu, 21 Apr 2016 21:28:37 +0000 (23:28 +0200)]
Added "yosys -D" feature
Clifford Wolf [Thu, 21 Apr 2016 17:47:25 +0000 (19:47 +0200)]
Fixed performance bug in "share" pass
Clifford Wolf [Thu, 21 Apr 2016 13:31:54 +0000 (15:31 +0200)]
Fixed handling of parameters and const functions in casex/casez pattern
Clifford Wolf [Thu, 21 Apr 2016 11:02:56 +0000 (13:02 +0200)]
Improvements in opt_expr
Clifford Wolf [Thu, 21 Apr 2016 10:06:07 +0000 (12:06 +0200)]
Bugfix and improvements in memory_share
Andrew Zonenberg [Thu, 21 Apr 2016 03:48:19 +0000 (20:48 -0700)]
Added GP_VREF cell
Clifford Wolf [Tue, 19 Apr 2016 08:37:04 +0000 (10:37 +0200)]
Merge pull request #149 from azonenberg/master
GP_RCOSC and GP_SHREG cells plus some cleanup
Andrew Zonenberg [Tue, 19 Apr 2016 02:22:52 +0000 (19:22 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Mon, 18 Apr 2016 09:58:21 +0000 (11:58 +0200)]
Added "shregmap -params"
Clifford Wolf [Mon, 18 Apr 2016 09:44:10 +0000 (11:44 +0200)]
Added "shregmap -zinit" and "shregmap -init"
Andrew Zonenberg [Sun, 17 Apr 2016 15:15:34 +0000 (08:15 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sun, 17 Apr 2016 13:37:22 +0000 (15:37 +0200)]
Improvements in "shregmap"
Andrew Zonenberg [Sat, 16 Apr 2016 22:14:32 +0000 (15:14 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sat, 16 Apr 2016 21:20:49 +0000 (23:20 +0200)]
Added "shregmap" pass
Clifford Wolf [Sat, 16 Apr 2016 21:20:34 +0000 (23:20 +0200)]
Fixed copy&paste error in log message in lut2mux
Clifford Wolf [Sat, 16 Apr 2016 21:20:11 +0000 (23:20 +0200)]
Minor hashlib bugfix
Andrew Zonenberg [Thu, 14 Apr 2016 06:13:51 +0000 (23:13 -0700)]
Added GP_SHREG cell
Andrew Zonenberg [Thu, 14 Apr 2016 06:13:39 +0000 (23:13 -0700)]
Refactoring: alphabetized cells_sim
Andrew Zonenberg [Sat, 9 Apr 2016 08:18:02 +0000 (01:18 -0700)]
Fixed missing semicolon
Andrew Zonenberg [Sat, 9 Apr 2016 08:17:24 +0000 (01:17 -0700)]
Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Sat, 9 Apr 2016 08:17:13 +0000 (01:17 -0700)]
Added GP_RCOSC cell
Clifford Wolf [Fri, 8 Apr 2016 09:58:40 +0000 (11:58 +0200)]
Merge pull request #147 from azonenberg/master
Added GP_BANDGAP, GP_POR, GP_RINGOSC primitives
Andrew Zonenberg [Thu, 7 Apr 2016 06:42:22 +0000 (23:42 -0700)]
Fixed assertion failure for non-inferrable counters in some cases
Andrew Zonenberg [Thu, 7 Apr 2016 06:10:34 +0000 (23:10 -0700)]
Added second divider to GP_RINGOSC
Andrew Zonenberg [Thu, 7 Apr 2016 05:40:25 +0000 (22:40 -0700)]
Added GP_RINGOSC primitive
Andrew Zonenberg [Thu, 7 Apr 2016 05:31:22 +0000 (22:31 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Tue, 5 Apr 2016 11:25:23 +0000 (13:25 +0200)]
Hashlib indenting fix
Clifford Wolf [Tue, 5 Apr 2016 11:25:05 +0000 (13:25 +0200)]
Added msan origins tracking
Clifford Wolf [Tue, 5 Apr 2016 10:51:04 +0000 (12:51 +0200)]
Prefer noninverting FFs in dfflibmap
projects / yosys.git / log