Tom de Vries [Sat, 30 Dec 2017 10:44:39 +0000 (10:44 +0000)]
Fix filename in ChangeLog entry for r256042
From-SVN: r256043
Tom de Vries [Sat, 30 Dec 2017 10:31:54 +0000 (10:31 +0000)]
Fix 'memory cannot be printed' in c-c++-common/ubsan/object-size-9.c
2017-12-30 Tom de Vries <tom@codesourcery.com>
PR testsuite/83612
* c-c++-common/ubsan/object-size-9.c (t): Add alignment attribute.
From-SVN: r256042
GCC Administrator [Sat, 30 Dec 2017 00:16:12 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r256039
Jerry DeLisle [Fri, 29 Dec 2017 22:36:25 +0000 (22:36 +0000)]
re PR libfortran/83613 (Executing gfortran.dg/inquire_internal.f90 hangs on darwin after r255621)
2017-12-29 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libgfortran/83613
* io/unit.c (init_units): Don't forget to unlock the unit locks
after being inserted.
From-SVN: r256035
Jerry DeLisle [Fri, 29 Dec 2017 19:25:31 +0000 (19:25 +0000)]
re PR fortran/83560 (list-directed formatting of INTEGER is missing plus on output when output open with SIGN='PLUS')
2017-12-29 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libgfortran/83560
* io/write.c (write_integer): Modify to use write_decimal.
For namelist mode, suppress leading blanks and emit them as
trailing blanks. Change parameter from len to kind for better
readability. (nml_write_obj): Fix comment style.
From-SVN: r256034
Paul Thomas [Fri, 29 Dec 2017 14:27:59 +0000 (14:27 +0000)]
re PR fortran/83567 (Parametrized derived types: Segmentation fault when assigning a function return value)
2017-12-28 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83567
* trans-expr.c (gfc_trans_assignment_1): Free parameterized
components of the lhs if dealloc is set.
*trans-decl.c (gfc_trans_deferred_vars): Do not free the
parameterized components of function results on leaving scope.
2017-12-28 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83567
* gfortran.dg/pdt_26.f90 : New test.
From-SVN: r256033
Uros Bizjak [Fri, 29 Dec 2017 11:23:14 +0000 (12:23 +0100)]
namedret2.C (f): Return a value.
* g++.old-deja/g++.ext/namedret2.C (f): Return a value.
From-SVN: r256032
Uros Bizjak [Fri, 29 Dec 2017 11:21:10 +0000 (12:21 +0100)]
namedret1.C (f): Return a value.
* g++.old-deja/g++.ext/namedret1.C (f): Return a value.
From-SVN: r256031
GCC Administrator [Fri, 29 Dec 2017 00:16:13 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r256030
Michael Meissner [Thu, 28 Dec 2017 21:19:12 +0000 (21:19 +0000)]
builtins.def: (_Float<N> and _Float<N>X BUILT_IN_CEIL): Add _Float<N> and _Float<N>X variants...
[gcc]
2017-12-28 Michael Meissner <meissner@linux.vnet.ibm.com>
* builtins.def: (_Float<N> and _Float<N>X BUILT_IN_CEIL): Add
_Float<N> and _Float<N>X variants for rounding built-in
functions.
(_Float<N> and _Float<N>X BUILT_IN_FLOOR): Likewise.
(_Float<N> and _Float<N>X BUILT_IN_NEARBYINT): Likewise.
(_Float<N> and _Float<N>X BUILT_IN_RINT): Likewise.
(_Float<N> and _Float<N>X BUILT_IN_ROUND): Likewise.
(_Float<N> and _Float<N>X BUILT_IN_TRUNC): Likewise.
* builtins.c (mathfn_built_in_2): Likewise.
* internal-fn.def (CEIL): Likewise.
(FLOOR): Likewise.
(NEARBYINT): Likewise.
(RINT): Likewise.
(ROUND): Likewise.
(TRUNC): Likewise.
* convert.c (convert_to_integer_1): Likewise.
* fold-const.c (tree_call_nonnegative_warnv_p): Likewise.
(integer_valued_real_call_p): Likewise.
* fold-const-call.c (fold_const_call_ss): Likewise.
* gencfn-macros.c (print_case_cfn): Change CFN and operator
printers to take a const char * suffix instead of a bool.
(print_define_operator_list): Likewise.
(fltall_suffixes): New list of suffixes, that include the
traditional suffixes as well as all of the _Float<N> and
_Float<N>X suffixes.
(main): For _Float<N> and _Float<N>X functions, emit both
<name>_FN and <name>_ALL variants. The <macro>_FN variant only
has the _Float<N> and _Float<N>X case names or operators. The
<name>_ALL variant has both the traditional and the
_Float<N>/_Float<N>X case names or operators.
* match.pd (COPYSIGN optimizations): Provide optimizations for
_Float<N> and _Float<N>X types where possible.
(MIN/MAX optimizations): Likewise.
(sqrt optimizations): Likewise.
(rounding optimizations): Likewise.
[gcc/c]
2017-12-28 Michael Meissner <meissner@linux.vnet.ibm.com>
* c-decl.c (header_for_builtin_fn): Add integer rounding _Float<N>
and _Float<N>X built-in functions.
From-SVN: r256026
Richard Sandiford [Thu, 28 Dec 2017 20:42:43 +0000 (20:42 +0000)]
[rs6000] Use gen_int_mode in ieee_128bit_negative_zero
Previously we'd generate a non-canonical zero-extended CONST_INT
instead of a sign-extended one, which tripped the assert for
canonical CONST_INTs after a later patch.
2017-12-28 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/powerpcspe/powerpcspe.md (ieee_128bit_negative_zero): Use
gen_int_mode rather than GEN_INT.
* config/rs6000/rs6000.md (ieee_128bit_negative_zero): Likewise.
From-SVN: r256024
Richard Sandiford [Thu, 28 Dec 2017 20:40:20 +0000 (20:40 +0000)]
Use valid_for_const_vector_p instead of CONSTANT_P
This patch makes the VEC_SERIES code use valid_for_const_vector_p
instead of CONSTANT_P, to match what we already do for VEC_DUPLICATE.
This showed up as a failure in gcc.c-torture/execute/pr28982b.c for -m32
on x86_64-linux-gnu after later patches.
2017-12-28 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* emit-rtl.c (gen_const_vec_series): Use valid_for_const_vector_p
instead of CONSTANT_P.
(gen_vec_series): Likewise.
* simplify-rtx.c (simplify_binary_operation_1): Likewise.
From-SVN: r256023
Steven G. Kargl [Thu, 28 Dec 2017 20:19:01 +0000 (20:19 +0000)]
re PR fortran/83548 (Compilation Error using logical function in parameter)
2017-12-28 Steven G. Kargl <kargl@gcc.gnu.org>
PR Fortran/83548
* match.c (gfc_match_type_spec): Check for LOGICAL conflict in
type-spec versus LOGICAL intrinsic subprogram.
2017-12-28 Steven G. Kargl <kargl@gcc.gnu.org>
PR Fortran/83548
* gfortran.dg/array_constructor_type_22.f03: New test.
From-SVN: r256022
Janne Blomqvist [Thu, 28 Dec 2017 18:49:12 +0000 (20:49 +0200)]
PR fortran/83344 Don't set bogus constant value
This patch does not fix PR 83344, but merely fixes an error where we
used to set a constant character length value from a non-constant
expression, and thus set it to some bogus value.
As a result of this, I have commented out part of the associate_22.f90
test which otherwise generates a warning message.
Regtested on x86_64-pc-linux-gnu.
gcc/fortran/ChangeLog:
2017-12-28 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/83344
* resolve.c (resolve_assoc_var): Don't set the constant value
unless the target is a constant expression.
gcc/testsuite/ChangeLog:
2017-12-28 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/83344
* gfortran.dg/associate_22.f90: Comment out part of test.
From-SVN: r256021
Andreas Schwab [Thu, 28 Dec 2017 16:28:44 +0000 (16:28 +0000)]
m68k.md (ashrdi3_const1, [...]): Add CC_STATUS_INIT.
* config/m68k/m68k.md (ashrdi3_const1, lshrdi3_const1): Add
CC_STATUS_INIT.
From-SVN: r256020
Paul Thomas [Thu, 28 Dec 2017 13:22:36 +0000 (13:22 +0000)]
re PR fortran/83567 (Parametrized derived types: Segmentation fault when assigning a function return value)
2017-12-28 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83567
* trans-expr.c (gfc_trans_assignment_1): Free parameterized
components of the lhs if dealloc is set.
*trans-decl.c (gfc_trans_deferred_vars): Do not free the
parameterized components of function results on leaving scope.
2017-12-28 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83567
* gfortran.dg/pdt_26.f90 : New test.
From-SVN: r256019
GCC Administrator [Thu, 28 Dec 2017 00:16:12 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r256017
Jonathan Wakely [Wed, 27 Dec 2017 22:18:08 +0000 (22:18 +0000)]
PR libstdc++/83600 fix end iterator for unready std::match_results
PR libstdc++/83600
* include/bits/regex.h (match_results::end()): Return valid iterator
when not ready.
* testsuite/28_regex/match_results/ctors/char/default.cc: Check that
unready objects are empty and have equal begin and end iterators.
* testsuite/28_regex/match_results/ctors/wchar_t/default.cc: Likewise.
From-SVN: r256014
Jonathan Wakely [Wed, 27 Dec 2017 22:18:02 +0000 (22:18 +0000)]
PR libstdc++/83598 don't modify flags passed to std::basic_regex constructors
PR libstdc++/83598
* include/bits/regex.h (basic_regex): Don't modify flags passed to
constructors.
* testsuite/28_regex/basic_regex/ctors/83598.cc: New test.
From-SVN: r256013
Jonathan Wakely [Wed, 27 Dec 2017 19:43:33 +0000 (19:43 +0000)]
PR libstdc++/83538 fix std::match_results<T>::reference (LWG 2306)
PR libstdc++/83538
* doc/xml/manual/intro.xml: Document LWG 2306 change.
* include/bits/regex.h (match_results::reference): Change to
non-const reference.
* testsuite/28_regex/match_results/typedefs.cc: Check types are
correct.
From-SVN: r256012
Louis Krupp [Wed, 27 Dec 2017 19:20:12 +0000 (19:20 +0000)]
2017_12_27 Louis Krupp <louis.krupp@zoho.com>
PR fortran/83092
* expr.c (gfc_apply_init): Check that typespec has character type
before using character length field.
2017_12_27 Louis Krupp <louis.krupp@zoho.com>
PR fortran/83092
* gfortran.dg/init_char_with_nonchar_ctr.f90: New test.
From-SVN: r256011
Kugan Vivekanandarajah [Wed, 27 Dec 2017 11:47:45 +0000 (11:47 +0000)]
aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
gcc/ChangeLog:
2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/aarch64/aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
(aarch64_ld1x2<VDC:mode>): Likewise.
(aarch64_simd_ld1<mode>_x2): Likewise.
(aarch64_simd_ld1<mode>_x2): Likewise.
* config/aarch64/arm_neon.h (vld1_u8_x2): New.
(vld1_s8_x2): Likewise.
(vld1_u16_x2): Likewise.
(vld1_s16_x2): Likewise.
(vld1_u32_x2): Likewise.
(vld1_s32_x2): Likewise.
(vld1_u64_x2): Likewise.
(vld1_s64_x2): Likewise.
(vld1_f16_x2): Likewise.
(vld1_f32_x2): Likewise.
(vld1_f64_x2): Likewise.
(vld1_p8_x2): Likewise.
(vld1_p16_x2): Likewise.
(vld1_p64_x2): Likewise.
(vld1q_u8_x2): Likewise.
(vld1q_s8_x2): Likewise.
(vld1q_u16_x2): Likewise.
(vld1q_s16_x2): Likewise.
(vld1q_u32_x2): Likewise.
(vld1q_s32_x2): Likewise.
(vld1q_u64_x2): Likewise.
(vld1q_s64_x2): Likewise.
(vld1q_f16_x2): Likewise.
(vld1q_f32_x2): Likewise.
(vld1q_f64_x2): Likewise.
(vld1q_p8_x2): Likewise.
(vld1q_p16_x2): Likewise.
(vld1q_p64_x2): Likewise.
gcc/testsuite/ChangeLog:
2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: New test.
From-SVN: r256010
Martin Liska [Wed, 27 Dec 2017 09:30:14 +0000 (10:30 +0100)]
Assign result of get_string_lenth to a SSA_NAME (PR tree-optimization/83552).
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
* tree-ssa-strlen.c (fold_strstr_to_strncmp): Assign result
of get_string_lenth to a SSA_NAME if not a GIMPLE value.
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
* gcc.dg/pr83552.c: New test.
From-SVN: r256009
Tom de Vries [Wed, 27 Dec 2017 07:50:04 +0000 (07:50 +0000)]
Workaround PR83046 in gang-static-2.c
2017-12-27 Tom de Vries <tom@codesourcery.com>
PR c++/83046
* testsuite/libgomp.oacc-c-c++-common/gang-static-2.c (test_static)
(test_nonstatic): Fix return type to workaround PR83046.
From-SVN: r256008
Tom de Vries [Wed, 27 Dec 2017 07:49:51 +0000 (07:49 +0000)]
Disable -gstatement-frontiers for nvptx
2017-12-27 Tom de Vries <tom@codesourcery.com>
* config/nvptx/nvptx.c (nvptx_option_override): Disable
-gstatement-frontiers.
From-SVN: r256007
GCC Administrator [Wed, 27 Dec 2017 00:16:12 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r256006
Thomas Koenig [Tue, 26 Dec 2017 23:29:20 +0000 (23:29 +0000)]
re PR fortran/83540 (Invalid code with MATMUL, -fno-realloc-lhs -ffrontend-optimize)
2017-12-26 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/83540
* frontend-passes.c (create_var): If an array to be created
has unknown size and -fno-realloc-lhs is in effect,
return NULL.
2017-12-26 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/83540
* gfortran.dg/inline_matmul_20.f90: New test.
From-SVN: r256003
Tom de Vries [Tue, 26 Dec 2017 16:56:22 +0000 (16:56 +0000)]
Use relative line number in unroll-5.c
2017-12-26 Tom de Vries <tom@codesourcery.com>
* c-c++-common/unroll-5.c: Use relative line number.
From-SVN: r256002
Alexander Monakov [Tue, 26 Dec 2017 14:34:33 +0000 (17:34 +0300)]
sel-sched: fix zero-usefulness case in sel_rank_for_schedule (PR 83513)
PR rtl-optimization/83513
* sel-sched.c (sel_rank_for_schedule): Order by non-zero usefulness
before priority comparison.
From-SVN: r256001
GCC Administrator [Tue, 26 Dec 2017 00:16:15 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r256000
Jakub Jelinek [Mon, 25 Dec 2017 11:59:17 +0000 (12:59 +0100)]
re PR target/83488 (ICE on a CET test-case)
PR target/83488
* config/i386/i386.opt (-mavx512vpopcntdq, -mmavx512bitalg): Move from
ix86_isa_flags2 to ix86_isa_flags.
* config/i386/i386-c.c (ix86_target_macros_internal): Test
OPTION_MASK_ISA_AVX512BITALG and OPTION_MASK_ISA_AVX512VPOPCNTDQ in
isa_flags rather than isa_flags2.
* config/i386/i386.c (ix86_target_string): Move -mavx512vpopcntdq
and -mavx512bitalg from isa2_opts to isa_opts.
(ix86_option_override_internal): Test OPTION_MASK_ISA_AVX512VPOPCNTDQ
in x_ix86_isa_flags_explicit rather than x_ix86_isa_flags2_explicit
and set it in x_ix86_isa_flags rather than x_ix86_isa_flags2.
Formatting fixes.
(def_builtin): Treat OPTION_MASK_ISA_AVX512BW or
OPTION_MASK_ISA_AVX512F ored with another option similarly to
OPTION_MASK_ISA_AVX512VL. Even for OPTION_MASK_ISA_AVX512VL don't
clear it if mask is just OPTION_MASK_ISA_AVX512VL itself.
(ix86_expand_builtin): Don't handle OPTION_MASK_ISA_GFNI and
OPTION_MASK_ISA_VPCLMULQDQ specially, instead handle
OPTION_MASK_ISA_AVX512BW and OPTION_MASK_ISA_AVX512F that way.
* config/i386/i386-builtin.def: Move AVX512VPOPCNTDQ and AVX512BITALG
builtins from bdesc_args2 to bdesc_args section.
(__builtin_ia32_compressstoreuqi512_mask,
__builtin_ia32_compressstoreuhi512_mask,
__builtin_ia32_compressstoreuqi256_mask,
__builtin_ia32_expandloadqi512_mask,
__builtin_ia32_expandloadqi512_maskz,
__builtin_ia32_expandloadhi512_mask,
__builtin_ia32_expandloadhi512_maskz,
__builtin_ia32_compressqi512_mask, __builtin_ia32_compresshi512_mask,
__builtin_ia32_compressqi256_mask, __builtin_ia32_expandqi512_mask,
__builtin_ia32_expandqi512_maskz, __builtin_ia32_expandhi512_mask,
__builtin_ia32_expandhi512_maskz, __builtin_ia32_expandqi256_mask,
__builtin_ia32_expandqi256_maskz, __builtin_ia32_vpshrd_v32hi_mask,
__builtin_ia32_vpshld_v32hi_mask, __builtin_ia32_vpshrdv_v32hi_mask,
__builtin_ia32_vpshrdv_v32hi_maskz, __builtin_ia32_vpshldv_v32hi_mask,
__builtin_ia32_vpshldv_v32hi_maskz,
__builtin_ia32_vpopcountb_v64qi_mask,
__builtin_ia32_vpopcountw_v32hi_mask,
__builtin_ia32_vpshufbitqmb512_mask,
__builtin_ia32_vpshufbitqmb256_mask): Add
" | OPTION_MASK_ISA_AVX512BW".
(__builtin_ia32_expandloadqi256_mask,
__builtin_ia32_expandloadqi256_maskz,
__builtin_ia32_vpopcountb_v32qi_mask): Add
" | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW".
(__builtin_ia32_expandloadhi256_mask,
__builtin_ia32_expandloadhi256_maskz,
__builtin_ia32_expandloadqi128_mask,
__builtin_ia32_expandloadqi128_maskz,
__builtin_ia32_expandloadhi128_mask,
__builtin_ia32_expandloadhi128_maskz,
__builtin_ia32_vpshrd_v16hi, __builtin_ia32_vpshrd_v16hi_mask,
__builtin_ia32_vpshrd_v8hi, __builtin_ia32_vpshrd_v8hi_mask,
__builtin_ia32_vpshrd_v8si, __builtin_ia32_vpshrd_v8si_mask,
__builtin_ia32_vpshrd_v4si, __builtin_ia32_vpshrd_v4si_mask,
__builtin_ia32_vpshrd_v4di, __builtin_ia32_vpshrd_v4di_mask,
__builtin_ia32_vpshrd_v2di, __builtin_ia32_vpshrd_v2di_mask,
__builtin_ia32_vpshld_v16hi, __builtin_ia32_vpshld_v16hi_mask,
__builtin_ia32_vpshld_v8hi, __builtin_ia32_vpshld_v8hi_mask,
__builtin_ia32_vpshld_v8si, __builtin_ia32_vpshld_v8si_mask,
__builtin_ia32_vpshld_v4si, __builtin_ia32_vpshld_v4si_mask,
__builtin_ia32_vpshld_v4di, __builtin_ia32_vpshld_v4di_mask,
__builtin_ia32_vpshld_v2di, __builtin_ia32_vpshld_v2di_mask,
__builtin_ia32_vpshrdv_v16hi, __builtin_ia32_vpshrdv_v16hi_mask,
__builtin_ia32_vpshrdv_v16hi_maskz, __builtin_ia32_vpshrdv_v8hi,
__builtin_ia32_vpshrdv_v8hi_mask, __builtin_ia32_vpshrdv_v8hi_maskz,
__builtin_ia32_vpshrdv_v8si, __builtin_ia32_vpshrdv_v8si_mask,
__builtin_ia32_vpshrdv_v8si_maskz, __builtin_ia32_vpshrdv_v4si,
__builtin_ia32_vpshrdv_v4si_mask, __builtin_ia32_vpshrdv_v4si_maskz,
__builtin_ia32_vpshrdv_v4di, __builtin_ia32_vpshrdv_v4di_mask,
__builtin_ia32_vpshrdv_v4di_maskz, __builtin_ia32_vpshrdv_v2di,
__builtin_ia32_vpshrdv_v2di_mask, __builtin_ia32_vpshrdv_v2di_maskz,
__builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask,
__builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi,
__builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz,
__builtin_ia32_vpshldv_v8si, __builtin_ia32_vpshldv_v8si_mask,
__builtin_ia32_vpshldv_v8si_maskz, __builtin_ia32_vpshldv_v4si,
__builtin_ia32_vpshldv_v4si_mask, __builtin_ia32_vpshldv_v4si_maskz,
__builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask,
__builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di,
__builtin_ia32_vpshldv_v2di_mask, __builtin_ia32_vpshldv_v2di_maskz,
__builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v16qi,
__builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v16hi,
__builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi,
__builtin_ia32_vpopcountw_v8hi_mask): Add
" | OPTION_MASK_ISA_AVX512VL".
* config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16,
_mm512_shrdi_epi32, _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
_mm512_shrdi_epi64, _mm512_mask_shrdi_epi64, _mm512_maskz_shrdi_epi64,
_mm512_shldi_epi16, _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
_mm512_maskz_shldi_epi32, _mm512_shldi_epi64, _mm512_mask_shldi_epi64,
_mm512_maskz_shldi_epi64, _mm512_shrdv_epi16, _mm512_shrdv_epi32,
_mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64,
_mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64, _mm512_shldv_epi16,
_mm512_shldv_epi32, _mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32,
_mm512_shldv_epi64, _mm512_mask_shldv_epi64,
_mm512_maskz_shldv_epi64): Don't require avx512bw for these intrinsics.
* config/i386/avx512bitalgintrin.h (_mm_bitshuffle_epi64_mask,
_mm_mask_bitshuffle_epi64_mask): Likewise.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET,
OPTION_MASK_ISA_AVX512BITALG_SET): Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET and
OPTION_MASK_ISA_AVX512BITALG_UNSET.
(OPTION_MASK_ISA2_AVX512F_UNSET,
OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Define.
(ix86_handle_option): For -mno-general-regs-only, clear from
ix86_isa_flags2 OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET rather than
just OPTION_MASK_ISA_MPX. For -mno-sse{,2,3,4,4.1,4.2,avx,avx2} and
-mno-ssse3 clear OPTION_MASK_ISA2_AVX512F_UNSET bits from
ix86_isa_flags2. For -mno-avx512f likewise, instead of masking
individually listed ISAs. For -m{,no-}avx512{vpopcntdq,bitalg} adjust
for moving from ix86_isa_flags2 to ix86_isa_flags.
From-SVN: r255997
GCC Administrator [Mon, 25 Dec 2017 00:16:17 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r255996
Michele Pezzutti [Sun, 24 Dec 2017 22:08:52 +0000 (23:08 +0100)]
re PR libstdc++/83237 (Values returned by std::poisson_distribution are not distributed correctly)
2017-12-24 Michele Pezzutti <mpezz@tiscali.it>
PR libstdc++/83237
* include/bits/random.tcc (poisson_distribution<>::operator()):
Fix __x = 1 case - see updated Errata of Devroye's treatise.
* testsuite/26_numerics/random/poisson_distribution/operators/
values.cc: Add test.
* testsuite/26_numerics/random/pr60037-neg.cc: Adjust dg-error
line number.
From-SVN: r255993
Jonathan Wakely [Sun, 24 Dec 2017 09:17:38 +0000 (09:17 +0000)]
PR libstdc++/83450 avoid -Wreturn-type warning in test
PR libstdc++/83450
* testsuite/21_strings/basic_string/pthread18185.cc: Add return
statement.
From-SVN: r255992
GCC Administrator [Sun, 24 Dec 2017 00:16:16 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r255991
Jakub Jelinek [Sat, 23 Dec 2017 08:40:19 +0000 (09:40 +0100)]
re PR c++/83553 (compiler removes body of the for-loop, although there is a case label inside)
PR c++/83553
* fold-const.c (struct contains_label_data): New type.
(contains_label_1): Return non-NULL even for CASE_LABEL_EXPR, unless
inside of a SWITCH_BODY seen during the walk.
(contains_label_p): Use walk_tree instead of
walk_tree_without_duplicates, prepare data for contains_label_1 and
provide own pset.
* c-c++-common/torture/pr83553.c: New test.
From-SVN: r255987
GCC Administrator [Sat, 23 Dec 2017 00:16:12 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r255986
Jakub Jelinek [Fri, 22 Dec 2017 18:04:18 +0000 (19:04 +0100)]
re PR debug/83550 (Bad location of DW_TAG_structure_type with forward declaration since r224161)
PR debug/83550
* c-decl.c (finish_struct): Set DECL_SOURCE_LOCATION on
TYPE_STUB_DECL and call rest_of_type_compilation before processing
incomplete vars rather than after it.
* c-c++-common/dwarf2/pr83550.c: New test.
From-SVN: r255981
Jakub Jelinek [Fri, 22 Dec 2017 18:01:58 +0000 (19:01 +0100)]
re PR debug/83547 ((statement-frontiers) error: void value not ignored as it ought to be)
PR debug/83547
* tree-iterator.c (alloc_stmt_list): Start with cleared
TREE_SIDE_EFFECTS regardless whether a new STATEMENT_LIST is allocated
or old one reused.
c/
* c-typeck.c (c_finish_stmt_expr): Ignore !TREE_SIDE_EFFECTS as
indicator of ({ }), instead skip all trailing DEBUG_BEGIN_STMTs first,
and consider empty ones if there are no other stmts. For
-Wunused-value walk all statements before the one only followed by
DEBUG_BEGIN_STMTs.
testsuite/
* gcc.c-torture/compile/pr83547.c: New test.
From-SVN: r255980
Jakub Jelinek [Fri, 22 Dec 2017 18:00:41 +0000 (19:00 +0100)]
re PR target/83488 (ICE on a CET test-case)
PR target/83488
* config/i386/avx512vnniintrin.h: Don't check for __AVX512F__ nor
enable avx512f explicitly in #pragma GCC target.
* config/i386/i386-builtin.def (__builtin_ia32_vpdpbusd_v8si,
__builtin_ia32_vpdpbusd_v8si_mask, __builtin_ia32_vpdpbusd_v8si_maskz,
__builtin_ia32_vpdpbusd_v4si, __builtin_ia32_vpdpbusd_v4si_mask,
__builtin_ia32_vpdpbusd_v4si_maskz, __builtin_ia32_vpdpbusds_v8si,
__builtin_ia32_vpdpbusds_v8si_mask,
__builtin_ia32_vpdpbusds_v8si_maskz, __builtin_ia32_vpdpbusds_v4si,
__builtin_ia32_vpdpbusds_v4si_mask,
__builtin_ia32_vpdpbusds_v4si_maskz, __builtin_ia32_vpdpwssd_v8si,
__builtin_ia32_vpdpwssd_v8si_mask, __builtin_ia32_vpdpwssd_v8si_maskz,
__builtin_ia32_vpdpwssd_v4si, __builtin_ia32_vpdpwssd_v4si_mask,
__builtin_ia32_vpdpwssd_v4si_maskz, __builtin_ia32_vpdpwssds_v8si,
__builtin_ia32_vpdpwssds_v8si_mask,
__builtin_ia32_vpdpwssds_v8si_maskz, __builtin_ia32_vpdpwssds_v4si,
__builtin_ia32_vpdpwssds_v4si_mask,
__builtin_ia32_vpdpwssds_v4si_maskz): Use
OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL instead of
just OPTION_MASK_ISA_AVX512VNNI.
* gcc.target/i386/pr83488-2.c: New test.
* gcc.target/i386/pr83488-3.c: New test.
From-SVN: r255979
Martin Jambor [Fri, 22 Dec 2017 17:03:16 +0000 (18:03 +0100)]
[PR 82027] Also stream opt_info of former_clones
2017-12-22 Martin Jambor <mjambor@suse.cz>
PR lto/82027
* lto-cgraph.c (output_cgraph_opt_summary_p): Also check former
clones.
testsuite/
* g++.dg/lto/pr82027_0.C: New test.
From-SVN: r255978
Ian Lance Taylor [Fri, 22 Dec 2017 16:43:28 +0000 (16:43 +0000)]
compiler: do not propagate address-taken of a slice element to the slice
Array_index_expression may be used for indexing/slicing array or
slice. If a slice element is address taken, the slice itself is
not necessarily address taken. Only propagate address-taken for
arrays.
Reviewed-on: https://go-review.googlesource.com/83877
From-SVN: r255977
Ian Lance Taylor [Fri, 22 Dec 2017 15:55:10 +0000 (15:55 +0000)]
compiler: bring escape analysis mostly in line with gc compiler
This CL ports the latest (~Go 1.10) escape analysis code from
the gc compiler. Changes include:
- In the gc compiler, the variable expression is represented
with the variable node itself (ONAME). It is the same node
used in the AST for multiple var expressions for the same
variable. In our case, the var expressions nodes are distinct
nodes. We need to propagate the escape state from/to the
underlying variable in getter and setter. We already do it in
the setter. Do it in the getter as well.
- At the point of escape analysis, some AST constructs have not
been lowered to runtime calls, for example, map literal
construction and some builtin calls. Change the analysis to
work on the non-lowered AST constructs instead of call
expressions for them. For this to work, the analysis needs to
look into Builtin_call_expression. Move its class definition
from expressions.cc to expressions.h, and add necessary
accessors. Also fix bugs in other runtime call handlings
(selectsend, ifaceX2Y2, etc.).
- Handle closures properly. The analysis tracks the function
reference expression, and the escape state is propagated to
the underlying heap expression for get_backend to do stack
allocation for non-escaping closures.
- Fix add_dereference. Before, this was doing expr->deref(),
which undoes an indirection instead of add one. In the gc
compiler, it adds a level of indirection, which is modeled as
an OIND node regardless of the type of the expression. We
can't do this for non-pointer typed expression, otherwise it
will result in a type error. Instead, we model it with a
special flavor of Node, "indirect". The flood phase handles
this by incrementing its level.
- Slicing of an array was not handled correctly. The gc compiler
has an implicit (compiler inserted) OADDR node for the array,
so the analysis is actually performed on the address of the
array. We don't have this implicit address-of expression in
the AST. Instead, we model this by adding an implicit child to
the Node of the Array_index_expression representing slicing of
an array.
- Array_index_expression may represent indexing or slicing. The
code distinguishes them by looking at whether the type of the
expression is a slice. This does not work if the slice element
is a slice. Instead, check whether its end() is NULL.
- Temporary references was handled only in a limited case, as
part of address-of expression. This CL handles it in general.
The analysis uses the Temporary_statement as the point of
tracking, and forwards Temporary_reference_expression to the
underlying statement when needed.
- Handle call return value flows, escpecially multiple return
values. This includes porting part of CL 8202, CL 20102, and
other fixes.
- Support go:noescape pragma.
- Add special handling for self assignment like
b.buf = b.buf[m:n]. (CL 3162)
- Remove ESCAPE_SCOPE, which was treated essentially the same as
ESCAPE_HEAP, and was removed from the gc compiler. (CL 32130)
- Run flood phase until fix point. (CL 30693)
- Unnamed parameters do not escape. (CL 38600)
- Various small bug fixes and improvements.
"make check-go" passes except the one test in math/big, when the
escape analysis is on. The escape analysis is still not run by
default.
Reviewed-on: https://go-review.googlesource.com/83876
From-SVN: r255976
Julia Koval [Fri, 22 Dec 2017 12:37:16 +0000 (13:37 +0100)]
Enable AVX512BITALG
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET,
OPTION_MASK_ISA_AVX512BITALG_UNSET): New.
(ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting.
* config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h.
* config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16,
_mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16,
_mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8,
_mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8,
_mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16,
_mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask,
_mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8,
_mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8,
_mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics.
* config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64,
_mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32,
_mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64,
_mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64,
_mm256_maskz_popcnt_epi64): New intrinsics.
* config/i386/cpuid.h (bit_AVX512BITALG): New bit.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg.
* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI,
V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI,
V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types.
* config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di,
__builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di,
__builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si,
__builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si,
__builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi,
__builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi,
__builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi,
__builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi,
__builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi,
__builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi,
__builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask,
__builtin_ia32_vpshufbitqmb256_mask,
__builtin_ia32_vpshufbitqmb512_mask): New builtins.
* config/i386/i386-c.c (__AVX512BITALG__): New.
* config/i386/i386.c (isa2_opts): Add -mavx512bitalg.
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_expand_args_builtin): Handle new types.
* config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New.
* config/i386/i386.opt: Add -mavx512bitalg.
* config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and
avx512bitalgintrin.h.
* config/i386/sse.md (VI48_AVX512VLBW): New iterator.
(vpopcount<mode><mask_name>): Add more types.
(avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New.
* doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq.
gcc/testsuite/
* g++.dg/other/i386-2.C: Add new options.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG.
* gcc.target/i386/avx512bitalg-vpopcntb-1.c: New.
* gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto.
* gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New.
* gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types.
* gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics.
* gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto.
Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com>
From-SVN: r255975
Igor Tsimbalist [Fri, 22 Dec 2017 11:41:02 +0000 (12:41 +0100)]
This is a follow up patch for pr83488 to fix an error in setting...
This is a follow up patch for pr83488 to fix an error in setting
OPTION_MASK_ISA_AVX512VNNI_SET and OPTION_MASK_ISA_AVX512F_SET bits.
There were both set in ix86_isa_flags2 while being defined in
different ISA sets. Additionally move OPTION_MASK_ISA_AVX512VNNI_SET
to ix86_isa_flags as it can be used with OPTION_MASK_ISA_AVX512VL_SET.
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VNNI_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_AVX512VNNI_*SET being in ix86_isa_flags.
* config/i386/i386-builtin.def: Move VNNI builtins from ARGS2
section to ARGS.
* config/i386/i386-c.c: Check for OPTION_MASK_ISA_AVX512VNNI in
isa_flag instead of isa_flag2.
* config/i386/i386.c (ix86_target_string): Move -mavx512vnni from
isa_opts2 to isa_opts.
* config/i386/i386.opt (mavx512vnni): Move from ix86_isa_flags2
to ix86_isa_flags.
From-SVN: r255974
Eric Botcazou [Fri, 22 Dec 2017 10:22:15 +0000 (10:22 +0000)]
extend.texi (Loop-Specific Pragmas): Document pragma GCC unroll.
* doc/extend.texi (Loop-Specific Pragmas): Document pragma GCC unroll.
c-family/
* c-pragma.c (init_pragma): Register pragma GCC unroll.
* c-pragma.h (enum pragma_kind): Add PRAGMA_UNROLL.
c/
* c-parser.c (c_parser_while_statement): Add unroll parameter and
build ANNOTATE_EXPR if present. Add 3rd operand to ANNOTATE_EXPR.
(c_parser_do_statement): Likewise.
(c_parser_for_statement): Likewise.
(c_parser_statement_after_labels): Adjust calls to above.
(c_parse_pragma_ivdep): New static function.
(c_parser_pragma_unroll): Likewise.
(c_parser_pragma) <PRAGMA_IVDEP>: Add support for pragma Unroll.
<PRAGMA_UNROLL>: New case.
cp/
* constexpr.c (cxx_eval_constant_expression) <ANNOTATE_EXPR>: Remove
assertion on 2nd operand.
(potential_constant_expression_1): Likewise.
* cp-tree.def (RANGE_FOR_STMT): Take a 5th operand.
* cp-tree.h (RANGE_FOR_UNROLL): New macro.
(cp_convert_range_for): Adjust prototype.
(finish_while_stmt_cond): Likewise.
(finish_do_stmt): Likewise.
(finish_for_cond): Likewise.
* init.c (build_vec_init): Adjut call to finish_for_cond.
* parser.c (cp_parser_statement): Adjust call to
cp_parser_iteration_statement.
(cp_parser_for): Add unroll parameter and pass it in calls to
cp_parser_range_for and cp_parser_c_for.
(cp_parser_c_for): Add unroll parameter and pass it in call to
finish_for_cond.
(cp_parser_range_for): Add unroll parameter, set in on RANGE_FOR_STMT
and pass it in call to cp_convert_range_for.
(cp_convert_range_for): Add unroll parameter and pass it in call to
finish_for_cond.
(cp_parser_iteration_statement): Add unroll parameter and pass it in
calls to finish_while_stmt_cond, finish_do_stmt and cp_parser_for.
(cp_parser_pragma_ivdep): New static function.
(cp_parser_pragma_unroll): Likewise.
(cp_parser_pragma) <PRAGMA_IVDEP>: Add support for pragma Unroll.
<PRAGMA_UNROLL>: New case.
* pt.c (tsubst_expr) <FOR_STMT>: Adjust call to finish_for_cond.
<RANGE_FOR_STMT>: Pass unrolling factor to cp_convert_range_for.
<WHILE_STMT>: Adjust call to finish_while_stmt_cond.
<DO_STMT>: Adjust call to finish_do_stmt.
* semantics.c (finish_while_stmt_cond): Add unroll parameter and
build ANNOTATE_EXPR if present.
(finish_do_stmt): Likewise.
(finish_for_cond): Likewise.
(begin_range_for_stmt): Build RANGE_FOR_STMT with 5th operand.
fortran/
* array.c (gfc_copy_iterator): Copy unroll field.
* decl.c (directive_unroll): New global variable.
(gfc_match_gcc_unroll): New function.
* gfortran.h (gfc_iterator]): Add unroll field.
(directive_unroll): Declare:
* match.c (gfc_match_do): Use memset to initialize the iterator.
* match.h (gfc_match_gcc_unroll): New prototype.
* parse.c (decode_gcc_attribute): Match "unroll".
(parse_do_block): Set iterator's unroll.
(parse_executable): Diagnose misplaced unroll directive.
* trans-stmt.c (gfc_trans_simple_do) Annotate loop condition with
annot_expr_unroll_kind.
(gfc_trans_do): Likewise.
* gfortran.texi (GNU Fortran Compiler Directives): Split section into
subections 'ATTRIBUTES directive' and 'UNROLL directive'.
From-SVN: r255973
Ian Lance Taylor [Fri, 22 Dec 2017 03:27:00 +0000 (03:27 +0000)]
compiler: improve escape analysis diagnostics
This CL brings escape analysis diagnostics closer to the gc
compiler's. This makes porting and debugging escape analysis
code easier. A few changes:
- In the gc compiler, the variable expression is represented
with the variable node itself (ONAME), the location of which
is the location of definition. We add a definition_location
method to Node, and make use of it when the gc compiler emits
diagnostics at the definition locations.
- In the gc compiler, methods are named T.M or (*T).M. Add the
type to the method name when possible.
- Print "moved to heap" messages only for variables.
- Reduce some duplicated diagnostics.
- Print "does not escape" messages in more situations which the
gc compiler does.
- Remove the special handling for closure numbers. In gofrontend,
closures are named "$nested#" where # is a global counter
starting from 0, whereas in the gc compiler they are named
"outer.func#" where # is a per-function counter starting from
1. We tried to adjust the closure name to better matching the
ones in the gc compiler, however, it cannot match exactly
because of the difference of the counter. Instead, just print
"outer.$nested#".
Reviewed-on: https://go-review.googlesource.com/83875
From-SVN: r255967
Alexandre Oliva [Fri, 22 Dec 2017 02:07:31 +0000 (02:07 +0000)]
[SFN] sync up debug-only stmt list's side effects with empty stmts too
for gcc/c-family/ChangeLog
PR debug/83527
PR debug/83419
* c-semantics.c (only_debug_stmts_after_p): New.
(pop_stmt_list): Clear side effects in debug-only stmt list.
Check for single nondebug stmt followed by debug stmts only.
for gcc/testsuite/ChangeLog
PR debug/83527
PR debug/83419
* gcc.dg/pr83527.c: New.
From-SVN: r255966
GCC Administrator [Fri, 22 Dec 2017 00:16:15 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r255965
Martin Sebor [Fri, 22 Dec 2017 00:07:39 +0000 (00:07 +0000)]
PR testsuite/83462 - c-c++-common/Warray-bounds-3.c fails
gcc/testsuite/ChangeLog
* c-c++-common/Warray-bounds-3.c: Adjust dg-warning grep pattern.
From-SVN: r255962
Jakub Jelinek [Thu, 21 Dec 2017 23:10:45 +0000 (00:10 +0100)]
re PR middle-end/83487 (ICE in expand_call, at calls.c:4098)
PR middle-end/83487
* config/i386/i386.c (ix86_function_arg_boundary): Return
PARM_BOUNDARY for TYPE_EMPTY_P types.
* gcc.c-torture/compile/pr83487.c: New test.
* gcc.dg/compat/pr83487-1.h: New file.
* gcc.dg/compat/pr83487-1_main.c: New test.
* gcc.dg/compat/pr83487-1_x.c: New file.
* gcc.dg/compat/pr83487-1_y.c: New file.
* gcc.dg/compat/pr83487-2_main.c: New test.
* gcc.dg/compat/pr83487-2_x.c: New file.
* gcc.dg/compat/pr83487-2_y.c: New file.
* g++.dg/abi/pr83487.C: New test.
* g++.dg/compat/abi/pr83487-1_main.C: New test.
* g++.dg/compat/abi/pr83487-1_x.C: New file.
* g++.dg/compat/abi/pr83487-1_y.C: New file.
* g++.dg/compat/abi/pr83487-2_main.C: New test.
* g++.dg/compat/abi/pr83487-2_x.C: New file.
* g++.dg/compat/abi/pr83487-2_y.C: New file.
From-SVN: r255961
Jakub Jelinek [Thu, 21 Dec 2017 23:09:14 +0000 (00:09 +0100)]
re PR c/83448 (ice in get_source_location_for_substring, at input.c:1507)
PR c/83448
* gimple-ssa-sprintf.c (maybe_warn): Don't call set_caret_index
if navail is >= dir.len.
* gcc.c-torture/compile/pr83448.c: New test.
* gcc.dg/tree-ssa/builtin-snprintf-warn-4.c: New test.
From-SVN: r255960
Eric Botcazou [Thu, 21 Dec 2017 22:08:30 +0000 (22:08 +0000)]
Add missing PR number
From-SVN: r255959
Eric Botcazou [Thu, 21 Dec 2017 22:02:45 +0000 (22:02 +0000)]
decl.c (gnat_to_gnu_entity): Always take into account the Esize if it is known.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Always take
into account the Esize if it is known.
From-SVN: r255958
Steve Ellcey [Thu, 21 Dec 2017 21:58:19 +0000 (21:58 +0000)]
t-aarch64-linux (MULTILIB_OSDIRNAMES): Fix triplet for ilp32.
2017-12-21 Steve Ellcey <sellcey@cavium.com>
* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Fix
triplet for ilp32.
From-SVN: r255957
Alexandre Oliva [Thu, 21 Dec 2017 20:30:23 +0000 (20:30 +0000)]
move ChangeLog entry to the right file
From-SVN: r255955
Jakub Jelinek [Thu, 21 Dec 2017 19:28:10 +0000 (20:28 +0100)]
re PR rtl-optimization/80747 (gcc.dg/tree-ssa/tailrecursion-4.c fails with ICE when compiled with options "-fprofile-use -freorder-blocks-and-partition")
PR rtl-optimization/80747
PR rtl-optimization/83512
* cfgrtl.c (force_nonfallthru_and_redirect): When splitting
succ edge from ENTRY, copy partition from e->dest to the newly
created bb.
* bb-reorder.c (reorder_basic_blocks_simple): If last_tail is
ENTRY, use BB_PARTITION of its successor block as current_partition.
Don't copy partition when splitting succ edge from ENTRY.
* gcc.dg/pr80747.c: New test.
* gcc.dg/pr83512.c: New test.
From-SVN: r255954
Jakub Jelinek [Thu, 21 Dec 2017 19:27:21 +0000 (20:27 +0100)]
re PR tree-optimization/83523 (ICE: verify_gimple failed (error: statement marked for throw, but doesn't))
PR tree-optimization/83523
* tree-ssa-math-opts.c (is_widening_mult_p): Return false if
for INTEGER_TYPE TYPE_OVERFLOW_TRAPS.
(convert_mult_to_fma): Likewise.
* g++.dg/tree-ssa/pr83523.C: New test.
From-SVN: r255953
Jakub Jelinek [Thu, 21 Dec 2017 19:26:34 +0000 (20:26 +0100)]
re PR tree-optimization/83521 (ICE: verify_gimple failed (error: invalid operand in unary operation))
PR tree-optimization/83521
* tree-ssa-phiopt.c (factor_out_conditional_conversion): Use
gimple_build_assign without code on result of
fold_build1 (VIEW_CONVERT_EXPR, ...), as it might not create
a VIEW_CONVERT_EXPR.
* gcc.dg/pr83521.c: New test.
From-SVN: r255952
Andrew Pinski [Thu, 21 Dec 2017 19:18:32 +0000 (19:18 +0000)]
t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle multi-arch for ilp32.
2017-12-21 Andrew Pinski <apinski@cavium.com>
Steve Ellcey <sellcey@cavium.com>
* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle
multi-arch for ilp32.
Co-Authored-By: Steve Ellcey <sellcey@cavium.com>
From-SVN: r255951
Nathan Sidwell [Thu, 21 Dec 2017 19:16:01 +0000 (19:16 +0000)]
[PR c++/83406] deducing lambda type
https://gcc.gnu.org/ml/gcc-patches/2017-12/msg01432.html
PR c++/83406
* parser.c (cp_parser_lambda_body): Remove obsolete
single-return-statement handling.
PR c++/83406
* g++.dg/cpp0x/lambda/lambda-ice15.C: Adjust error.
* g++.dg/cpp1y/pr83406.C: New.
From-SVN: r255950
Uros Bizjak [Thu, 21 Dec 2017 19:00:28 +0000 (20:00 +0100)]
re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.
testsuite/ChangeLog:
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
From-SVN: r255949
Alexandre Oliva [Thu, 21 Dec 2017 18:14:21 +0000 (18:14 +0000)]
[-fcompare-debug] retain insn locations when turning dbr seq into return
A number of -fcompare-debug errors on sparc arise as we split a dbr
SEQUENCE back into separate insns to turn the branch into a return.
If we just take the location from the PREV_INSN, it might be a debug
insn without INSN_LOCATION, or an insn with an unrelated location.
But that's silly: each of the SEQUENCEd insns is still an insn with
its own INSN_LOCATION, so use that instead, even though some may have
been adjusted while constructing the SEQUENCE.
for gcc/ChangeLog
* reorg.c (make_return_insns): Reemit each insn with its own
location.
From-SVN: r255948
Alexandre Oliva [Thu, 21 Dec 2017 18:14:06 +0000 (18:14 +0000)]
[SFN] propagate single-nondebug-stmt's side effects to enclosing list
Statements without side effects, preceded by debug begin stmt markers,
would become a statement list with side effects, although the stmt on
its own would be extracted from the list and remain not having side
effects. This causes debug info and possibly codegen differences.
This patch fixes it, identifying the situation in which the stmt would
have been extracted from the stmt list, and propagating the side
effects flag from the stmt to the list.
for gcc/ChangeLog
PR debug/83419
* c-family/c-semantics.c (pop_stmt_list): Propagate side
effects from single nondebug stmt to container list.
for gcc/testsuite/ChangeLog
PR debug/83419
* gcc.dg/pr83419.c: New.
From-SVN: r255947
James Greenhalgh [Thu, 21 Dec 2017 16:39:43 +0000 (16:39 +0000)]
[patch AArch64] Do not perform a vector splat for vector initialisation if it is not useful
Our current vector initialisation code will first duplicate
the first element to both lanes, then overwrite the top lane with a new
value.
This duplication can be clunky and wasteful.
Better would be to simply use the fact that we will always be overwriting
the remaining bits, and simply move the first element to the corrcet place
(implicitly zeroing all other bits).
We also need a new pattern in simplify-rtx.c:simplify_ternary_operation ,
to ensure we can still simplify:
(vec_merge:OUTER
(vec_duplicate:OUTER x:INNER)
(subreg:OUTER y:INNER 0)
(const_int N))
To:
(vec_concat:OUTER x:INNER y:INNER) or (vec_concat y x)
---
gcc/
* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code
generation for cases where splatting a value is not useful.
* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
across a vec_duplicate and a paradoxical subreg forming a vector
mode to a vec_concat.
gcc/testsuite/
* gcc.target/aarch64/vect-slp-dup.c: New.
From-SVN: r255946
James Greenhalgh [Thu, 21 Dec 2017 16:32:25 +0000 (16:32 +0000)]
[Patch combine] Don't create ZERO_EXTEND from subregs unless we have a scalar int mode
gcc/
* combine.c (simplify_set): Do not transform subregs to zero_extends
if the destination is not a scalar int mode.
From-SVN: r255945
Eric Botcazou [Thu, 21 Dec 2017 16:22:04 +0000 (16:22 +0000)]
re PR c++/82872 (ICE in ignore_overflows on __PTRDIFF_MAX__ index)
PR c++/82872
* convert.c (convert_to_integer_1) <POINTER_TYPE>: Do not return the
shared zero if the input has overflowed.
From-SVN: r255944
Kyrylo Tkachov [Thu, 21 Dec 2017 15:02:49 +0000 (15:02 +0000)]
[arm] Specify +dotprod support for Cortex-A55 and Cortex-A75 in native system detection
Since support for -mcpu=cortex-a55 and -mcpu=cortex-a75
was added we added support for the +dotprod extension
which these CPUs support.
We already specify as such in the arm-cpus.in entries for
these processors. However the table in driver-arm.c was
not adding +dotproct to the -march string that it generates.
This patch fixes that oversight.
In the future I'd like to get the arm_cpu_table in driver-arm.c
be auto-generated somehow from the arm-cpus.in data so
that we don't have to keep track of discrepancies explicitly...
Bootstrapped and tested on arm-none-linux-gnueabihf.
* config/arm/driver-arm.c (arm_cpu_table): Specify dotprod
support for Cortex-A55 and Cortex-A75.
From-SVN: r255943
Kyrylo Tkachov [Thu, 21 Dec 2017 14:50:02 +0000 (14:50 +0000)]
[arm] Fix assembler option rewrite alphabetical comparison
* common/config/arm/arm-common.c (compare_opt_names): Add function
comment. Use strcmp instead of manual loop.
From-SVN: r255942
Martin Liska [Thu, 21 Dec 2017 14:22:08 +0000 (15:22 +0100)]
Fix gcov-dump tool for GCDA files (PR gcov-profile/83509).
2017-12-21 Martin Liska <mliska@suse.cz>
PR gcov-profile/83509
* gcov-dump.c (dump_gcov_file): Do not read info about
support_unexecuted_blocks for gcda files.
From-SVN: r255941
Jakub Jelinek [Thu, 21 Dec 2017 09:11:58 +0000 (10:11 +0100)]
re PR rtl-optimization/82973 (ICE in output_constant_pool_2, at varasm.c:3896 on aarch64)
PR rtl-optimization/82973
* emit-rtl.h (valid_for_const_vec_duplicate_p): Rename to ...
(valid_for_const_vector_p): ... this.
* emit-rtl.c (valid_for_const_vec_duplicate_p): Rename to ...
(valid_for_const_vector_p): ... this. Adjust function comment.
(gen_vec_duplicate): Adjust caller.
* optabs.c (expand_vector_broadcast): Likewise.
* simplify-rtx.c (simplify_const_unary_operation): Don't optimize into
CONST_VECTOR if some element isn't simplified valid_for_const_vector_p
constant.
(simplify_const_binary_operation): Likewise. Use CONST_FIXED_P macro
instead of GET_CODE == CONST_FIXED.
(simplify_subreg): Use CONST_FIXED_P macro instead of
GET_CODE == CONST_FIXED.
* gfortran.dg/pr82973.f90: New test.
From-SVN: r255939
Jakub Jelinek [Thu, 21 Dec 2017 09:11:29 +0000 (10:11 +0100)]
re PR rtl-optimization/82973 (ICE in output_constant_pool_2, at varasm.c:3896 on aarch64)
PR rtl-optimization/82973
* emit-rtl.h (valid_for_const_vec_duplicate_p): Rename to ...
(valid_for_const_vector_p): ... this.
* emit-rtl.c (valid_for_const_vec_duplicate_p): Rename to ...
(valid_for_const_vector_p): ... this. Adjust function comment.
(gen_vec_duplicate): Adjust caller.
* optabs.c (expand_vector_broadcast): Likewise.
* simplify-rtx.c (simplify_const_unary_operation): Don't optimize into
CONST_VECTOR if some element isn't simplified valid_for_const_vector_p
constant.
(simplify_const_binary_operation): Likewise. Use CONST_FIXED_P macro
instead of GET_CODE == CONST_FIXED.
(simplify_subreg): Use CONST_FIXED_P macro instead of
GET_CODE == CONST_FIXED.
* gfortran.dg/pr82973.f90: New test.
From-SVN: r255938
Jakub Jelinek [Thu, 21 Dec 2017 08:45:30 +0000 (09:45 +0100)]
re PR target/83488 (ICE on a CET test-case)
PR target/83488
* config/i386/i386.c (ix86_target_string): Move -mavx512vbmi2 and
-mshstk entries from isa_opts2 to isa_opts and -mhle, -mmovbe,
-mclzero and -mmwaitx entries from isa_opts to isa_opts2.
(ix86_option_override_internal): Adjust for
OPTION_MASK_ISA_{HLE,MOVBE,CLZERO,MWAITX} moving to ix86_isa_flags2
and OPTION_MASK_ISA_SHSTK moving to ix86_isa_flags.
(BDESC_VERIFYS): Remove SPECIAL_ARGS2 related checks.
(ix86_init_mmx_sse_builtins): Remove bdesc_special_args2 handling.
Use def_builtin2 instead of def_builtin for OPTION_MASK_ISA_MWAITX
and OPTION_MASK_ISA_CLZERO builtins. Use def_builtin instead of
def_builtin2 for CET builtins.
(ix86_expand_builtin): Remove bdesc_special_args2 handling. Fix
up formatting in IX86_BUILTIN_RDPID code.
* config/i386/i386-builtin.def: Move VBMI2 builtins from SPECIAL_ARGS2
section to SPECIAL_ARGS and from ARGS2 section to ARGS.
* config/i386/i386.opt (mavx512vbmi2, mshstk): Move from
ix86_isa_flags2 to ix86_isa_flags.
(mhle, mmovbe, mclzero, mmwaitx): Move from ix86_isa_flags to
ix86_isa_flags2.
* config/i386/i386-c.c (ix86_target_macros_internal): Check for
OPTION_MASK_ISA_{CLZERO,MWAITX} in isa_flag2 instead of isa_flag.
Check for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2} in isa_flag instead
of isa_flag2.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VBMI2_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_{SHSTK,AVX512VBMI2}_*SET being in ix86_isa_flags
and OPTION_MASK_ISA_{MOVBE,MWAITX,CLZERO}_*SET in ix86_isa_flags2.
* gcc.target/i386/pr83488.c: New test.
From-SVN: r255937
Richard Sandiford [Thu, 21 Dec 2017 07:03:03 +0000 (07:03 +0000)]
poly_int: prune_runtime_alias_test_list
This patch makes prune_runtime_alias_test_list take the iteration
factor as a poly_int and tracks polynomial offsets internally
as well.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-data-ref.h (prune_runtime_alias_test_list): Take the
factor as a poly_uint64 rather than an unsigned HOST_WIDE_INT.
* tree-data-ref.c (prune_runtime_alias_test_list): Likewise.
Track polynomial offsets.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255936
Richard Sandiford [Thu, 21 Dec 2017 07:02:53 +0000 (07:02 +0000)]
poly_int: compute_data_ref_alignment
This patch makes vect_compute_data_ref_alignment treat DR_INIT as a
poly_int and handles cases in which the calculated misalignment might
not be constant.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vect-data-refs.c (vect_compute_data_ref_alignment):
Treat drb->init as a poly_int. Fail if its misalignment wrt
vector_alignment isn't known.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255935
Richard Sandiford [Thu, 21 Dec 2017 07:02:46 +0000 (07:02 +0000)]
poly_int: loop versioning threshold
This patch splits the loop versioning threshold out from the
cost model threshold so that the former can become a poly_uint64.
We still use a single test to enforce both limits where possible.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vectorizer.h (_loop_vec_info): Add a versioning_threshold
field.
(LOOP_VINFO_VERSIONING_THRESHOLD): New macro
(vect_loop_versioning): Take the loop versioning threshold as a
separate parameter.
* tree-vect-loop-manip.c (vect_loop_versioning): Likewise.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
versioning_threshold.
(vect_analyze_loop_2): Compute the loop versioning threshold
whenever loop versioning is needed, and store it in the new
field rather than combining it with the cost model threshold.
(vect_transform_loop): Update call to vect_loop_versioning.
Try to combine the loop versioning and cost thresholds here.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255934
Richard Sandiford [Thu, 21 Dec 2017 07:02:36 +0000 (07:02 +0000)]
poly_int: tree-ssa-loop-ivopts.c:iv_use
This patch makes ivopts handle polynomial address offsets
when recording potential IV uses.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssa-loop-ivopts.h (strip_offset): Return the offset as
poly_uint64_pod rather than an unsigned HOST_WIDE_INT.
* tree-loop-distribution.c (classify_builtin_st): Update accordingly.
* tree-ssa-loop-ivopts.c (iv_use::addr_offset): Change from
an unsigned HOST_WIDE_INT to a poly_uint64_pod.
(group_compare_offset): Update accordingly.
(split_small_address_groups_p): Likewise.
(record_use): Take addr_offset as a poly_uint64 rather than
an unsigned HOST_WIDE_INT.
(strip_offset): Return the offset as a poly_uint64 rather than
an unsigned HOST_WIDE_INT.
(record_group_use, split_address_groups): Track polynomial offsets.
(add_iv_candidate_for_use): Likewise.
(addr_offset_valid_p): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(strip_offset_1): Return the offset as a poly_int64 rather than
a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255933
Richard Sandiford [Thu, 21 Dec 2017 07:02:28 +0000 (07:02 +0000)]
poly_int: get_binfo_at_offset
This patch changes the offset parameter to get_binfo_at_offset
from HOST_WIDE_INT to poly_int64. This function probably doesn't
need to handle polynomial offsets in practice, but it's easy
to do and avoids forcing the caller to check first.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (get_binfo_at_offset): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* tree.c (get_binfo_at_offset): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255932
Richard Sandiford [Thu, 21 Dec 2017 07:02:20 +0000 (07:02 +0000)]
poly_int: build_ref_for_offset
This patch changes the offset parameter to build_ref_for_offset
from HOST_WIDE_INT to poly_int64.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* ipa-prop.h (build_ref_for_offset): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* tree-sra.c (build_ref_for_offset): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255931
Richard Sandiford [Thu, 21 Dec 2017 07:02:13 +0000 (07:02 +0000)]
poly_int: MEM_REF offsets
This patch allows MEM_REF offsets to be polynomial, with mem_ref_offset
now returning a poly_offset_int instead of an offset_int. The
non-mechanical changes to callers of mem_ref_offset were handled by
previous patches.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* fold-const.h (mem_ref_offset): Return a poly_offset_int rather
than an offset_int.
* tree.c (mem_ref_offset): Likewise.
(build_simple_mem_ref_loc): Treat MEM_REF offsets as poly_ints.
* builtins.c (get_object_alignment_2): Likewise.
* expr.c (get_inner_reference, expand_expr_real_1): Likewise.
* gimple-fold.c (get_base_constructor): Likewise.
* gimple-ssa-strength-reduction.c (restructure_reference): Likewise.
* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref):
Likewise.
* ipa-polymorphic-call.c
(ipa_polymorphic_call_context::ipa_polymorphic_call_context): Likewise.
* ipa-prop.c (compute_complex_assign_jump_func): Likewise.
(get_ancestor_addr_info): Likewise.
* ipa-param-manipulation.c (ipa_get_adjustment_candidate): Likewise.
* match.pd: Likewise.
* tree-data-ref.c (dr_analyze_innermost): Likewise.
* tree-dfa.c (get_addr_base_and_unit_offset_1): Likewise.
* tree-eh.c (tree_could_trap_p): Likewise.
* tree-object-size.c (addr_object_size): Likewise.
* tree-ssa-address.c (copy_ref_info): Likewise.
* tree-ssa-alias.c (indirect_ref_may_alias_decl_p): Likewise.
(indirect_refs_may_alias_p): Likewise.
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
* tree-ssa.c (maybe_rewrite_mem_ref_base): Likewise.
(non_rewritable_mem_ref_base): Likewise.
* tree-vect-data-refs.c (vect_check_gather_scatter): Likewise.
* tree-vrp.c (vrp_prop::check_array_ref): Likewise.
* varasm.c (decode_addr_const): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255930
Richard Sandiford [Thu, 21 Dec 2017 07:02:06 +0000 (07:02 +0000)]
poly_int: find_bswap_or_nop_load
This patch handles polynomial offsets in find_bswap_or_nop_load,
which could be useful for constant-sized data at a variable offset.
It is needed for a later patch to compile.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* gimple-ssa-stor-merging.c (find_bswap_or_nop_load): Track polynomial
offsets for MEM_REFs.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255929
Richard Sandiford [Thu, 21 Dec 2017 07:01:59 +0000 (07:01 +0000)]
poly_int: adjust_ptr_info_misalignment
This patch makes adjust_ptr_info_misalignment take the adjustment
as a poly_uint64 rather than an unsigned int.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssanames.h (adjust_ptr_info_misalignment): Take the increment
as a poly_uint64 rather than an unsigned int.
* tree-ssanames.c (adjust_ptr_info_misalignment): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255928
Richard Sandiford [Thu, 21 Dec 2017 07:01:52 +0000 (07:01 +0000)]
poly_int: decode_addr_const
This patch makes the varasm-local addr_const track polynomial offsets.
I'm not sure how useful this is, but it was easier to convert than not.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* varasm.c (addr_const::offset): Change from HOST_WIDE_INT
to poly_int64.
(decode_addr_const): Update accordingly.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255927
Richard Sandiford [Thu, 21 Dec 2017 07:01:38 +0000 (07:01 +0000)]
poly_int: bit_field_size/offset
verify_expr ensured that the size and offset in gimple BIT_FIELD_REFs
satisfied tree_fits_uhwi_p. This patch extends that so that they can
be poly_uint64s, and adds helper routines for accessing them when the
verify_expr requirements apply.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (bit_field_size, bit_field_offset): New functions.
* hsa-gen.c (gen_hsa_addr): Use them.
* tree-ssa-forwprop.c (simplify_bitfield_ref): Likewise.
(simplify_vector_constructor): Likewise.
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
* tree-cfg.c (verify_expr): Require the sizes and offsets of a
BIT_FIELD_REF to be poly_uint64s rather than uhwis.
* fold-const.c (fold_ternary_loc): Protect tree_to_uhwi with
tree_fits_uhwi_p.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255926
Richard Sandiford [Thu, 21 Dec 2017 07:01:30 +0000 (07:01 +0000)]
poly_int: emit_group_load/store
This patch changes the sizes passed to emit_group_load and
emit_group_store from int to poly_int64.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.h (emit_group_load, emit_group_load_into_temps)
(emit_group_store): Take the size as a poly_int64 rather than an int.
* expr.c (emit_group_load_1, emit_group_load): Likewise.
(emit_group_load_into_temp, emit_group_store): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255925
Richard Sandiford [Thu, 21 Dec 2017 07:01:23 +0000 (07:01 +0000)]
poly_int: reload<->ira interface
This patch uses poly_int64 for:
- ira_reuse_stack_slot
- ira_mark_new_stack_slot
- ira_spilled_reg_stack_slot::width
all of which are part of the IRA/reload interface.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* ira-int.h (ira_spilled_reg_stack_slot::width): Change from
an unsigned int to a poly_uint64.
* ira.h (ira_reuse_stack_slot, ira_mark_new_stack_slot): Take the
sizes as poly_uint64s rather than unsigned ints.
* ira-color.c (ira_reuse_stack_slot, ira_mark_new_stack_slot):
Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255924
Richard Sandiford [Thu, 21 Dec 2017 07:01:17 +0000 (07:01 +0000)]
poly_int: emit_inc
This patch changes the LRA emit_inc routine so that it takes
a poly_int64 rather than an int.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* lra-constraints.c (emit_inc): Change inc_amount from an int
to a poly_int64.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255923
Richard Sandiford [Thu, 21 Dec 2017 07:01:10 +0000 (07:01 +0000)]
poly_int: cfgexpand stack variables
This patch changes the type of stack_var::size from HOST_WIDE_INT
to poly_uint64. The difference in signedness is because the
field was set by:
v->size = tree_to_uhwi (size);
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* cfgexpand.c (stack_var::size): Change from a HOST_WIDE_INT
to a poly_uint64.
(add_stack_var, stack_var_cmp, partition_stack_vars)
(dump_stack_var_partition): Update accordingly.
(alloc_stack_frame_space): Take the size as a poly_int64 rather
than a HOST_WIDE_INT.
(expand_stack_vars, expand_one_stack_var_1): Handle polynomial sizes.
(defer_stack_allocation, estimated_stack_frame_size): Likewise.
(account_stack_vars, expand_one_var): Likewise. Return a poly_uint64
rather than a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255922
Richard Sandiford [Thu, 21 Dec 2017 07:01:00 +0000 (07:01 +0000)]
poly_int: argument sizes
This patch changes various bits of state related to argument sizes so
that they have type poly_int64 rather than HOST_WIDE_INT. This includes:
- incoming_args::pops_args and incoming_args::size
- rtl_data::outgoing_args_size
- pending_stack_adjust
- stack_pointer_delta
- stack_usage::pushed_stack_size
- args_size::constant
It also changes TARGET_RETURN_POPS_ARGS so that the size of the
arguments passed in and the size returned by the hook are both
poly_int64s.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* target.def (return_pops_args): Treat both the input and output
sizes as poly_int64s rather than HOST_WIDE_INTS.
* targhooks.h (default_return_pops_args): Update accordingly.
* targhooks.c (default_return_pops_args): Likewise.
* doc/tm.texi: Regenerate.
* emit-rtl.h (incoming_args): Change pops_args, size and
outgoing_args_size from int to poly_int64_pod.
* function.h (expr_status): Change x_pending_stack_adjust and
x_stack_pointer_delta from int to poly_int64.
(args_size::constant): Change from HOST_WIDE_INT to poly_int64.
(ARGS_SIZE_RTX): Update accordingly.
* calls.c (highest_outgoing_arg_in_use): Change from int to
unsigned int.
(stack_usage_watermark, stored_args_watermark): New variables.
(stack_region_maybe_used_p, mark_stack_region_used): New functions.
(emit_call_1): Change the stack_size and rounded_stack_size
parameters from HOST_WIDE_INT to poly_int64. Track n_popped
as a poly_int64.
(save_fixed_argument_area): Check stack_usage_watermark.
(initialize_argument_information): Change old_pending_adj from
a HOST_WIDE_INT * to a poly_int64_pod *.
(compute_argument_block_size): Return the size as a poly_int64
rather than an int.
(finalize_must_preallocate): Track polynomial argument sizes.
(compute_argument_addresses): Likewise.
(internal_arg_pointer_based_exp): Track polynomial offsets.
(mem_overlaps_already_clobbered_arg_p): Rename to...
(mem_might_overlap_already_clobbered_arg_p): ...this and take the
size as a poly_uint64 rather than an unsigned HOST_WIDE_INT.
Check stored_args_used_watermark.
(load_register_parameters): Update accordingly.
(check_sibcall_argument_overlap_1): Likewise.
(combine_pending_stack_adjustment_and_call): Take the unadjusted
args size as a poly_int64 rather than an int. Return a bool
indicating whether the optimization was possible and return
the new adjustment by reference.
(check_sibcall_argument_overlap): Track polynomail argument sizes.
Update stored_args_watermark.
(can_implement_as_sibling_call_p): Handle polynomial argument sizes.
(expand_call): Likewise. Maintain stack_usage_watermark and
stored_args_watermark. Update calls to
combine_pending_stack_adjustment_and_call.
(emit_library_call_value_1): Handle polynomial argument sizes.
Call stack_region_maybe_used_p and mark_stack_region_used.
Maintain stack_usage_watermark.
(store_one_arg): Likewise. Update call to
mem_overlaps_already_clobbered_arg_p.
* config/arm/arm.c (arm_output_function_prologue): Add a cast to
HOST_WIDE_INT.
* config/avr/avr.c (avr_outgoing_args_size): Likewise.
* config/microblaze/microblaze.c (microblaze_function_prologue):
Likewise.
* config/cr16/cr16.c (cr16_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
(cr16_compute_frame, cr16_initial_elimination_offset): Add casts
to HOST_WIDE_INT.
* config/ft32/ft32.c (ft32_compute_frame): Likewise.
* config/i386/i386.c (ix86_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
(ix86_expand_split_stack_prologue): Add a cast to HOST_WIDE_INT.
* config/moxie/moxie.c (moxie_compute_frame): Likewise.
* config/m68k/m68k.c (m68k_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
* config/vax/vax.c (vax_return_pops_args): Likewise.
* config/pa/pa.h (STACK_POINTER_OFFSET): Add a cast to poly_int64.
(EXIT_IGNORE_STACK): Update reference to crtl->outgoing_args_size.
* config/arm/arm.h (CALLER_INTERWORKING_SLOT_SIZE): Likewise.
* config/powerpcspe/aix.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/powerpcspe/darwin.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/powerpcspe/powerpcspe.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/aix.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/darwin.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/rs6000.h (STACK_DYNAMIC_OFFSET): Likewise.
* dojump.h (saved_pending_stack_adjust): Change x_pending_stack_adjust
and x_stack_pointer_delta from int to poly_int64.
* dojump.c (do_pending_stack_adjust): Update accordingly.
* explow.c (allocate_dynamic_stack_space): Handle polynomial
stack_pointer_deltas.
* function.c (STACK_DYNAMIC_OFFSET): Add a cast to poly_int64.
(pad_to_arg_alignment): Track polynomial offsets.
(assign_parm_find_stack_rtl): Likewise.
(assign_parms, locate_and_pad_parm): Handle polynomial argument sizes.
* toplev.c (output_stack_usage): Update reference to
current_function_pushed_stack_size.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255921
Richard Sandiford [Thu, 21 Dec 2017 07:00:52 +0000 (07:00 +0000)]
poly_int: instantiate_virtual_regs
This patch makes the instantiate virtual regs pass track offsets
as poly_ints.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* function.c (in_arg_offset, var_offset, dynamic_offset)
(out_arg_offset, cfa_offset): Change from int to poly_int64.
(instantiate_new_reg): Return the new offset as a poly_int64_pod
rather than a HOST_WIDE_INT.
(instantiate_virtual_regs_in_rtx): Track polynomial offsets.
(instantiate_virtual_regs_in_insn): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255920
Richard Sandiford [Thu, 21 Dec 2017 07:00:46 +0000 (07:00 +0000)]
poly_int: REG_ARGS_SIZE
This patch adds new utility functions for manipulating REG_ARGS_SIZE
notes and allows the notes to carry polynomial as well as constant sizes.
The code was inconsistent about whether INT_MIN or HOST_WIDE_INT_MIN
should be used to represent an unknown size. The patch uses
HOST_WIDE_INT_MIN throughout.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (get_args_size, add_args_size_note): New functions.
(find_args_size_adjust): Return a poly_int64 rather than a
HOST_WIDE_INT.
(fixup_args_size_notes): Likewise. Make the same change to the
end_args_size parameter.
* rtlanal.c (get_args_size, add_args_size_note): New functions.
* builtins.c (expand_builtin_trap): Use add_args_size_note.
* calls.c (emit_call_1): Likewise.
* explow.c (adjust_stack_1): Likewise.
* cfgcleanup.c (old_insns_match_p): Update use of
find_args_size_adjust.
* combine.c (distribute_notes): Track polynomial arg sizes.
* dwarf2cfi.c (dw_trace_info): Change beg_true_args_size,
end_true_args_size, beg_delay_args_size and end_delay_args_size
from HOST_WIDE_INT to poly_int64.
(add_cfi_args_size): Take the args_size as a poly_int64 rather
than a HOST_WIDE_INT.
(notice_args_size, notice_eh_throw, maybe_record_trace_start)
(maybe_record_trace_start_abnormal, scan_trace, connect_traces): Track
polynomial arg sizes.
* emit-rtl.c (try_split): Use get_args_size.
* recog.c (peep2_attempt): Likewise.
* reload1.c (reload_as_needed): Likewise.
* expr.c (find_args_size_adjust): Return the adjustment as a
poly_int64 rather than a HOST_WIDE_INT.
(fixup_args_size_notes): Change end_args_size from a HOST_WIDE_INT
to a poly_int64 and change the return type in the same way.
(emit_single_push_insn): Track polynomial arg sizes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255919
Richard Sandiford [Thu, 21 Dec 2017 07:00:37 +0000 (07:00 +0000)]
poly_int: push_block/emit_push_insn
This patch changes the "extra" parameters to push_block and
emit_push_insn from int to poly_int64.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.h (push_block, emit_push_insn): Change the "extra" parameter
from HOST_WIDE_INT to poly_int64.
* expr.c (push_block, emit_push_insn): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255918
Richard Sandiford [Thu, 21 Dec 2017 06:58:16 +0000 (06:58 +0000)]
poly_int: frame allocations
This patch converts the frame allocation code (mostly in function.c)
to use poly_int64 rather than HOST_WIDE_INT for frame offsets and
sizes.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* function.h (frame_space): Change start and length from HOST_WIDE_INT
to poly_int64.
(get_frame_size): Return the size as a poly_int64 rather than a
HOST_WIDE_INT.
(frame_offset_overflow): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
(assign_stack_temp): Likewise for the size.
* function.c (get_frame_size): Return a poly_int64 rather than
a HOST_WIDE_INT.
(frame_offset_overflow): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(try_fit_stack_local): Take the start, length and size as poly_int64s
rather than HOST_WIDE_INTs. Return the offset as a poly_int64_pod
rather than a HOST_WIDE_INT.
(add_frame_space): Take the start and end as poly_int64s rather than
HOST_WIDE_INTs.
(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
(assign_stack_temp): Likewise for the size.
(temp_slot): Change size, base_offset and full_size from HOST_WIDE_INT
to poly_int64.
(find_temp_slot_from_address): Handle polynomial offsets.
(combine_temp_slots): Likewise.
* emit-rtl.h (rtl_data::x_frame_offset): Change from HOST_WIDE_INT
to poly_int64.
* cfgexpand.c (alloc_stack_frame_space): Return the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(expand_one_stack_var_at): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(expand_stack_vars, expand_one_stack_var_1, expand_used_vars): Handle
polynomial frame offsets.
* config/m32r/m32r-protos.h (m32r_compute_frame_size): Take the size
as a poly_int64 rather than an int.
* config/m32r/m32r.c (m32r_compute_frame_size): Likewise.
* config/v850/v850-protos.h (compute_frame_size): Likewise.
* config/v850/v850.c (compute_frame_size): Likewise.
* config/xtensa/xtensa-protos.h (compute_frame_size): Likewise.
* config/xtensa/xtensa.c (compute_frame_size): Likewise.
* config/pa/pa-protos.h (pa_compute_frame_size): Likewise.
* config/pa/pa.c (pa_compute_frame_size): Likewise.
* explow.h (get_dynamic_stack_base): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* explow.c (get_dynamic_stack_base): Likewise.
* final.c (final_start_function): Use the constant lower bound
of the frame size for -Wframe-larger-than.
* ira.c (do_reload): Adjust for new get_frame_size return type.
* lra.c (lra): Likewise.
* reload1.c (reload): Likewise.
* config/avr/avr.c (avr_asm_function_end_prologue): Likewise.
* config/pa/pa.h (EXIT_IGNORE_STACK): Likewise.
* rtlanal.c (get_initial_register_offset): Return the offset as
a poly_int64 rather than a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255917
Richard Sandiford [Thu, 21 Dec 2017 06:58:08 +0000 (06:58 +0000)]
poly_int: reload1.c
This patch makes a few small poly_int64 changes to reload1.c,
mostly related to eliminations. Again, there's no real expectation
that reload will be used for targets that have polynomial-sized modes,
but it seemed easier to convert it anyway.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* reload1.c (elim_table): Change initial_offset, offset and
previous_offset from HOST_WIDE_INT to poly_int64_pod.
(offsets_at): Change the target array's element type from
HOST_WIDE_INT to poly_int64_pod.
(set_label_offsets, eliminate_regs_1, eliminate_regs_in_insn)
(elimination_costs_in_insn, update_eliminable_offsets)
(verify_initial_elim_offsets, set_offsets_for_label)
(init_eliminable_invariants): Update after above changes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255916
Richard Sandiford [Thu, 21 Dec 2017 06:58:00 +0000 (06:58 +0000)]
poly_int: reload.c
This patch makes a few small poly_int64 changes to reload.c,
such as in the "decomposition" structure. In practice, any
port with polynomial-sized modes should be using LRA rather
than reload, but it's easier to convert reload anyway than
to sprinkle to_constants everywhere.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* reload.h (reload::inc): Change from an int to a poly_int64_pod.
* reload.c (combine_reloads, debug_reload_to_stream): Likewise.
(decomposition): Change start and end from HOST_WIDE_INT
to poly_int64_pod.
(decompose, immune_p): Update accordingly.
(find_inc_amount): Return a poly_int64 rather than an int.
* reload1.c (inc_for_reload): Take the inc_amount as a poly_int64
rather than an int.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255915
Richard Sandiford [Thu, 21 Dec 2017 06:57:41 +0000 (06:57 +0000)]
poly_int: get_inner_reference & co.
This patch makes get_inner_reference and ptr_difference_const return the
bit size and bit position as poly_int64s rather than HOST_WIDE_INTS.
The non-mechanical changes were handled by previous patches.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (get_inner_reference): Return the bitsize and bitpos
as poly_int64_pods rather than HOST_WIDE_INT.
* fold-const.h (ptr_difference_const): Return the pointer difference
as a poly_int64_pod rather than a HOST_WIDE_INT.
* expr.c (get_inner_reference): Return the bitsize and bitpos
as poly_int64_pods rather than HOST_WIDE_INT.
(expand_expr_addr_expr_1, expand_expr_real_1): Track polynomial
offsets and sizes.
* fold-const.c (make_bit_field_ref): Take the bitpos as a poly_int64
rather than a HOST_WIDE_INT. Update call to get_inner_reference.
(optimize_bit_field_compare): Update call to get_inner_reference.
(decode_field_reference): Likewise.
(fold_unary_loc): Track polynomial offsets and sizes.
(split_address_to_core_and_offset): Return the bitpos as a
poly_int64_pod rather than a HOST_WIDE_INT.
(ptr_difference_const): Likewise for the pointer difference.
* asan.c (instrument_derefs): Track polynomial offsets and sizes.
* config/mips/mips.c (r10k_safe_mem_expr_p): Likewise.
* dbxout.c (dbxout_expand_expr): Likewise.
* dwarf2out.c (loc_list_for_address_of_addr_expr_of_indirect_ref)
(loc_list_from_tree_1, fortran_common): Likewise.
* gimple-laddress.c (pass_laddress::execute): Likewise.
* gimple-ssa-store-merging.c (find_bswap_or_nop_load): Likewise.
* gimplify.c (gimplify_scan_omp_clauses): Likewise.
* simplify-rtx.c (delegitimize_mem_from_attrs): Likewise.
* tree-affine.c (tree_to_aff_combination): Likewise.
(get_inner_reference_aff): Likewise.
* tree-data-ref.c (split_constant_offset_1): Likewise.
(dr_analyze_innermost): Likewise.
* tree-scalar-evolution.c (interpret_rhs_expr): Likewise.
* tree-sra.c (ipa_sra_check_caller): Likewise.
* tree-vect-data-refs.c (vect_check_gather_scatter): Likewise.
* ubsan.c (maybe_instrument_pointer_overflow): Likewise.
(instrument_bool_enum_load, instrument_object_size): Likewise.
* gimple-ssa-strength-reduction.c (slsr_process_ref): Update call
to get_inner_reference.
* hsa-gen.c (gen_hsa_addr): Likewise.
* sanopt.c (maybe_optimize_ubsan_ptr_ifn): Likewise.
* tsan.c (instrument_expr): Likewise.
* match.pd: Update call to ptr_difference_const.
gcc/ada/
* gcc-interface/trans.c (Attribute_to_gnu): Track polynomial
offsets and sizes.
* gcc-interface/utils2.c (build_unary_op): Likewise.
gcc/cp/
* constexpr.c (check_automatic_or_tls): Track polynomial
offsets and sizes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255914
Richard Sandiford [Thu, 21 Dec 2017 06:57:32 +0000 (06:57 +0000)]
poly_int: fold_comparison
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* fold-const.c (fold_comparison): Track sizes and offsets as
poly_int64s rather than HOST_WIDE_INTs when folding address
comparisons.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255913
Richard Sandiford [Thu, 21 Dec 2017 06:57:18 +0000 (06:57 +0000)]
poly_int: get_bit_range
This patch makes get_bit_range return the range and position as poly_ints.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.h (get_bit_range): Return the bitstart and bitend as
poly_uint64s rather than unsigned HOST_WIDE_INTs. Return the bitpos
as a poly_int64 rather than a HOST_WIDE_INT.
* expr.c (get_bit_range): Likewise.
(expand_assignment): Update call accordingly.
* fold-const.c (optimize_bit_field_compare): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255912
Richard Sandiford [Thu, 21 Dec 2017 06:57:04 +0000 (06:57 +0000)]
[AArch64] Tweak aarch64_classify_address interface
Previously aarch64_classify_address used an rtx code to distinguish
LDP/STP addresses from normal addresses; the code was PARALLEL
to select LDP/STP and anything else to select normal addresses.
This patch replaces that parameter with a dedicated enum.
The SVE port will add another enum value that didn't map naturally
to an rtx code.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_addr_query_type): New enum.
(aarch64_legitimate_address_p): Use it instead of an rtx code,
as an optional final parameter.
* config/aarch64/aarch64.c (aarch64_classify_address): Likewise.
(aarch64_legitimate_address_p): Likewise.
(aarch64_print_address_internal): Take an aarch64_addr_query_type
instead of an rtx code.
(aarch64_address_valid_for_prefetch_p): Update calls accordingly.
(aarch64_legitimate_address_hook_p): Likewise.
(aarch64_print_ldpstp_address): Likewise.
(aarch64_print_operand_address): Likewise.
(aarch64_address_cost): Likewise.
* config/aarch64/constraints.md (Uml, Umq, Ump, Utq): Likewise.
* config/aarch64/predicates.md (aarch64_mem_pair_operand): Likewise.
(aarch64_mem_pair_lanes_operand): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255911
Richard Biener [Thu, 21 Dec 2017 04:41:27 +0000 (04:41 +0000)]
tree-ssa-dom.c (dom_opt_dom_walker::optimize_stmt): Call update_stmt_if_modified.
* tree-ssa-dom.c (dom_opt_dom_walker::optimize_stmt): Call
update_stmt_if_modified.
From-SVN: r255910
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