git.libre-soc.org Git

coroutines, ensure placeholder var is properly declared.

In cases that we need to extended the lifetime of a temporary captured
by reference, we make a replacement var for the temporary.  This will
be then used to define a coroutine frame entry (so that the var created
is elided by a later phase).  However, we should ensure that the var
is correctly declared anyway.

gcc/cp/ChangeLog:

2020-04-07  Iain Sandoe  <iain@sandoe.co.uk>

* coroutines.cc (maybe_promote_captured_temps): Ensure that
reference capture placeholder vars are properly declared.

arm: MVE: Add C++ polymorphism and fix some more issues

This patch adds C++ polymorphism for the MVE intrinsics, by using the native C++
polymorphic functions when C++ is used.

It also moves the PRESERVE name macro definitions to the right place so that the
variants without the '__arm_' prefix are not available if we define the PRESERVE
NAMESPACE macro.

This patch further fixes two testisms that were brought to light by C++ testing
added in this patch.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* g++.target/arm/mve.exp: New.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16: Fix testism.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32: Likewise.

arm: MVE: Fixes for pointers used in intrinsics for c++

This patch fixes the passing of some pointers to builtins that expect slightly
different types of pointers. In C this didn't prove an issue, but when
compiling for C++ gcc complains.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h: Cast some pointers to expected types.

arm: MVE: Fix -Wall testisms

This patch fixes some testisms I found when testing using -Wall/-Werror.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Fix testism.
* gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise.

arm: MVE: make sure we only use the Arm namespace variant of vuninitializedq

This patch replaces all uses of 'vuninitializedq_*' by the same function but
under the __arm_ namespace. In case we define the PRESERVE MACRO the variant
without the '__arm_' prefix will not be available.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
same with '__arm_' prefix.

arm: MVE: Fix vec extracts to memory

This patch fixes vec extracts to memory that can arise from code as seen in the
testcase added. The patch fixes this by allowing mem operands in the set of
mve_vec_extract patterns, which given the only '=r' constraint will lead to the
scalar value being written to a register and then stored in memory using scalar
store pattern.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c: New
test.

arm: MVE Fix immediate constraints on some vector instructions

Hi,

This patch fixes the immediate checks on vcvt and vqshr(u)n[bt] instructions.
It also removes the 'arm_mve_immediate_check' as the check was wrong and the
error message is not much better than the constraint one, which albeit isn't
great either.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm.c (arm_mve_immediate_check): Removed.
* config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
(mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
mve_vqshruntq_m_n_s*): Fixed immediate constraints.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c: New test.

arm: MVE Don't use lsll for 32-bit shifts scalar

After fixing the v[id]wdups using the "moving the wrap parameter" into the
top-end of a DImode operand using a shift, I noticed we were using lsll for
32-bit shifts in scalars, where we don't need to, as we can simply do a move,
which is much better if we don't need to use the bottom part.

We can solve this in a better way, but for now this will do.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.

arm: MVE: Fix v[id]wdup's

This patch fixes v[id]wdup intrinsics. They had two issues:
1) the predicated versions did not link the incoming inactive vector parameter
to the output
2) The backend didn't enforce the wrap limit operand be in an odd register.

1) was fixed like we did for all other predicated intrinsics
2) requires a temporary hack where we pass the value in the top end of DImode
operand. The proper fix would be to add a register CLASS but this interacted
badly with other existing targets codegen. We will look to fix this properly in GCC 11.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
* config/arm/mve/md: Fix v[id]wdup patterns.

arm: MVE: Fix constant load pattern

This patch fixes the constant load pattern for MVE, this was not accounting
correctly for label + offset cases.

Added test that ICE'd before and removed the scan assemblers for the mve_vector*
tests as they were too fragile.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm.c (output_move_neon): Deal with label + offset cases.
* config/arm/mve.md (*mve_mov<mode>): Handle const vectors.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/mve_load_from_array.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Remove
scan-assembler.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.

arm: MVE: Do not use typeof for pointer parameters

To make sure our inlining of _Generic doesn't go crazy we added an in between
declaration of the parameters used for _Generic selection. However, this will
not work if the parameter being passed in is an array. Since none of our
intrinsics return pointers we do not need to use typeof here as we will never be
able to nest intrinsics through this parameter. I also removed the unnecessary
const pointers in mve_typeid.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
and remove const_ptr enums.

arm: MVE: Fix polymorphism for scalars and constants

This patch merges some polymorphic functions that were uncorrectly separating
scalar variants. It also simplifies the way we detect scalars and constants in
mve_typeid.

I also fixed some polymorphic intrinsics that were splitting of scalar cases.

gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* config/arm/arm_mve.h (vsubq_n): Merge with...
(vsubq): ... this.
(vmulq_n): Merge with...
(vmulq): ... this.
(__ARM_mve_typeid): Simplify scalar and constant detection.

gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Fix test.
* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.

S/390: Fix layout of struct sigaction_t

The ordering of some fields in struct sigaction on s390x (64bit)
differs compared to s390 and other architectures.
This patch adjusts this order according to the definition of
<glibc-src>/sysdeps/unix/sysv/linux/s390/bits/sigaction.h

Without this fix e.g. the call
sigaction( suspendSignalNumber, &sigusr1, null ) in thread.d
leads to setting the sa_restorer field to 0xffffffffffffffff.
In case a signal, the signal handler returns to this address
and the process stops with a SIGILL.

This was observable in several execution testcases on s390x:
libphobos.druntime/core/thread.d
libphobos.druntime_shared/core/thread.d
libphobos.thread/tlsgc_sections.d
libphobos.allocations/tls_gc_integration.d
libphobos.phobos/std/parallelism.d
libphobos.phobos_shared/std/parallelism.d
libphobos.shared/host.c
libphobos.shared/linkD.c
libphobos.shared/linkDR.c
libphobos.shared/link_linkdep.d
libphobos.shared/load.d
libphobos.shared/loadDR.c
libphobos.shared/load_linkdep.d
libphobos.shared/load_loaddep.d

libphobos/ChangeLog:

2020-04-07 Stefan Liebler <stli@linux.ibm.com>

* libdruntime/core/sys/posix/signal.d:
Add struct sigaction_t for SystemZ.

c++: Fix usage of CONSTRUCTOR_PLACEHOLDER_BOUNDARY inside array initializers [PR90996]

This PR reports that ever since the introduction of the
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag, we are sometimes failing to resolve
PLACEHOLDER_EXPRs inside array initializers that refer to some inner
constructor.  In the testcase in the PR, we have as the initializer for "S c[];"
the following

  {{.a=(int &) &_ZGR1c_, .b={*(&<PLACEHOLDER_EXPR struct S>)->a}}}

where CONSTRUCTOR_PLACEHOLDER_BOUNDARY is set on the middle constructor.  When
calling replace_placeholders from store_init_value, we pass the entire
initializer to it, and as a result we fail to resolve the PLACEHOLDER_EXPR
within due to the CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag on the middle
constructor blocking replace_placeholders_r from reaching it.

To fix this, we could perhaps either call replace_placeholders in more places,
or we could change where we set CONSTRUCTOR_PLACEHOLDER_BOUNDARY.  This patch
takes this latter approach -- when building up an array initializer, we now
bubble any CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag from the element initializers
up to the array initializer so that the boundary doesn't later impede us when we
call replace_placeholders from store_init_value.

Besides fixing the kind of code like in the testcase, this shouldn't cause any
other differences in PLACEHOLDER_EXPR resolution because we don't create or use
PLACEHOLDER_EXPRs of array type in the frontend, as far as I can tell.

gcc/cp/ChangeLog:

PR c++/90996
* tree.c (replace_placeholders): Look through all handled components,
not just COMPONENT_REFs.
* typeck2.c (process_init_constructor_array): Propagate
CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element initializer to
the array initializer.

gcc/testsuite/ChangeLog:

PR c++/90996
* g++.dg/cpp1y/pr90996.C: New test.

i386: Fix V{64QI,32HI}mode constant permutations [PR94509]

The following testcases are miscompiled, because expand_vec_perm_pshufb
incorrectly thinks it can use vpshufb instruction for the permutations
when it can't.
The
          if (vmode == V32QImode)
            {
              /* vpshufb only works intra lanes, it is not
                 possible to shuffle bytes in between the lanes.  */
              for (i = 0; i < nelt; ++i)
                if ((d->perm[i] ^ i) & (nelt / 2))
                  return false;
            }
intra-lane check which is correct has been copied and adjusted for 64-byte
modes into:
          if (vmode == V64QImode)
            {
              /* vpshufb only works intra lanes, it is not
                 possible to shuffle bytes in between the lanes.  */
              for (i = 0; i < nelt; ++i)
                if ((d->perm[i] ^ i) & (nelt / 4))
                  return false;
            }
which is not correct, because 64-byte modes have 4 lanes rather than just
two and the above is only testing that the permutation grabs even lane elts
from even lanes and odd lane elts from odd lanes, but not that they are
from the same 256-bit half.

The following patch fixes it by using 3 * nelt / 4 instead of nelt / 4,
so we actually check the most significant 2 bits rather than just one.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

PR target/94509
* config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
for inter-lane permutation for 64-byte modes.

* gcc.target/i386/avx512bw-pr94509-1.c: New test.
* gcc.target/i386/avx512bw-pr94509-2.c: New test.

openmp: Fix parallel master error recovery [PR94512]

We need to set OMP_PARALLEL_COMBINED only if the parsing of omp_master
succeeded, because otherwise there is no nested master construct in the
parallel.

2020-04-07 Jakub Jelinek <jakub@redhat.com>

PR c++/94512
* c-parser.c (c_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
if c_parser_omp_master succeeded.

* parser.c (cp_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
if cp_parser_omp_master succeeded.

* g++.dg/gomp/pr94512.C: New test.

aarch64: Fix {ash[lr],lshr}<mode>3 expanders [PR94488]

The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port.  The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases.  All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

PR target/94488
* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
Assume it is a REG after that instead of testing it and doing FAIL
otherwise.  Formatting fix.

* gcc.c-torture/compile/pr94488.c: New test.

d: Always set ASM_VOLATILE_P on asm statements (PR94425)

gcc/d/ChangeLog:

PR d/94425
* toir.cc (IRVisitor::visit (GccAsmStatement *)): Set ASM_VOLATILE_P
on all asm statements.

RTEMS: Delete useless mcpu=8540 multilib

The support for the 32-bit float GPRs was removed in GCC 8.

gcc/

* config/rs6000/t-rtems: Delete mcpu=8540 multilib.

i386: Fix emit_reduc_half on V{64Q,32H}Imode [PR94500]

The following testcase is miscompiled in 8.x, because emit_reduc_half is
prepared to handle for 512-bit modes only i equal to 512, 256, 128 and 64.
V32HImode also needs i equal to 32 and V64QImode i equal to 32 and 16,
but emit_reduc_half in that case performs a redundant permutation exactly
like i == 32.  In 9+ the testcase works because Richard in r9-3393
changed the reduc_* expanders so that they actually don't call
ix86_expand_reduc on 512-bit modes, but only 128-bit ones.

The patch fixes emit_reduc_half to handle also i of 32 and 16 similarly to
how V32QImode/V16HImode are handled for AVX2.  I think it shouldn't hurt
to fix the function even on the trunk and 9 branch even when nothing uses
it ATM.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

PR target/94500
* config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
handle i < 64 using avx512bw_lshrv4ti3.  Formatting fixes.

* gcc.target/i386/avx512bw-pr94500.c: New test.

c++: Fix ICE with implicit operator== [PR94462]

duplicate_decls assumed that any TREE_ARTIFICIAL function at namespace scope
was a built-in function, but now in C++20 it's possible to have an
implicitly declared hidden friend operator==. We just need to move the
assert into the if condition.

gcc/cp/ChangeLog
2020-04-06 Jason Merrill <jason@redhat.com>

PR c++/94462
* decl.c (duplicate_decls): Fix handling of DECL_HIDDEN_FRIEND_P.

Daily bump.

libgo: update to almost the 1.14.2 release

Update to edea4a79e8d7dea2456b688f492c8af33d381dc2 which is likely to
be approximately the 1.14.2 release.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/227377

libgomp/test: Remove a build sysroot fix regression

Fix a problem with commit c8e759b4215b ("libgomp/test: Fix compilation
for build sysroot") that caused a regression in some standalone test
environments where testsuite/libgomp-test-support.exp is used, but the
compiler is expected to be determined by `[find_gcc]', and set the
GCC_UNDER_TEST TCL variable in testsuite/libgomp-site-extra.exp instead.

libgomp/
* configure.ac: Add testsuite/libgomp-site-extra.exp to output
files.
* configure: Regenerate.
* testsuite/libgomp-site-extra.exp.in: New file.
* testsuite/libgomp-test-support.exp.in (GCC_UNDER_TEST): Remove
variable.
* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
variable.
* testsuite/Makefile.in: Regenerate.

libatomic/test: Fix compilation for build sysroot

Fix a problem with the libatomic testsuite using a method to determine
the compiler to use resulting in the tool being different from one the
library has been built with, and causing a catastrophic failure from the
lack of a suitable `--sysroot=' option where the `--with-build-sysroot='
configuration option has been used to build the compiler resulting in
the inability to link executables.

Address this problem by providing a DejaGNU configuration file defining
the compiler to use, via the GCC_UNDER_TEST TCL variable, set from $CC
by autoconf, which will have all the required options set for the target
compiler to build executables in the environment configured, removing
failures like:

.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm
collect2: error: ld returned 1 exit status
compiler exited with status 1
FAIL: libatomic.c/atomic-compare-exchange-1.c (test for excess errors)
Excess errors:
.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm

UNRESOLVED: libatomic.c/atomic-compare-exchange-1.c compilation failed to produce executable

and bringing overall test results for the `riscv64-linux-gnu' target
(here with the `x86_64-linux-gnu' host and RISC-V QEMU in the Linux user
emulation mode as the target board) from:

=== libatomic Summary ===

# of unexpected failures 27
# of unresolved testcases 27

to:

=== libatomic Summary ===

# of expected passes 54

libatomic/
* configure.ac: Add testsuite/libatomic-site-extra.exp to output
files.
* configure: Regenerate.
* libatomic/testsuite/libatomic-site-extra.exp.in: New file.
* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
variable.
* testsuite/Makefile.in: Regenerate.

cselib: Fix endless cselib loop on (plus:P (reg) (const_int 0))

getopt.c hangs the compiler on h8300-elf with -O2 -g, because the
IL contains addition of constant 0, the first PLUS operand is determined
to have the SP_DERIVED_VALUE_P and the new code in cselib recurses
indefinitely on seeing SP_DERIVED_VALUE_P with locs of
(plus:P SP_DERIVED_VALUE_P (const_int 0)).

Fixed by making sure cselib_subst_to_values canonicalizes it, hashing
already hashes it the same too.

2020-04-06 Jakub Jelinek <jakub@redhat.com>

* cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
+ const0_rtx return the SP_DERIVED_VALUE_P.

Update gcc sv.po.

* sv.po: Update.

Update cpplib eo.po.

* eo.po: Update.

Fix fortran/93686 -- ICE matching data statements with derived-type pointers.

gcc/fortran/ChangeLog:

2020-04-06 Steven G. Kargl <kargl@gcc.gnu.org>

PR fortran/93686
* decl.c (gfc_match_data): Handle data matching for derived type
pointers.

gcc/testsuite/ChangeLog:

2020-04-06 Steven G. Kargl <kargl@gcc.gnu.org>

PR fortran/93686
* gfortran.dg/pr93686_1.f90: New test.
* gfortran.dg/pr93686_2.f90: Likewise.
* gfortran.dg/pr93686_3.f90: Likewise.
* gfortran.dg/pr93686_4.f90: Likewise.

skip gcc.target/arm/div64-unwinding.c on vxworks_kernel targets

This test verifies, by using a weak reference to _Unwind_RaiseException,
that performing division by zero does not cause that symbol to get
indirectly pulled into our closure.

The testing methodology unfortunately does not work on VxWorks targets
when building in kernel mode. This is inherent to how kernel mode
on VxWorks works: The link is only partial and the remaining symbols
which have not been resolved already get automatically resolved by
the VxWorks loader at the moment the module is loaded onto the target,
prior to execution. The resolution includes weak symbols too, which
defeats the purpose of this test.

gcc/testsuite/

* gcc.target/arm/div64-unwinding.c: Skip on vxworks_kernel targets.

lra: Stop eh_return data regs being incorrectly marked live [PR92989]

lra_assign has an assert to make sure that no pseudo is allocated
to a conflicting hard register.  It used to be restricted to
!flag_ipa_ra, but in g:a1e6ee38e708ef2bdef4 I'd enabled it for
flag_ipa_ra too.  It then tripped a few times while building
libstdc++ for mips-mti-linux.

Previous patches fixed one of the problems: registers clobbered
by the taking of an exception were being treated as live at the
beginning of the EH receiver, and this got propagated to predecessor
blocks.  But it turns out that there was a second problem: eh_return
data registers were also being marked live in the same way.

These registers are defined by the unwinder and so in reality they
are live on entry to the EH receiver.  But definitions can only happen
in blocks, not on edges, so for liveness purposes we use artificial
definitions at the start of the EH receiver.  process_bb_lives should
therefore model the effect of a definition, not a plain use.

2020-04-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
PR rtl-optimization/92989
* lra-lives.c (process_bb_lives): Do not treat eh_return data
registers as being live at the beginning of the EH receiver.

libstdc++: Make string_view::copy usable in constant expressions (PR 94498)

PR libstdc++/94498
* include/bits/char_traits.h (__gnu_cxx::char_traits::move): Make it
usable in constant expressions for C++20.
(__gnu_cxx::char_traits::copy, __gnu_cxx::char_traits::assign): Add
_GLIBCXX20_CONSTEXPR.
(std::char_traits<char>, std::char_traits<wchar_t>)
(std::char_traits<char8_t>): Make move, copy and assign usable in
constant expressions for C++20.
(std::char_traits<char16_t>, std::char_traits<char32_t>): Make move
and copy usable in constant expressions for C++20.
* include/std/string_view (basic_string_view::copy): Add
_GLIBCXX20_CONSTEXPR.
* testsuite/21_strings/basic_string_view/operations/copy/char/
constexpr.cc: New test.
* testsuite/21_strings/basic_string_view/operations/copy/wchar_t/
constexpr.cc: New test.

c++: Fix crash in gimplifier with paren init of aggregates [PR94155]

Here we crash in the gimplifier because gimplify_init_ctor_eval doesn't
expect null indexes for a constructor:

      /* ??? Here's to hoping the front end fills in all of the indices,
         so we don't have to figure out what's missing ourselves.  */
      gcc_assert (purpose);

The indexes weren't filled because we never called reshape_init: for
a constructor that represents parenthesized initialization of an
aggregate we don't allow brace elision or designated initializers.

PR c++/94155 - crash in gimplifier with paren init of aggregates.
* init.c (build_vec_init): Fill in indexes.

* g++.dg/cpp2a/paren-init22.C: New test.

Daily bump.

libstdc++: Refer to Git documentation

* doc/xml/manual/appendix_contributing.xml: Refer to Git
documentation instead of Subversion. Switch to https.
* doc/html/manual/appendix_contributing.html: Regenerate.

coroutines, testsuite: Renumber two tests (NFC).

Try to keep tests order by distinct number (and with a short
descriptive name appended).

2020-04-05 Iain Sandoe <iain@sandoe.co.uk>

* g++.dg/coroutines/torture/co-await-14-template-traits.C: Rename...
* g++.dg/coroutines/torture/co-await-16-template-traits.C: to this.
* g++.dg/coroutines/torture/co-await-15-capture-comp-ref.C: Rename..
* g++.dg/coroutines/torture/co-await-17-capture-comp-ref.C: to this.

Minor doc fix for ISO C90

* extend.texi: Add free to list of ISO C90 functions that
are recognized by the compiler.

Microblaze: Fixed missing save of r18 in fast_interrupt. Register 18 is used as a clobber register, and must be stored when entering a fast_interrupt. Before this fix, register 18 was only saved if it was used directly in the interrupt function.

    However, if the fast_interrupt function called a function that used
    r18, the register would not be saved, and thus be mangled
    upon returning from the interrupt.

* config/microblaze/microblaze.c (microblaze_must_save_register): Check
for fast_interrupt.

Microblaze: Modified trap instruction There is a bug in trap instruction generation. Instead of "bri 0" instruction "brki r0, -1" was used, corrected it now.

* gcc/config/microblaze/microblaze.md (trap): Update output pattern.

* gcc.target/microblaze/others/builtin-trap.c: Update expected output.

Daily bump.

debug: Improve debug info of c++14 deduced return type [PR94459]

On the following testcase, in gdb ptype S<long>::m1 prints long as return
type, but all the other methods show void instead.
PR53756 added code to add_type_attribute if the return type is
auto/decltype(auto), but we actually should look through references,
pointers and qualifiers.
Haven't included there DW_TAG_atomic_type, because I think at least ATM
one can't use that in C++.  Not sure about DW_TAG_array_type or what else
could be deduced.

> http://eel.is/c++draft/dcl.spec.auto#3 says it has to appear as a
> decl-specifier.
>
> http://eel.is/c++draft/temp.deduct.type#8 lists the forms where a template
> argument can be deduced.
>
> Looks like you are missing arrays, pointers to members, and function return
> types.

2020-04-04  Hannes Domani  <ssbssa@yahoo.de>
    Jakub Jelinek  <jakub@redhat.com>

PR debug/94459
* dwarf2out.c (gen_subprogram_die): Look through references, pointers,
arrays, pointer-to-members, function types and qualifiers when
checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
to emit type again on definition.

* g++.dg/debug/pr94459.C: New test.

Co-Authored-By: Hannes Domani <ssbssa@yahoo.de>

libgcc: only use __mmap if glibc >- 2.26

* generic-morestack.c: Only use __mmap on glibc >= 2.26.

c++: Mangling of dependent conversions [PR91377]

We skip over other conversion codes when mangling expressions, we should do
the same with IMPLICIT_CONV_EXPR.

gcc/cp/ChangeLog
2020-04-04 Jason Merrill <jason@redhat.com>

PR c++/91377
* mangle.c (write_expression): Skip IMPLICIT_CONV_EXPR.

c++: Refrain from using replace_placeholders in constexpr evaluation [PR94205]

This removes the use of replace_placeholders in cxx_eval_constant_expression
(which is causing the new test lambda-this6.C to ICE due to replace_placeholders
mutating the shared TARGET_EXPR_INITIAL tree which then trips up the
gimplifier).

In its place, this patch adds a 'parent' field to constexpr_ctx which is used to
store a pointer to an outer constexpr_ctx that refers to another object under
construction.  With this new field, we can beef up lookup_placeholder to resolve
PLACEHOLDER_EXPRs which refer to former objects under construction, which fixes
PR94205 without needing to do replace_placeholders.  Also we can now respect the
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag when resolving PLACEHOLDER_EXPRs, and
doing so fixes the constexpr analogue of PR79937.

gcc/cp/ChangeLog:

PR c++/94205
PR c++/79937
* constexpr.c (struct constexpr_ctx): New field 'parent'.
(cxx_eval_bare_aggregate): Propagate CONSTRUCTOR_PLACEHOLDER_BOUNDARY
flag from the original constructor to the reduced constructor.
(lookup_placeholder): Prefer to return the outermost matching object
by recursively calling lookup_placeholder on the 'parent' context,
but don't cross CONSTRUCTOR_PLACEHOLDER_BOUNDARY constructors.
(cxx_eval_constant_expression): Link the 'ctx' context to the 'new_ctx'
context via 'new_ctx.parent' when being expanded without an explicit
target.  Don't call replace_placeholders.
(cxx_eval_outermost_constant_expr): Initialize 'ctx.parent' to NULL.

gcc/testsuite/ChangeLog:

PR c++/94205
PR c++/79937
* g++.dg/cpp1y/pr79937-5.C: New test.
* g++.dg/cpp1z/lambda-this6.C: New test.

c++: Fix constexpr evaluation of self-modifying CONSTRUCTORs [PR94219]

This PR reveals that cxx_eval_bare_aggregate and cxx_eval_store_expression do
not anticipate that a constructor element's initializer could mutate the
underlying CONSTRUCTOR.  Evaluation of the initializer could add new elements to
the underlying CONSTRUCTOR, thereby potentially invalidating any pointers to
or assumptions about the CONSTRUCTOR's elements, and so these routines should be
prepared for that.

To fix this problem, this patch makes cxx_eval_bare_aggregate and
cxx_eval_store_expression recompute the constructor_elt pointers through which
we're assigning, after it evaluates the initializer.  Care is taken to to not
slow down the common case where the initializer does not modify the underlying
CONSTRUCTOR.

gcc/cp/ChangeLog:

PR c++/94219
PR c++/94205
* constexpr.c (get_or_insert_ctor_field): Split out (while adding
support for VECTOR_TYPEs, and optimizations for the common case)
from ...
(cxx_eval_store_expression): ... here.  Rename local variable
'changed_active_union_member_p' to 'activated_union_member_p'.  Record
the sequence of indexes into 'indexes' that yields the subobject we're
assigning to.  Record the integer offsets of the constructor indexes
we're assigning through into 'index_pos_hints'.  After evaluating the
initializer of the store expression, recompute 'valp' using 'indexes'
and using 'index_pos_hints' as hints.
(cxx_eval_bare_aggregate): Tweak comments.  Use get_or_insert_ctor_field
to recompute the constructor_elt pointer we're assigning through after
evaluating each initializer.

gcc/testsuite/ChangeLog:

PR c++/94219
PR c++/94205
* g++.dg/cpp1y/constexpr-nsdmi3.C: New test.
* g++.dg/cpp1y/constexpr-nsdmi4.C: New test.
* g++.dg/cpp1y/constexpr-nsdmi5.C: New test.
* g++.dg/cpp1z/lambda-this5.C: New test.

Fix previous commit.

gcc/ChangeLog:

2020-04-04 Jan Hubicka <hubicka@ucw.cz>

PR ipa/93940
* ipa-fnsummary.c (vrp_will_run_p): New function.
(fre_will_run_p): New function.
(evaluate_properties_for_edge): Use it.
* ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
!optimize_debug to optimize_debug.

gcc/testsuite/ChangeLog:

2020-04-04 Jan Hubicka <hubicka@ucw.cz>

* g++.dg/tree-ssa/pr93940.C: New test.

c++: Fix invalid pointer-to-member in requires [PR67825]

A recent change to cmcstl2 led to two tests failing due to this bug: our
valid expression checking in the context of a requires-expression wasn't
catching that an expression of member function type can only appear as the
function operand of a call expression. Fixed by using convert_to_void to do
the same checking as a discarded-value expression.

This patch also fixes 67825, which already had a testcase, but the testcase
was testing for the wrong behavior.

gcc/cp/ChangeLog
2020-04-04 Jason Merrill <jason@redhat.com>

PR c++/67825
* constraint.cc (tsubst_valid_expression_requirement): Call
convert_to_void.

c++: Fix reuse of class constants [PR94453]

The testcase hit an ICE trying to expand a TARGET_EXPR temporary cached from
the other lambda-expression. This patch fixes this in two ways:

1) Avoid reusing a TARGET_EXPR from another function.
2) Avoid ending up with a TARGET_EXPR at all; the use of 'p' had become
<TARGET_EXPR<NON_LVALUE_EXPR<TARGET_EXPR ...>>>, which doesn't make any
sense.

gcc/cp/ChangeLog
2020-04-04 Jason Merrill <jason@redhat.com>

PR c++/94453
* constexpr.c (maybe_constant_value): Use break_out_target_exprs.
* expr.c (mark_use) [VIEW_CONVERT_EXPR]: Don't wrap a TARGET_EXPR in
NON_LVALUE_EXPR.

ipa: Fix wrong code with failed propagation to builtin_constant_p [PR93940]

this patch fixes wrong code on a testcase where inline predicts
builtin_constant_p to be true but we fail to optimize its parameter to constant
becuase FRE is not run and the value is passed by an aggregate.

This patch makes the inline predicates to disable aggregate tracking
when FRE is not going to be run and similarly value range when VRP is not
going to be run.

This is just partial fix.  Even with it we can arrange FRE/VRP to fail and
produce wrong code, unforutnately.

I think for GCC11 I will need to implement transformation in ipa-inline
but this is bit hard to do: predicates only tracks that value will be constant
and do not track what constant to be.

Optimizing builtin_constant_p in a conditional is not going to do good job
when the value is used later in a place that expects it to be constant.
This is pre-existing problem that is not limited to inline tracking. For example,
FRE may do the transofrm at one place but not in another due to alias oracle
walking limits.

So I am not sure what full fix would be :(

gcc/ChangeLog:

2020-04-04  Jan Hubicka  <hubicka@ucw.cz>

PR ipa/93940
* ipa-fnsummary.c (vrp_will_run_p): New function.
(fre_will_run_p): New function.
(evaluate_properties_for_edge): Use it.
* ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
!optimize_debug to optimize_debug.

gcc/testsuite/ChangeLog:

2020-04-04  Jan Hubicka  <hubicka@ucw.cz>

* g++.dg/tree-ssa/pr93940.C: New test.

cselib: Don't consider SP_DERIVED_VALUE_P values as useless [PR94468]

The following testcase ICEs, because at one point we see the
SP_DERIVED_VALUE_P VALUE as useless (not PRESERVED_VALUE_P and no locs)
and so expect it to be discarded as useless.  But, later on we
are adding some new VALUE that is equivalent to it, and when adding
the equivalency that that new VALUE is equal to this SP_DERIVED_VALUE_P,
new_elt_loc_list has code for VALUE canonicalization and reverses addition
if uid is smaller, and at that point a new loc is added to the
SP_DERIVED_VALUE_P VALUE and it isn't discarded as useless anymore.
Now, I think we don't want to discard the SP_DERIVED_VALUE_P values
even if they have no locs, because they still have the special behaviour
that they then force other new VALUEs to be canonicalized against them,
which is what this patch implements.  I've not set PRESERVED_VALUE_P
on the SP_DERIVED_VALUE_P at the creation time, because whether a VALUE
is preserved or not is something that affects var-tracking decisions quite a
lot and we shouldn't set it blindly on other VALUEs.

Or, to avoid the repetitive code, should I introduce
static bool
cselib_useless_value_p (cselib_val *v)
{
  return (v->locs == 0
  && !PRESERVED_VALUE_P (v->val_rtx)
  && !SP_DERIVED_VALUE_P (v->val_rtx)));
}
predicate and use it in those 6 spots?

2020-04-04  Jakub Jelinek  <jakub@redhat.com>

PR rtl-optimization/94468
* cselib.c (references_value_p): Formatting fix.
(cselib_useless_value_p): New function.
(discard_useless_locs, discard_useless_values,
cselib_invalidate_regno_val, cselib_invalidate_mem,
cselib_record_set): Use it instead of
v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).

* g++.dg/opt/pr94468.C: New test.

c++: Fix further protected_set_expr_location related -fcompare-debug issues [PR94441]

My recent protected_set_expr_location changes work well when
that function is called unconditionally, but as the testcase shows, the C++
FE has a few spots that do:
  if (!EXPR_HAS_LOCATION (stmt))
    protected_set_expr_location (stmt, locus);
or similar.  Now, if we have for -g0 stmt of some expression that can
have location and has != UNKNOWN_LOCATION, while -g instead has
a STATEMENT_LIST containing some DEBUG_BEGIN_STMTs + that expression with
that location, we don't call protected_set_expr_location in the -g0 case,
but do call it in the -g case, because on the STATEMENT_LIST
!EXPR_HAS_LOCATION.
The following patch introduces a helper function which digs up the single
expression of a STATEMENT_LIST and uses that expression in the
EXPR_HAS_LOCATION check (plus changes protected_set_expr_location to
also use that helper).

Or do we want a further wrapper, perhaps C++ FE only, that would do this
protected_set_expr_location_if_unset (stmt, locus)?

2020-04-04  Jakub Jelinek  <jakub@redhat.com>

PR debug/94441
* tree-iterator.h (expr_single): Declare.
* tree-iterator.c (expr_single): New function.
* tree.h (protected_set_expr_location_if_unset): Declare.
* tree.c (protected_set_expr_location): Use expr_single.
(protected_set_expr_location_if_unset): New function.

* parser.c (cp_parser_omp_for_loop): Use
protected_set_expr_location_if_unset.
* cp-gimplify.c (genericize_if_stmt, genericize_cp_loop): Likewise.

* g++.dg/opt/pr94441.C: New test.

Daily bump.

Fix stdarg-3 regression on xstormy16 port

PR rtl-optimization/92264
* config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
reloading of auto-increment addressing modes.

openmp: Fix ICE on #pragma omp parallel master in template [PR94477]

The following testcase ICEs, because for parallel combined with some
other construct we initialize the omp_parallel_combined_clauses pointer
and expect the construct combined with it to clear it after it no longer
needs it, but OMP_MASTER didn't do that.

2020-04-04 Jakub Jelinek <jakub@redhat.com>

PR c++/94477
* pt.c (tsubst_expr) <case OMP_MASTER>: Clear
omp_parallel_combined_clauses.

* g++.dg/gomp/pr94477.C: New test.

libgcc: avoid mmap/munmap hooks in split-stack code on GNU/Linux

* generic-morestack.c: On GNU/Linux use __mmap/__munmap rather
than mmap/munmap, to avoid hooks.

x86: Mark scratch operand in ssse3_pshufbv8qi3 as earlyclobber

commit 16ed2601ad0a4aa82f11e9df86ea92183f94f979
Author: H.J. Lu <hongjiu.lu@intel.com>
Date:   Wed May 15 15:26:19 2019 +0000

    i386: Emulate MMX pshufb with SSE version

has

+(define_insn_and_split "ssse3_pshufbv8qi3"
+  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
+  (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yv")
+           (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")]
+          UNSPEC_PSHUFB))
+   (clobber (match_scratch:V4SI 3 "=X,x,Yv"))]
                                       ^^^  There are earlyclobber.
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+  "@
+   pshufb\t{%2, %0|%0, %2}
+   #
+   #"
+  "TARGET_MMX_WITH_SSE && reload_completed"
+  [(set (match_dup 3) (match_dup 5))
+   (set (match_dup 3)
+  (and:V4SI (match_dup 3) (match_dup 2)))
+   (set (match_dup 0)
+  (unspec:V16QI [(match_dup 1) (match_dup 4)] UNSPEC_PSHUFB))]

If input register operand 2 is dead after this insn, RA may choose it
as scratch operand.  Since it isn't marked as earlyclobber, operand 2
becomes unused after split and then it gets optimized out.  Mark scratch
operand as earlyclobber fixes the issue.

gcc/

PR target/94467
* config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
as earlyclobber.

gcc/testsuite/

PR target/94467
* gcc.target/i386/pr94467-1.c: New test.
* gcc.target/i386/pr94467-2.c: Likewise.

Fix va-arg-22.c at -O1 on m32r.

PR rtl-optimization/92264
* config/m32r/m32r.c (m32r_output_block_move): Properly account for
post-increment addressing of source operands as well as residuals
when computing any adjustments to the input pointer.

i386: Fix up handling of OPTION_MASK_ISA_MMX builtins [PR94461]

In https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00576.html the builtin
handling was changed so that OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE
etc. in i386-builtin.def means we require both mmx and sse, not just one of
those, and later on for other option combinations very similar rule has
been clarified, with a few exceptions that ix86_expand_builtin lists
(SSE | 3DNOW_A, SSE4_2 | CRC32 and FMA | FMA4 are one or the other).
The above mentioned patch also added OPTION_MASK_ISA_MMX to a few insns
that in the ISA documents are documented e.g. only requiring SSE2 or SSSE3
etc. CPUID, but because those builtins take or return V2SI or similar
MMX-ish arguments, we can't really support those builtins in functions that
have MMX disabled.
Now, during the TARGET_MMX_WITH_SSE changes,
https://gcc.gnu.org/ml/gcc-patches/2019-02/msg01479.html
and
https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01084.html
actually changed this; it added | OPTION_MASK_ISA_SSE2 to builtins
that were formerly OPTION_MASK_ISA_MMX only, but didn't touch the builtins
that were already using OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX
for something different (both options must be enabled).
This causes e.g. ICE on the following testcase, because the builtins are
now enabled even with just -mmmx -mno-sse2, even when they (those changed in
2017) require SSE2.
The following patch instead reverts the above two 2019-ish changes (except
for header/testsuite changes), and instead treats OPTION_MASK_ISA_MMX
requirement in bdesc/.isa specially, as being satisfied by either
TARGET_MMX (no changes really needed for that), or by TARGET_MMX_WITH_SSE.
This achieves what the two 2019-ish patches want to do, that the
OPTION_MASK_ISA_MMX only builtins are enabled not just with -mmmx, but also
with -m64 -msse2, and for the other builtins that require MMX and something
else will either require -mmmx and that some other ISA, or -m64 -msse2 and
that other ISA, but -mmmx will not enable builtins that need something more
than OPTION_MASK_ISA_MMX only.
The i386-builtins.c changes that aren't reversion of the two patches try to
make sure that in .isa we still record OPTION_MASK_ISA_MMX for builtins that
have that requirement, so that it is in the end only ix86_expand_builtin
that decides if the builtin is ok or not and the rest of code just decides
if it is the right time to declare the builtin already or if it should be
deferred.

2020-04-03 Jakub Jelinek <jakub@redhat.com>

PR target/94461
* config/i386/i386-expand.c (ix86_expand_builtin): If
TARGET_MMX_WITH_SSE without TARGET_MMX and bisa contains
OPTION_MASK_ISA_MMX, clear OPTION_MASK_ISA_MMX and set
OPTION_MASK_ISA_SSE2 in bisa. Revert 2019-05-17 and 2019-05-15
changes.
* config/i386/i386-builtins.c (def_builtin): If mask includes
OPTION_MASK_ISA_MMX and TARGET_MMX_WITH_SSE, consider it satisfied.
(ix86_add_new_builtins): For TARGET_64BIT, consider
OPTION_MASK_ISA_SSE2 enabled in isa as satisfying OPTION_MASK_ISA_MMX
requirement.
(ix86_init_tm_builtins): If TARGET_MMX_WITH_SSE consider
OPTION_MASK_ISA_MMX as satisfied.
(bdesc_tm): Revert 2019-05-15 changes.
(ix86_init_mmx_sse_builtins): Likewise.
* config/i386/i386-builtin.def: Likewise.

* gcc.target/i386/pr94461.c: New test.

c++: alias template and parameter packs (PR91966).

In this testcase, when we do a pack expansion of count_better_mins<nums>,
nums appears both in the definition of count_better_mins and as its template
argument.  The intent is that we get a expansion over pairs of elements of
the pack, i.e. less<2,2>, less<2,7>, less<7,2>, ....  But if we substitute
into the definition of count_better_mins when parsing the template, we end
up with sum<less<nums,nums>...>, which never gives us less<2,7>.  We could
deal with this by somehow marking up the use of 'nums' as an argument for
'num', but it's simpler to mark the alias as complex, so we need to
instantiate it later with all its arguments rather than replace it early
with its expansion.

gcc/cp/ChangeLog
2020-04-03  Jason Merrill  <jason@redhat.com>

PR c++/91966
* pt.c (complex_pack_expansion_r): New.
(complex_alias_template_p): Use it.

i386: Fix vph{add,subs?}[wd] 256-bit AVX2 RTL patterns [PR94460]

The following testcase is miscompiled, because the AVX2 patterns don't
describe correctly what the insn does.  E.g. vphaddd with %ymm* operands
(the second pattern) instruction as per:
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi32&expand=2941
does { a0+a1, a2+a3, b0+b1, b2+b3, a4+a5, a6+a7, b4+b5, b6+b7 }
but our RTL pattern did
     { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7 }
where the first and last 64 bits are the same and two middle 64 bits
swapped.
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi16&expand=2939
similarly, insn does:
     { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7,
       a8+a9, a10+a11, a12+a13, a14+a15, b8+b9, b10+b11, b12+b13, b14+b15 }
but RTL pattern did
     { a0+a1, a2+a3, a4+a5, a6+a7, a8+a9, a10+a11, a12+a13, a14+a15,
       b0+b1, b2+b3, b4+b5, b6+b7, b8+b9, b10+b11, b12+b13, b14+b15 }
again, first and last 64 bits are the same and the two middle 64 bits
swapped.

2020-04-03  Jakub Jelinek  <jakub@redhat.com>

PR target/94460
* config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
second half of first lane from first lane of second operand and
first half of second lane from second lane of first operand.

* gcc.target/i386/avx2-pr94460.c: New test.

c++: Add test for PR c++/93211

The fix for PR c++/90711 also fixed this PR.

gcc/testsuite/ChangeLog:

PR c++/93211
PR c++/90711
* g++.dg/template/koenig11.C: New test.

arm: MVE: Fix unintended change to tests

When committing my last patch I accidentally removed -mfpu=auto from the following tests. This puts it back.

testsuite/ChangeLog:
2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Put -mfpu=auto back.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.

Testing Done:
@IP: I assert this is almost no risk.

Reviewed at http://pdtlreviewboard.cambridge.arm.com/r/12880/

arm: Do not process rest of MVE header file after unsupported error

This patch makes sure the rest of the header file is not parsed if MVE is not
supported.  The user should not be including this file if MVE is not supported,
nevertheless making sure it doesn't parse the rest of the header file will
save the user from a huge error output that would be rather useless.

gcc/ChangeLog:
2020-04-03  Andre Vieira  <andre.simoesdiasvieira@arm.com>

        * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.

AArch64: Fix options canonicalization for assembler

It is currently impossible to use fp16 on any architecture higher than Armv8.3-a
due to a bug in options canonization.  This bug results in the fp16 flag not
being emitted in the assembly when it should have been.

This is caused by a complicated architectural requirement at Armv8.4-a.  On
Armv8.2-a and Armv8.3-a fp16fml is an optional extension and turning it on turns
on both fp and fp16.  However starting with Armv8.4-a fp16fml is mandatory if
fp16 is available, otherwise it's optional.

In short this means that to enable fp16fml the smallest option that needs to
passed to the assembler is Armv8.4-a+fp16.

The fix in this patch takes into account that an option may be on by default in
an architecture, but that not all the bits required to use it are on by default
in an architecture.  In such cases the difference between the two are still
emitted to the assembler.

gcc/ChangeLog:

PR target/94396
* common/config/aarch64/aarch64-common.c
(aarch64_get_extension_string_for_isa_flags): Handle default flags.

gcc/testsuite/ChangeLog:

PR target/94396
* gcc.target/aarch64/options_set_11.c: New test.
* gcc.target/aarch64/options_set_12.c: New test.
* gcc.target/aarch64/options_set_13.c: New test.
* gcc.target/aarch64/options_set_14.c: New test.
* gcc.target/aarch64/options_set_15.c: New test.
* gcc.target/aarch64/options_set_16.c: New test.
* gcc.target/aarch64/options_set_17.c: New test.
* gcc.target/aarch64/options_set_18.c: New test.
* gcc.target/aarch64/options_set_19.c: New test.
* gcc.target/aarch64/options_set_20.c: New test.
* gcc.target/aarch64/options_set_21.c: New test.
* gcc.target/aarch64/options_set_22.c: New test.
* gcc.target/aarch64/options_set_23.c: New test.
* gcc.target/aarch64/options_set_24.c: New test.
* gcc.target/aarch64/options_set_25.c: New test.
* gcc.target/aarch64/options_set_26.c: New test.

middle-end/94465 - handle released SSA names in array_ref_low_bound

array_ref_low_bound is used in dumping ARRAY_REFs which in turn
is called when basic blocks are deleted. cleanup_control_flow_pre
consciously decides to remove unreachable basic-blocks in arbitrary
order so the following makes array_ref_low_bound forgiving in the
case the SSA name with the index definition has been released
already.

2020-04-03 Richard Biener <rguenther@suse.de>

PR middle-end/94465
* tree.c (array_ref_low_bound): Deal with released SSA names
in index position.

Improve svn-rev to search for pattern at line beginning.

* gcc-git-customization.sh: Search for the pattern
at line beginning only.

amdgcn: Support unordered floating-point comparison operators

2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>

gcc/
* config/gcn/gcn.c (print_operand): Handle unordered comparison
operators.
* config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
comparison operators.

libstdc++: Fix std::to_address for debug iterators (PR 93960)

It should be valid to use std::to_address on a past-the-end iterator,
but the debug mode iterators do a check for dereferenceable in their
operator->(). That check is generally useful, so rather than remove it
this changes std::__to_address to identify a debug mode iterator and
use base().operator->() to skip the check.

PR libstdc++/93960
* include/bits/ptr_traits.h (__to_address): Add special case for debug
iterators, to avoid dereferenceable check.
* testsuite/20_util/to_address/1_neg.cc: Adjust dg-error line number.
* testsuite/20_util/to_address/debug.cc: New test.

Revert "[nvptx, libgomp] Update pr85381-{2,4}.c test-cases" [PR89713, PR94392]

In response to PR94392 commit 75efe9cb1f8938a713ce540dc3b27bc2afcd3fae
"c/94392 - only enable -ffinite-loops for C++", this reverts PR89713
commit 00908992f2a78f213d227aea8dbab014a1361df0, as apparently now again
"empty oacc loops are" no longer "removed before expand".

libgomp/
PR tree-optimization/89713
PR c/94392
* testsuite/libgomp.oacc-c-c++-common/pr85381-2.c: Again expect
'bar.sync'.
* testsuite/libgomp.oacc-c-c++-common/pr85381-4.c: Likewise.

Fix PR94443 with gsi_insert_seq_before [PR94443]

This patch is to fix the stupid mistake by using
gsi_insert_seq_before instead of gsi_insert_before.

BTW, the regression testing on one x86_64 machine from CFarm is
unable to reveal it (I guess due to native arch sandybridge?), so I
specified additional option -march=znver2 and verified the coverage.

Bootstrapped/regtested on powerpc64le-linux-gnu (P9) and
x86_64-pc-linux-gnu, also verified the fail cases in related PRs.

2020-04-03  Kewen Lin  <linkw@gcc.gnu.org>

gcc/
    PR tree-optimization/94443
    * tree-vect-loop.c (vectorizable_live_operation): Use
    gsi_insert_seq_before to replace gsi_insert_before.

gcc/testsuite/
    PR tree-optimization/94443
    * gcc.dg/vect/pr94443.c: New test.

ICF: compare type attributes for gimple_call_fntypes.

PR ipa/94445
* ipa-icf-gimple.c (func_checker::compare_gimple_call):
Compare type attributes for gimple_call_fntypes.

S/390 zTPF: Handle skip trace addresses when unwinding

Check for and handle new skip trace addresses when unwinding on zTPF.

libgcc/ChangeLog:

2020-04-03 Jim Johnston <jjohnst@us.ibm.com>

* config/s390/tpf-unwind.h (MIN_PATRANGE, MAX_PATRANGE)
(TPFRA_OFFSET): Macros removed.
(CP_CNF, cinfc_fast, CINFC_CMRESET, CINTFC_CMCENBKST)
(CINTFC_CMCENBKED, ICST_CRET, ICST_SRET, LOWCORE_PAGE3_ADDR)
(PG3_SKIPPING_OFFSET): New macros.
(__isPATrange): Use cinfc_fast for the check.
(__isSkipResetAddr): New function.
(s390_fallback_frame_state): Check for skip trace addresses. Use
either ICST_CRET or ICST_SRET to calculate return address
location.
(__tpf_eh_return): Handle skip trace addresses.

Daily bump.

Fix some comment typos in alias.c.

2020-04-02 Sandra Loosemore <sandra@codesourcery.com>

* alias.c (get_alias_set): Fix comment typos.

Fix check_effective_target_sigsetjmp for glibc targets.

2020-04-02 Sandra Loosemore <sandra@codesourcery.com>

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_sigsetjmp): Test
for __sigsetjmp as well as sigsetjmp.

Fix fortran/85982 ICE in resolve_component.

2020-04-01 Fritz Reese <foreese@gcc.gnu.org>

PR fortran/85982
* fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
attribute checking used by TYPE.

2020-04-01 Fritz Reese <foreese@gcc.gnu.org>

PR fortran/85982
* gfortran.dg/dec_structure_28.f90: New test.

[Fortran] Resolve formal args before checking DTIO

        * gfortran.h (gfc_resolve_formal_arglist): Add prototype.
        * interface.c (check_dtio_interface1): Call it.
        * resolve.c (gfc_resolve_formal_arglist): Renamed from
        resolve_formal_arglist, removed static.
        (find_arglists, resolve_types): Update calls.

        * gfortran.dg/dtio_35.f90: New.

Prevent IPA-SRA from creating calls to local comdats (PR 92676)

since r278669 (fix for PR ipa/91956), IPA-SRA makes sure that the clone
it creates is put into the same same_comdat as the original cgraph_node,
so that it can call private comdats (such as the ipa-split bits of a
comdat that is private).

However, that means that if there is non-comdat caller of a public
comdat that is modified by IPA-SRA, it now finds itself calling a
private comdat, which call graph verifier does not like (and for a
reason, in theory it can disappear and since it is private it would not
be available from other CUs).

The patch fixes this by performing the fix for PR 91956 only when the
node in question actually calls a local comdat and when it does, also
making sure that no callers come from a different same_comdat (disabling
IPA-SRA if both conditions are true), so that it plays by the rules in
both modes, does not violate the private comdat calling rule and at the
same time does not disable the transformation unnecessarily.

The patch also fixes up the calls_comdat_local of callers of the
modified node, despite that not triggering any known issues.

2020-04-02 Martin Jambor <mjambor@suse.cz>

PR ipa/92676
* ipa-sra.c (struct caller_issues): New fields candidate and
call_from_outside_comdat.
(check_for_caller_issues): Check for calls from outsied of
candidate's same_comdat_group.
(check_all_callers_for_issues): Set up issues.candidate, check result
of the new check.
(mark_callers_calls_comdat_local): New function.
(process_isra_node_results): Set calls_comdat_local of callers if
appropriate.

c/94392 - only enable -ffinite-loops for C++

This does away with enabling -ffinite-loops at -O2+ for all languages
and instead enables it selectively for C++ only.

It also makes -ffinite-loops loop-private at CFG construction time
fixing correctness issues with inlining.

2020-04-02 Richard Biener <rguenther@suse.de>

PR c/94392
* c-opts.c (c_common_post_options): Enable -ffinite-loops
for -O2 and C++11 or newer.

* common.opt (ffinite-loops): Initialize to zero.
* opts.c (default_options_table): Remove OPT_ffinite_loops
entry.
* cfgloop.h (loop::finite_p): New member.
* cfgloopmanip.c (copy_loop_info): Copy finite_p.
* ipa-icf-gimple.c (func_checker::compare_loops): Compare
finite_p.
* lto-streamer-in.c (input_cfg): Stream finite_p.
* lto-streamer-out.c (output_cfg): Likewise.
* tree-cfg.c (replace_loop_annotate): Initialize finite_p
from flag_finite_loops at CFG build time.
* tree-ssa-loop-niter.c (finite_loop_p): Check the loops
finite_p flag instead of flag_finite_loops.
* doc/invoke.texi (ffinite-loops): Adjust documentation of
default setting.

* gcc.dg/torture/pr94392.c: New testcase.

debug/94450 - remove DW_TAG_imported_unit generated in LTRANS units

This removes the DW_TAG_imported_unit we generate for each referenced
early debug unit in LTRANS units. They are more harmful than they
do good and the semantics can be read in a way making it even wrong.

2020-04-02 Richard Biener <rguenther@suse.de>

PR debug/94450
* dwarf2out.c (dwarf2out_early_finish): Remove code emitting
DW_TAG_imported_unit.

doc: RISC-V: Update binutils requirement to 2.30

Complement commit bfe78b08471f ("RISC-V: Using fmv.x.w/fmv.w.x rather
than fmv.x.s/fmv.s.x") and document a binutils 2.30 requirement in the
installation manual, matching the addition of fmv.x.w/fmv.w.x mnemonics
to GAS.

gcc/
* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
2.30.

Fix PR94401 by considering reverse overrun

The commit r10-7415 brings scalar type consideration
to eliminate epilogue peeling for gaps, but it exposed
one problem that the current handling doesn't consider
the memory access type VMAT_CONTIGUOUS_REVERSE, for
which the overrun happens on low address side.  This
patch is to make the code take care of it by updating
the offset and construction element order accordingly.

Bootstrapped/regtested on powerpc64le-linux-gnu P8
and aarch64-linux-gnu.

2020-04-02  Kewen Lin  <linkw@gcc.gnu.org>

gcc/ChangeLog

    PR tree-optimization/94401
    * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
    access type when loading halves of vector to avoid peeling for gaps.

Fix up -Wliteral-suffix warning on mti-linux.h

I've noticed while trying to reproduce PR92989 the following warning:
In file included from ./tm.h:42,
                 from ../../gcc/backend.h:28,
                 from ../../gcc/lra-assigns.c:80:
../../gcc/config/mips/mti-linux.h:31:5: warning: invalid suffix on literal; C++11 requires a space between literal and string macro [-Wliteral-suffix]
     "/%{mmicromips:micro}mips%{mel|EL:el}-"MIPS_SYSVERSION_SPEC  \
     ^
This fixes it, string concatenation works just fine even with whitespace
in between.

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

* config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
between a string literal and MIPS_SYSVERSION_SPEC macro.

sra/doc: Document param sra-max-propagations

I forgot to document the new param in invoke.texi, does the text below
look OK?

Tested with make info and make pdf.

Thanks,

Martin

2020-04-02 Martin Jambor <mjambor@suse.cz>

* doc/invoke.texi (Optimize Options): Document sra-max-propagations.

params: Decrease -param=max-find-base-term-values= default [PR92264]

For the PR in question, my proposal would be to also lower
-param=max-find-base-term-values=
default from 2000 to 200 after this, at least in the above 4
bootstraps/regtests there is nothing that would ever result in
find_base_term returning non-NULL with more than 200 VALUEs being processed.

2020-04-02 Jakub Jelinek <jakub@redhat.com>

PR rtl-optimization/92264
* params.opt (-param=max-find-base-term-values=): Decrease default
from 2000 to 200.

cselib: Reuse VALUEs on sp adjustments [PR92264]

As discussed in the PR, if !ACCUMULATE_OUTGOING_ARGS on large functions we
can have hundreds of thousands of stack pointer adjustments and cselib
creates a new VALUE after each sp adjustment, which form extremely deep
VALUE chains, which is very harmful e.g. for find_base_term.
E.g. if we have
sp -= 4
sp -= 4
sp += 4
sp += 4
sp -= 4
sp += 4
that means 7 VALUEs, one for the sp at beginning (val1), than val2 = val1 -
4, then val3 = val2 - 4, then val4 = val3 + 4, then val5 = val4 + 4, then
val6 = val5 - 4, then val7 = val6 + 4.
This patch tweaks cselib, so that it is smarter about sp adjustments.
When cselib_lookup (stack_pointer_rtx, Pmode, 1, VOIDmode) and we know
nothing about sp yet (this happens at the start of the function, for
non-var-tracking also after cselib_reset_table and for var-tracking after
processing fp_setter insn where we forget about former sp values because
that is now hfp related while everything after it is sp related), we
look it up normally, but in addition to what we have been doing before
we mark the VALUE as SP_DERIVED_VALUE_P.  Further lookups of sp + offset
are then special cased, so that it is canonicalized to that
SP_DERIVED_VALUE_P VALUE + CONST_INT (if possible).  So, for the above,
we get val1 with SP_DERIVED_VALUE_P set, then val2 = val1 - 4, val3 = val1 -
8 (note, no longer val2 - 4!), then we get val2 again, val1 again, val2
again, val1 again.
In the find_base_term visited_vals.length () > 100 find_base_term
statistics during combined x86_64-linux and i686-linux bootstrap+regtest
cycle, without the patch I see:
find_base_term > 100
returning NULL returning non-NULL
32-bit compilations 4229178 407
64-bit compilations 217523 0
with largest visited_vals.length () when returning non-NULL being 206.
With the patch the same numbers are:
32-bit compilations 1249588 135
64-bit compilations 3510 0
with largest visited_vals.length () when returning non-NULL being 173.
This shows significant reduction of the deep VALUE chains.
On powerpc64{,le}-linux, these stats didn't change at all, we have
1008 0
for all of -m32, -m64 and little-endian -m64, just the
gcc.dg/pr85180.c and gcc.dg/pr87985.c testcases which are unrelated to sp.

My earlier version of the patch, which contained just the rtl.h and cselib.c
changes, regressed some tests:
gcc.dg/guality/{pr36728-{1,3},pr68860-{1,2}}.c
gcc.target/i386/{pr88416,sse-{13,23,24,25,26}}.c
The problem with the former tests was worse debug info, where with -m32
where arg7 was passed in a stack slot we though a push later on might have
invalidated it, when it couldn't.  This is something I've solved with the
var-tracking.c (vt_initialize) changes.  In those problematic functions, we
create a cfa_base VALUE (argp) and want to record that at the start of
the function the argp VALUE is sp + off and also record that current sp
VALUE is argp's VALUE - off.  The second permanent equivalence didn't make
it after the patch though, because cselib_add_permanent_equiv will
cselib_lookup the value of the expression it wants to add as the equivalence
and if it is the same VALUE as we are calling it on, it doesn't do anything;
and due to the cselib changes for sp based accesses that is exactly what
happened.  By reversing the order of the cselib_add_permanent_equiv calls we
get both equivalences though and thus are able to canonicalize the sp based
accesses in var-tracking to the cfa_base value + offset.
The i386 FAILs were all ICEs, where we had pushf instruction pushing flags
and then pop pseudo reading that value again.  With the cselib changes,
cselib during RTL DSE is able to see through the sp adjustment and wanted
to replace_read what was done pushf, by moving the flags register into a
pseudo and replace the memory read in the pop with that pseudo.  That is
wrong for two reasons: one is that the backend doesn't have an instruction
to move the flags hard register into some other register, but replace_read
has been validating just the mem -> pseudo replacement and not the insns
emitted by copy_to_mode_reg.  And the second issue is that it is obviously
wrong to replace a stack pop which contains stack post-increment by a copy
of pseudo into destination.  dse.c has some code to handle RTX_AUTOINC, but
only uses it when actually removing stores and only when there is REG_INC
note (stack RTX_AUTOINC does not have those), in check_for_inc_dec* where
it emits the reg adjustment(s) before the insn that is going to be deleted.
replace_read doesn't remove the insn, so if it e.g. contained REG_INC note,
it would be kept there and we might have the RTX_AUTOINC not just in *loc,
but other spots.
So, the dse.c changes try to validate the added insns and punt on all
RTX_AUTOINC in *loc.  Furthermore, it seems that with the cselib.c changes
on the gfortran.dg/pr87360.f90 and gcc.target/i386/pr88416.c testcases
check_for_inc_dec{,_1} happily throws stack pointer autoinc on the floor,
which is also wrong.  While we could perhaps do the for_each_inc_dec
call regardless of whether we have REG_INC note or not, we aren't prepared
to handle e.g. REG_ARGS_SIZE distribution and thus could end up with wrong
unwind info or ICEs during dwarf2cfi.c.  So the patch also punts on those,
after all, if we'd in theory managed to try to optimize such pushes before,
we'd create wrong-code.

On x86_64-linux and i686-linux, the patch has some minor debug info coverage
differences, but it doesn't appear very significant to me.
https://github.com/pmachata/dwlocstat tool gives (where before is vanilla
trunk + the rtl.h patch but not {cselib,var-tracking,dse}.c
--enable-checking=yes,rtl,extra bootstrapped, then {cselib,var-tracking,dse}.c
hunks applied and make cc1plus, while after is trunk with the whole patch
applied).

64-bit cc1plus
before
cov% samples cumul
0..10 1232756/48% 1232756/48%
11..20 31089/1% 1263845/49%
21..30 39172/1% 1303017/51%
31..40 38853/1% 1341870/52%
41..50 47473/1% 1389343/54%
51..60 45171/1% 1434514/56%
61..70 69393/2% 1503907/59%
71..80 61988/2% 1565895/61%
81..90 104528/4% 1670423/65%
91..100 875402/34% 2545825/100%
after
cov% samples cumul
0..10 1233238/48% 1233238/48%
11..20 31086/1% 1264324/49%
21..30 39157/1% 1303481/51%
31..40 38819/1% 1342300/52%
41..50 47447/1% 1389747/54%
51..60 45151/1% 1434898/56%
61..70 69379/2% 1504277/59%
71..80 61946/2% 1566223/61%
81..90 104508/4% 1670731/65%
91..100 875094/34% 2545825/100%

32-bit cc1plus
before
cov% samples cumul
0..10 1231221/48% 1231221/48%
11..20 30992/1% 1262213/49%
21..30 36422/1% 1298635/51%
31..40 35793/1% 1334428/52%
41..50 47102/1% 1381530/54%
51..60 41201/1% 1422731/56%
61..70 65467/2% 1488198/58%
71..80 59560/2% 1547758/61%
81..90 104076/4% 1651834/65%
91..100 881879/34% 2533713/100%
after
cov% samples cumul
0..10 1230469/48% 1230469/48%
11..20 30390/1% 1260859/49%
21..30 36362/1% 1297221/51%
31..40 36042/1% 1333263/52%
41..50 47619/1% 1380882/54%
51..60 41674/1% 1422556/56%
61..70 65849/2% 1488405/58%
71..80 59857/2% 1548262/61%
81..90 104178/4% 1652440/65%
91..100 881273/34% 2533713/100%

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

PR rtl-optimization/92264
* rtl.h (struct rtx_def): Mention that call bit is used as
SP_DERIVED_VALUE_P in cselib.c.
* cselib.c (SP_DERIVED_VALUE_P): Define.
(PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
(cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
val_rtx and sp based expression where offsets cancel each other.
(preserve_constants_and_equivs): Formatting fix.
(cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
locs list for cfa_base_preserved_val if needed.  Formatting fix.
(autoinc_split): If the to be returned value is a REG, MEM or
VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
(rtx_equal_for_cselib_1): Call autoinc_split even if both
expressions are PLUS in Pmode with CONST_INT second operands.
Handle SP_DERIVED_VALUE_P cases.
(cselib_hash_plus_const_int): New function.
(cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
second operand, as well as for PRE_DEC etc. that ought to be
hashed the same way.
(cselib_subst_to_values): Substitute PLUS with Pmode and
CONST_INT operand if the first operand is a VALUE which has
SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
SP_DERIVED_VALUE_P + adjusted offset.
(cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
set SP_DERIVED_VALUE_P on it.  Set PRESERVED_VALUE_P when adding
SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
* var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
on the sp value before calling cselib_add_permanent_equiv on the
cfa_base value.
* dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
in the insn without REG_INC note.
(replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
Punt on invalid insns added by copy_to_mode_reg.  Formatting fixes.

aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]

The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits
invalid RTL.
For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits
into that mode) and x being SImode; for non-CONST_INT y it zero extends y
into SImode and compares that against x, for CONST_INT y it zero extends y
into SImode.  The problem is that when the zero extended constant isn't
usable directly, it forces it into a REG, but with y_mode mode, and then
compares against y.  That is wrong, because it should force it into a SImode
REG and compare that way.

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

PR target/94435
* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.

* gcc.target/aarch64/pr94435.c: New test.

[ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317).

Following MVE ACLE intrinsics have an issue with writeback to the base address.

vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_z_f32.

This patch fixes the bug reported in PR94317 by adding separate builtin calls to update the result and writeback to base address for the above intrinsics.

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

PR target/94317
* config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
(LDRGBWBXU_Z_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
intrinsic defintion by adding a new builtin call to writeback into base
address.
(__arm_vldrdq_gather_base_wb_u64): Likewise.
(__arm_vldrdq_gather_base_wb_z_s64): Likewise.
(__arm_vldrdq_gather_base_wb_z_u64): Likewise.
(__arm_vldrwq_gather_base_wb_s32): Likewise.
(__arm_vldrwq_gather_base_wb_u32): Likewise.
(__arm_vldrwq_gather_base_wb_z_s32): Likewise.
(__arm_vldrwq_gather_base_wb_z_u32): Likewise.
(__arm_vldrwq_gather_base_wb_f32): Likewise.
(__arm_vldrwq_gather_base_wb_z_f32): Likewise.
* config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
builtin's qualifier.
(vldrdq_gather_base_wb_z_u): Likewise.
(vldrwq_gather_base_wb_u): Likewise.
(vldrdq_gather_base_wb_u): Likewise.
(vldrwq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_z_f): Likewise.
(vldrdq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_wb_f): Likewise.
(vldrdq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_nowb_z_u): Define builtin.
(vldrdq_gather_base_nowb_z_u): Likewise.
(vldrwq_gather_base_nowb_u): Likewise.
(vldrdq_gather_base_nowb_u): Likewise.
(vldrwq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_z_f): Likewise.
(vldrdq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_s): Likewise.
(vldrwq_gather_base_nowb_f): Likewise.
(vldrdq_gather_base_nowb_s): Likewise.
* config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
pattern.
(mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
(mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_<supf>v4di):  Modify RTL pattern.
(mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_z_<supf>v4di):  Modify RTL pattern.

gcc/testsuite/ChangeLog:

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

PR target/94317
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Modify.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.

libstdc++-v3/test: Better skip for "use_service.cc"

2020-04-01 Andrea Corallo <andrea.corallo@arm.com>

* testsuite/experimental/net/execution_context/use_service.cc:
Require pthread and gthreads.

[Fortran] Fix error cleanup of select rank (PR93522)

PR fortran/93522
* match.c (gfc_match_select_rank): Fix error cleanup.

PR fortran/93522
* gfortran.dg/select_rank_4.f90: New.

S/390: Remove superfluous commutative constraint modifiers

For operands with an identical set of alternatives there is no point
in marking them commutative. This patch removes the superfluous
constraint modifiers in vector.md and vx-builtins.md since it might
slow down reload without buying us anything.

There were even two patterns where the constraint modifier was plain
wrong: "sub<VF_HW>3" and "ior_not<VT>3". Fortunately it never had any effect.

gcc/ChangeLog:

2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>

* config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
modifier.
("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
Remove constraints from expander.
* config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.

fortran : ICE in gfc_resolve_findloc PR93498

ICE occurs when findloc is used with character arguments of different
kinds.  If the character kinds are different reject the code.

Original patch provided by Steven G. Kargl  <kargl@gcc.gnu.org>.

gcc/fortran/ChangeLog:

PR fortran/93498
* check.c (gfc_check_findloc):  If the kinds of the arguments
differ goto label "incompat".

gcc/testsuite/ChangeLog:

PR fortran/93498
* gfortran.dg/pr93498_1.f90:  New test.
* gfortran.dg/pr93498_2.f90:  New test.

fortran: ICE equivalence with an element of an array PR94030

Deferred size arrays can not be used in equivalance statements.

gcc/fortran/ChangeLog:

PR fortran/94030
* resolve.c (resolve_equivalence): Correct formatting
around the label "identical_types". Instead of using
gfc_resolve_array_spec use is_non_constants_shape_array
to determine whether the array can be used in a in an
equivalence statement.

gcc/testsuite/ChangeLog:

PR fortran/94030
* gfortran.dg/pr94030_1.f90
* gfortran.dg/pr94030_2.f90

Daily bump.

d: Fix new tests gdc.dg/pr93038.d and gdc.dg/pr93038b.d in r10-7320 fail

The scan-file match is likely too strict to always succeed, so instead
have split it up into a set of smaller matches.

gcc/testsuite/ChangeLog:

PR d/94315
* gdc.dg/pr93038.d: Split dg-final into multiple tests.
* gdc.dg/pr93038b.d: Likewise.

d: Fix gdc.dg/pr92216.d FAILs on 32-bit targets

The symbol being scanned for only matched on 64-bit targets.

gcc/testsuite/ChangeLog:

PR d/94321
* gdc.dg/pr92216.d: Update to work on targets with 16 or 32-bit
pointers.

libstdc++: Move "free books" list from fsf.org to gnu.org

* doc/xml/manual/appendix_free.xml: Move "free books" list from
fsf.org to gnu.org.
* doc/html/manual/appendix_free.html: Regenerate.

analyzer: handle compound assignments [PR94378]

PR analyzer/94378 reports a false -Wanalyzer-malloc-leak
when returning a struct containing a malloc-ed pointer.

The issue is that the assignment code was not handling
compound copies, only copying top-level values from region to region,
and not copying child values.

This patch introduces a region_model::copy_region function, using
it for assignments and when analyzing function return values.
It recursively copies nested values within structs, unions, and
arrays, fixing the bug.

gcc/analyzer/ChangeLog:
PR analyzer/94378
* checker-path.cc: Include "bitmap.h".
* constraint-manager.cc: Likewise.
* diagnostic-manager.cc: Likewise.
* engine.cc: Likewise.
(exploded_node::detect_leaks): Pass null region_id to pop_frame.
* program-point.cc: Include "bitmap.h".
* program-state.cc: Likewise.
* region-model.cc (id_set<region_id>::id_set): Convert to...
(region_id_set::region_id_set): ...this.
(svalue_id_set::svalue_id_set): New ctor.
(region_model::copy_region): New function.
(region_model::copy_struct_region): New function.
(region_model::copy_union_region): New function.
(region_model::copy_array_region): New function.
(stack_region::pop_frame): Drop return value.  Add
"result_dst_rid" param; if it is non-null, use copy_region to copy
the result to it.  Rather than capture and pass a single "known
used" return value to be used by purge_unused_values, instead
gather and pass a set of known used return values.
(root_region::pop_frame): Drop return value.  Add "result_dst_rid"
param.
(region_model::on_assignment): Use copy_region.
(region_model::on_return): Likewise for the result.
(region_model::on_longjmp): Pass null for pop_frame's
result_dst_rid.
(region_model::update_for_return_superedge): Pass the region for the
return value of the call, if any, to pop_frame, rather than setting
the lvalue for the lhs of the result.
(region_model::pop_frame): Drop return value.  Add
"result_dst_rid" param.
(region_model::purge_unused_svalues): Convert third param from an
svalue_id * to an svalue_id_set *, updating the initial populating
of the "used" bitmap accordingly.  Don't remap it when done.
(struct selftest::coord_test): New selftest fixture, extracted from...
(selftest::test_dump_2): ...here.
(selftest::test_compound_assignment): New selftest.
(selftest::test_stack_frames): Pass null to new param of pop_frame.
(selftest::analyzer_region_model_cc_tests): Call the new selftest.
* region-model.h (class id_set): Delete template.
(class region_id_set): Reimplement, using old id_set implementation.
(class svalue_id_set): Likewise.  Convert from auto_sbitmap to
auto_bitmap.
(region::get_active_view): New accessor.
(stack_region::pop_frame): Drop return value.  Add
"result_dst_rid" param.
(root_region::pop_frame): Likewise.
(region_model::pop_frame): Likewise.
(region_model::copy_region): New decl.
(region_model::purge_unused_svalues): Convert third param from an
svalue_id * to an svalue_id_set *.
(region_model::copy_struct_region): New decl.
(region_model::copy_union_region): New decl.
(region_model::copy_array_region): New decl.

gcc/testsuite/ChangeLog:
PR analyzer/94378
* gcc.dg/analyzer/compound-assignment-1.c: New test.
* gcc.dg/analyzer/compound-assignment-2.c: New test.
* gcc.dg/analyzer/compound-assignment-3.c: New test.

subreg: Fix PR94123, SVN r273240 causes gcc.target/powerpc/pr87507.c to fail

Segher's patch that added -fsplit-wide-types-early and enabled by default
for rs6000, caused pr87507.c to FAIL because when running lower-subreg
earlier, we don't see any pseudo-to-pseudo copies of our wide type,
which are created by combine, therefore, we skip decomposing our TImode
accesses. The fix here is just to always run the third pass of lower-subreg
instead of disabling it if we ran the second pass.

2020-04-01 Peter Bergner <bergner@linux.ibm.com>

PR rtl-optimization/94123
* lower-subreg.c (pass_lower_subreg3::gate): Remove test for
flag_split_wide_types_early.