Paul Mackerras [Sat, 2 May 2020 03:28:19 +0000 (13:28 +1000)]
Implement the extswsli instruction
This mainly required the addition of an entry to the opcode 31 decode
table and a 32-bit sign-extender in the rotator.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Wed, 6 May 2020 23:59:19 +0000 (09:59 +1000)]
Merge pull request #166 from paulusmack/master
MSR fixes, implement privilege checking, implement dcbz
Paul Mackerras [Mon, 4 May 2020 05:17:04 +0000 (15:17 +1000)]
execute1: Fix interrupt delivery during slow instructions
During slow instructions such as multiply or divide, if a decrementer
(or other asynchronous) interrupt becomes pending, it disrupts the
logic that keeps stall asserted until the end of the slow
instruction, and the interrupt logic starts trying to deliver the
interrupt before the slow instruction has finished.
To fix that, make the interrupt logic wait until it sees e_in.valid
set before setting exception to 1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 30 Apr 2020 23:00:21 +0000 (09:00 +1000)]
wishbone_debug_master: Fix address auto-increment for memory writes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 6 May 2020 04:15:22 +0000 (14:15 +1000)]
Merge remote-tracking branch 'remotes/origin/master'
Paul Mackerras [Sun, 3 May 2020 22:31:18 +0000 (08:31 +1000)]
dcache: Don't assert on dcbz cache hit
We can hit the assert for req_op = OP_STORE_HIT and reloading in the
case of dcbz, since it looks like a store. Therefore we need to
exclude that case from the assert.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Wed, 6 May 2020 03:27:17 +0000 (13:27 +1000)]
Merge pull request #165 from mikey/xics
Implement XICS compliant interrupt controller
Anton Blanchard [Fri, 1 May 2020 09:52:59 +0000 (19:52 +1000)]
Merge pull request #167 from tomtor/patch-1
Fix Rust README.md
Tom Vijlbrief [Fri, 1 May 2020 07:39:49 +0000 (09:39 +0200)]
Update README.md
Fix formatting of Rust README
Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
Paul Mackerras [Wed, 29 Apr 2020 01:37:02 +0000 (11:37 +1000)]
Change the default cross compiler prefix to powerpc64le-linux-gnu-
That is what is used by the packaged cross-compilers on (at least)
Fedora and Ubuntu.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 29 Apr 2020 01:11:22 +0000 (11:11 +1000)]
Makefile: fix typo
Fix a typo which meant that the console tests weren't getting
executed by 'make check'.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 28 Apr 2020 23:09:23 +0000 (09:09 +1000)]
tests: Add a test for privileged instruction interrupts
This adds a test that tries to execute various privileged instructions
with MSR[PR] = 1. This also incidentally tests some of the MSR bit
manipulations.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 28 Apr 2020 08:11:52 +0000 (18:11 +1000)]
dcache: Implement the dcbz instruction
This adds logic to dcache and loadstore1 to implement dcbz. For now
it zeroes a single cache line (by default 64 bytes), not 128 bytes
like IBM Power processors do.
The dcbz operation is performed much like a load miss, except that
we are writing zeroes to memory instead of reading. As each ack
comes back, we write zeroes to the BRAM instead of data from memory.
In this way we zero the line in memory and also zero the line of
cache memory, establishing the line in the cache if it wasn't already
resident. If it was already resident then we overwrite the existing
line in the cache.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 3 Apr 2020 03:50:17 +0000 (14:50 +1100)]
Plumb insn_type through to loadstore1
In preparation for adding a TLB to the dcache, this plumbs the
insn_type from execute1 through to loadstore1, so that we can have
other operations besides loads and stores (e.g. tlbie) going to
loadstore1 and thence to the dcache. This also plumbs the unit field
of the decode ROM from decode2 through to execute1 to simplify the
logic around which ops need to go to loadstore1.
The load and store data formatting are now not conditional on the
op being OP_LOAD or OP_STORE. This eliminates the inferred latches
clocked by each of the bits of r.op that we were getting previously.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 28 Apr 2020 09:38:58 +0000 (19:38 +1000)]
execute1: Generate privileged instruction interrupts when MSR[PR] = 1
This adds logic to execute1 to check, when MSR[PR] = 1, whether each
instruction arriving to be executed is a privileged instruction.
If it is, a privileged-instruction type program interrupt is generated.
For the mtspr and mfspr instructions, we need to look at bit 20 of the
instruction (bit 4 of the SPR number) to determine if the SPR is
privileged.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 28 Apr 2020 10:28:20 +0000 (20:28 +1000)]
execute1: Improve architecture compliance of MSR and related instructions
This makes our treatment of the MSR conform better with the ISA.
- On reset, initialize the MSR to have the SF and LE bits set and
all the others reset. For good measure initialize r properly too.
- Fix the bit numbering in msr_copy (the code was using big-endian
bit numbers, not little-endian).
- Use constants like MSR_EE to index MSR bits instead of expressions
like '63 - 48', for readability.
- Set MSR[SF, LE] and clear MSR[PR, IR, DR, RI] on interrupts.
- Copy the relevant fields for rfid instead of using msr_copy, because
the partial function fields of the MSR should be left unchanged,
not zeroed. Our implementation of rfid is like the architecture
description of hrfid, because we don't implement hypervisor mode.
- Return the whole MSR for mfmsr.
- Implement the L field for mtmsrd (L=1 copies just EE and RI).
- For mtmsrd with L=0, leave out the HV, ME and LE bits as per the arch.
- For mtmsrd and rfid, if PR ends up set, then also set EE, IR and DR
as per the arch.
- A few other minor tidyups (no semantic change).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Thu, 23 Apr 2020 09:50:16 +0000 (19:50 +1000)]
Merge pull request #164 from mikey/tags
Add VHDL TAGS
Anton Blanchard [Thu, 23 Apr 2020 09:49:24 +0000 (19:49 +1000)]
Merge pull request #163 from paulusmack/excpath
Fix the bug causing the assert that Mikey hit
Michael Neuling [Thu, 23 Apr 2020 04:37:29 +0000 (14:37 +1000)]
XICS test case
Checks interrupt masking and priorities.
Adds to `make test_xics` which is run in `make check` also.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 23 Apr 2020 04:36:05 +0000 (14:36 +1000)]
XICS interrupt controller
New unified ICP and ICS XICS compliant interrupt controller.
Configurable number of hardware sources.
Fixed hardware source number based on hardware line taken. All
hardware interrupts are a fixed priority. Level interrupts supported
only.
Hardwired to 0xc0004000 in SOC (UART is kept at 0xc0002000).
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 23 Apr 2020 04:28:59 +0000 (14:28 +1000)]
Wire up sim uart TX interrupt
TX is always ready, so just always sent interrupt when enabled.
No RX interrupt.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 23 Apr 2020 04:28:08 +0000 (14:28 +1000)]
Add calls to dis/enable potato uart IRQ
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Wed, 8 Apr 2020 07:35:32 +0000 (17:35 +1000)]
Add VHDL TAGS
Adds `make TAGS`
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Wed, 22 Apr 2020 03:54:38 +0000 (13:54 +1000)]
execute1: Don't execute ld/st instruction when taking interrupt
This fixes a bug in the logic where we would still send a load
or store instruction to loadstore1 even though we have decided
to take an asynchronous interrupt.
Reported-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Thu, 16 Apr 2020 08:42:42 +0000 (18:42 +1000)]
Merge pull request #162 from antonblanchard/bin2hex-removal
rust_lib_demo: Remove bin2hex.py
Anton Blanchard [Thu, 16 Apr 2020 08:42:13 +0000 (18:42 +1000)]
Merge pull request #161 from antonblanchard/hello-world-Makefile
hello_world: Use Makefile automatic variables
Anton Blanchard [Thu, 16 Apr 2020 07:44:17 +0000 (17:44 +1000)]
rust_lib_demo: Remove bin2hex.py
We are using scripts/bin2hex.py, so we can get rid of this copy.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 16 Apr 2020 07:40:52 +0000 (17:40 +1000)]
Merge pull request #160 from antonblanchard/tomtor-rust-2
Rebase Tom's rust demo patches
Anton Blanchard [Thu, 16 Apr 2020 07:38:07 +0000 (17:38 +1000)]
hello_world: Use Makefile automatic variables
Fix a few whitespace issues while here.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 16 Apr 2020 07:14:18 +0000 (17:14 +1000)]
rust_lib_demo: Use common console code
Use a symlink to share the console code in hello_world. Not ideal,
but we can improve on it later.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 16 Apr 2020 07:08:15 +0000 (17:08 +1000)]
rust_lib_demo: Update package dependencies to fix a build error
I'm hitting a build error:
error[E0050]: method `alloc` has 2 parameters but the declaration in trait `core::alloc::AllocRef::alloc` has 3
Updating the version of linked_list_allocator fixes it. I updated
heapless to while I was at it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Tom Vijlbrief [Fri, 3 Jan 2020 09:34:21 +0000 (10:34 +0100)]
Add Rust demo
Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
Anton Blanchard [Thu, 16 Apr 2020 05:15:07 +0000 (15:15 +1000)]
Merge pull request #159 from shenki/fusesoc-ram-16k
FuseSoC needs 16kB of RAM
Joel Stanley [Wed, 15 Apr 2020 06:36:54 +0000 (16:06 +0930)]
Set default RAM to be 16K in microwatt.core
This allows it to run hello world out of the box.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Wed, 15 Apr 2020 06:32:21 +0000 (16:02 +0930)]
README: hello world needs 16KB of RAM
STACK_TOP is at 0x2000 (8K) so we need something larger as a minimum.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Anton Blanchard [Tue, 14 Apr 2020 02:47:00 +0000 (12:47 +1000)]
Merge pull request #158 from paulusmack/excpath
Fix exception stuff so we make timing again
Anton Blanchard [Thu, 9 Apr 2020 01:47:05 +0000 (11:47 +1000)]
Merge pull request #157 from paulusmack/master
Start using cache-inhibited loads and stores to access the UART
Paul Mackerras [Mon, 6 Apr 2020 04:07:45 +0000 (14:07 +1000)]
Decode attn in the major opcode decode table
This decodes attn using entry 0 of the major_decode_rom_array table
instead of a special case in the decode1_1 process. This means that
only the major opcode (the top 6 bits) is checked at decode time.
To make sure the instruction is attn not some random illegal pattern,
we now check bits 1-10 of the instruction at execute time and
generate an illegal instruction interrupt if those bits are not
0100000000.
This reduces LUT consumption by 42 LUTs on the Arty A7-100.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Apr 2020 03:24:08 +0000 (13:24 +1000)]
Decode sc in the major opcode decode table
This decodes sc using entry 17 of the major_decode_rom_array table
instead of a special case in the decode1_1 process. This means that
only the major opcode (the top 6 bits) is checked at decode time.
To make sure that the instruction is sc not scv, we now check bit
1 of the instruction at execute time and generate an illegal
instruction interrupt if it is 0 (indicating scv). The level field
of the sc instruction is now ignored.
This reduces LUT consumption by 31 LUTs on the Arty A7-100.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Apr 2020 03:07:00 +0000 (13:07 +1000)]
Remove sim_config instruction
It's not used any more, and it's not in the ISA.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 7 Apr 2020 10:07:33 +0000 (20:07 +1000)]
execute1: Implement trap instructions properly
This implements the trap instructions (tw, twi, td, tdi) using
much of the same code as is used for the cmp/cmpl instructions.
A 5-bit comparison value is generated, and for cmp/cmpl, the
appropriate 3 bits are used to update the destination CR, and for
trap instructions, the comparison value is ANDed with the TO
field, and an exception is generated if any bit of the result
is 1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Apr 2020 02:58:42 +0000 (12:58 +1000)]
Consolidate trap variants under a single OP_TRAP
This replaces OP_TD, OP_TDI, OP_TW and OP_TWI with a single OP_TRAP,
distinguishing the cases by the input_reg_b and is_32bit fields of
the decode ROM. This adds the twi and td cases to the decode tables.
For now we make all of the trap instructions unconditionally generate
a trap-type program interrupt if the TO field of the instruction is
all ones, and do nothing otherwise.
This reduces the number of values in insn_type_t from 65 to 62,
meaning that an insn_type_t can now be encoded in 6 bits rather
than 7.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 7 Apr 2020 08:38:18 +0000 (18:38 +1000)]
execute1: Simplify the interrupt logic a little
This makes some simplifications to the interrupt logic which will
help with later commits.
- When irq_valid is set, don't set exception to 1 until we have a
valid instruction. That means we can remove the if e_in.valid = '1'
test from the exception = '1' block.
- Don't assert stall_out on the first cycle of delivering an
interrupt. If we do get another instruction in the next cycle,
nothing will happen because we have ctrl.irq_state set and we
will just continue writing the interrupt registers.
- Make sure we deliver as many completions as we got instructions,
otherwise the outstanding instruction count in control.vhdl gets
out of sync.
- In writeback, make sure all of the other write enables are ignored
when e_in.exc_write_enable is set.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Apr 2020 02:20:36 +0000 (12:20 +1000)]
Rename OP_MCRF to OP_CROP and trim insn_type_t
OP_MCRF covers the CR logical ops as well as mcrf since commit
c05441bf4793 ("Implement CRNOR and friends"), so this renames
OP_MCRF to OP_CROP. The OP_* values for the individual CR logical
ops (OP_CRAND, etc.) are not used, so remove them from insn_type_t.
No functional change.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Apr 2020 04:09:20 +0000 (14:09 +1000)]
tests: Put an attn instruction at 0x700
This puts an attn instruction at offset 0x700 in each of the tests
so that the test will terminate if a program interrupt is taken.
This means that we can implement the tw instruction to cause a
program interrupt.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 3 Apr 2020 06:02:14 +0000 (17:02 +1100)]
Give exceptions a separate path to writeback
This adds separate fields in Execute1ToWritebackType for use in
writing SRR0/1 (and in future other SPRs) on an interrupt. With
this, we make timing once again on the Arty A7-100 -- previously
we were missing by 0.2ns, presumably due to the result mux being
wider than before.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 3 Apr 2020 02:47:20 +0000 (13:47 +1100)]
tests: Update executables
As suggested by Michael Neuling.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 3 Apr 2020 02:46:36 +0000 (13:46 +1100)]
tests: Adjust header inclusions and Makefile.test
This fixes the decrementer, illegal and sc tests to compile
successfully with cross-compilers that don't provide unistd.h
or string.h. Instead of those headers we include stddef.h.
This also fixes tests/Makefile.test to do what one expects
when CROSS_COMPILE is defined in the environment.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 1 Apr 2020 04:48:30 +0000 (15:48 +1100)]
hello_world: Use ldcix/stdcix to access UART
This is one step towards ultimately removing the address-based
cache inhibit hack from dcache.vhdl.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 1 Apr 2020 04:46:43 +0000 (15:46 +1100)]
hello_world: Adjust header inclusions and Makefile
Currently hello_world fails to build with distro cross compiler
packages such as Debian gcc-powerpc64-linux-gnu, because it doesn't
provide string.h or unistd.h. In fact we don't need them, we just
need stddef.h. This adds #include <stddef.h> to console.h to get
size_t defined. We also add #include "console.h" to console.c.
The hello_world Makefile currently hard-codes CROSS_COMPILE on
non-PPC machines. This means that a command like:
$ CROSS_COMPILE=powerpc64le-linux-gnu- make
doesn't do what you expect; it just tries to use powerpc64le-linux-gcc
regardless. Adding a '?' makes it do what one expects.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Thu, 2 Apr 2020 23:36:36 +0000 (10:36 +1100)]
Merge pull request #155 from mikey/exceptions
Add decrementer, illegal and system call exceptions
Michael Neuling [Tue, 31 Mar 2020 06:32:38 +0000 (17:32 +1100)]
Add test cases for new exceptions and supervisor state
This adds test cases for:
- sc, illegals and decrementer exceptions
- decrementer overflow
- rfid
- mt/mf sprg0/1 srr0/1
- mtdec
- mtmsrd
- sc
It also adds these test cases to make check/check_light
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 31 Mar 2020 06:32:09 +0000 (17:32 +1100)]
Add sc, illegal and decrementer exceptions and some supervisor state
This adds the following exceptions:
- 0x700 program check (for illegal instructions)
- 0x900 decrementer
- 0xc00 system call
This also adds some supervisor state:
- decremeter
- msr
(SPRG0/1 and SRR0/1 already exist as fast SPRs)
It also adds some supporting instructions:
- rfid
- mtmsrd
- mfmsr
- sc
MSR state is added but only EE is used in this patch set. Other bits
are read/written but are not used at all.
This adds a 2 stage state machine to execute1.vhdl. This state machine
allows fast SPRS SRR0/1 to be written in different cycles. This state
machine can be extended later to add DAR and DSISR SPR writing for
more complex exceptions like page faults.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 24 Mar 2020 22:58:18 +0000 (09:58 +1100)]
Plumb attn instruction through to execute1
Currently we decode attn but we just mark it as an illegal.
This adds a separate case statement in execute 1 for attn to terminate
the core. Illegals also do this currently but we are soon implementing
a 0x700 execption for them.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 17 Mar 2020 04:25:34 +0000 (15:25 +1100)]
Breakout the console code so it can be reused.
No functional change.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Mon, 30 Mar 2020 02:46:23 +0000 (13:46 +1100)]
Merge pull request #153 from paulusmack/master
Load/store improvements
Paul Mackerras [Mon, 30 Mar 2020 01:39:08 +0000 (12:39 +1100)]
loadstore1: Add support for cache-inhibited load and store instructions
This adds support for lbzcix, lhzcix, lwzcix, ldcix, stbcix, sthcix,
stwcix and stdcix. The temporary hack where accesses to addresses of
the form 0xc??????? are made non-cacheable is left in for now to avoid
making existing programs non-functional.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 29 Mar 2020 22:16:58 +0000 (09:16 +1100)]
loadstore1: Move load data formatting from writeback to loadstore1
This puts all the data formatting (byte rotation based on lowest three
bits of the address, byte reversal, sign extension, zero extension)
in loadstore1. Writeback now simply sends the data provided to the
register files.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 28 Mar 2020 09:24:13 +0000 (20:24 +1100)]
loadstore1: Move logic from dcache to loadstore1
So that the dcache could in future be used by an MMU, this moves
logic to do with data formatting, rA updates for update-form
instructions, and handling of unaligned loads and stores out of
dcache and into loadstore1. For now, dcache connects only to
loadstore1, and loadstore1 now has the connection to writeback.
Dcache generates a stall signal to loadstore1 which indicates that
the request presented in the current cycle was not accepted and
should be presented again. However, loadstore1 doesn't currently
use it because we know that we can never hit the circumstances
where it might be set.
For unaligned transfers, loadstore1 generates two requests to
dcache back-to-back, and then waits to see two acks back from
dcache (cycles where d_in.valid is true).
Loadstore1 now has a FSM for tracking how many acks we are
expecting from dcache and for doing the rA update cycles when
necessary. Handling for reservations and conditional stores is
still in dcache.
Loadstore1 now generates its own stall signal back to decode2,
so we no longer need the logic in execute1 that generated the stall
for the first two cycles.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Wed, 11 Mar 2020 01:46:01 +0000 (12:46 +1100)]
Merge pull request #152 from mikey/gitignore
gitignore: Fix RAM file name
Paul Mackerras [Thu, 5 Mar 2020 04:02:10 +0000 (15:02 +1100)]
dcache: Remove LOAD_UPDATE2 state
Since we removed one cycle from the load hit case, we actually no
longer need the extra cycle provided by having the LOAD_UPDATE
state. Therefore this makes the load hit case in the IDLE and
NEXT_DWORD states go to LOAD_UPDATE2 rather than LOAD_UPDATE.
Then we remove LOAD_UPDATE and then rename LOAD_UPDATE2 to
LOAD_UPDATE.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 4 Mar 2020 05:20:05 +0000 (16:20 +1100)]
dcache: Trim one cycle from the load hit path
Currently we don't get the result from a load that hits in the dcache
until the fourth cycle after the instruction was presented to
loadstore1. This trims this back to 3 cycles by taking the low order
bits of the address generated in loadstore1 into dcache directly (not
via the output register of loadstore1) and using them to address the
read port of the dcache data RAM. We use the lower 12 address bits
here in the expectation that any reasonable data cache design will
have a set size of 4kB or less in order to avoid the aliasing problems
that can arise with a virtually-indexed physically-tagged cache if
the set size is greater than the smallest page size provided by the
MMU.
With this we can get rid of r2 and drive the signals going to
writeback from r1, since the load hit data is now available one
cycle earlier. We need a multiplexer on the read address of the
data cache RAM in order to handle the second doubleword of an
unaligned access.
One small complication is that we now need an extra cycle in the case
of an unaligned load which misses in the data cache and which reads
the 2nd-last and last doublewords of a cache line. This is the reason
for the PRE_NEXT_DWORD state; if we just go straight to NEXT_DWORD
then we end up having the write of the last doubleword of the cache
line and the read of that same doubleword occurring in the same
cycle, which means we read stale data rather than the just-fetched
data.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Fri, 28 Feb 2020 04:54:21 +0000 (15:54 +1100)]
gitignore: Fix RAM file name
From:
commit
8e0389b9736c60572e13ef5eeb50d3a775c3ffc6
Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Wed Oct 23 12:08:55 2019 +1100
ram: Rework main RAM interface
We need to change the name.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Thu, 27 Feb 2020 21:09:08 +0000 (08:09 +1100)]
dcache: Implement load-reserve and store-conditional instructions
This involves plumbing the (existing) 'reserve' and 'rc' bits in
the decode tables down to dcache, and 'rc' and 'store_done' bits
from dcache to writeback.
It turns out that we had 'RC' set in the 'rc' column for several
ordinary stores and for the attn instruction. This corrects them
to 'NONE', and sets the 'rc' column to 'ONE' for the conditional
stores.
In writeback we now have logic to set CR0 when the input from dcache
has rc = 1.
In dcache we have the reservation itself, which has a valid bit
and the address down to cache line granularity. We don't currently
store the reservation length. For a store conditional which fails,
we set a 'cancel_store' signal which inhibits the write to the
cache and prevents the state machine from starting a bus cycle or
going to the STORE_WAIT_ACK state. Instead we set r1.stcx_fail
which causes the instruction to complete in the next cycle with
rc=1 and store_done=0.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 26 Feb 2020 00:55:36 +0000 (11:55 +1100)]
dcache: Add support for unaligned loads and stores
For an unaligned load or store, we do the first doubleword (dword) of
the transfer as normal, but then go to a new NEXT_DWORD state of the
state machine to do the cache tag lookup for the second dword of the
transfer. From the NEXT_DWORD state we have much the same transitions
to other states as from the IDLE state (the transitions for OP_LOAD_HIT
are a bit different but almost identical for the other op values).
We now do the preparation of the data to be written in loadstore1,
that is, byte reversal if necessary and rotation by a number of
bytes based on the low 3 bits of the address. We do rotation not
shifting so we have the bytes that need to go into the second
doubleword in the right place in the low bytes of the data sent to
dcache. The rotation and byte reversal are done in a single step
with one multiplexer per byte by setting the select inputs for each
byte appropriately.
This also fixes writeback to not write the register value until it
has received both pieces of an unaligned load value.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Sat, 22 Feb 2020 21:51:33 +0000 (08:51 +1100)]
Merge pull request #150 from sharkcz/selinux
make the sources volume mount SELinux friendly
Paul Mackerras [Fri, 21 Feb 2020 01:34:23 +0000 (12:34 +1100)]
dcache: Fix obscure bug and minor cleanups
The obscure bug is that a non-cacheable load with update would never
do the update and would never complete the instruction. This is fixed
by making state NC_LOAD_WAIT_ACK go to LOAD_UPDATE2 if r1.req.update
is set.
The slow load forms with update can go to LOAD_UPDATE2 at the end
rather than LOAD_UPDATE, thus saving a cycle. Loads with a cache
hit need the LOAD_UPDATE state in the third cycle since they are
not writing back until the 4th cycle, when the state is LOAD_UPDATE2.
Slow loads (cacheable loads that miss and non-cacheable loads)
currently go to LOAD_UPDATE in the cycle after they see
r1.wb.ack = 1 for the last time, but that cycle is the cycle where
they write back, and the following cycle does nothing. Going to
LOAD_UPDATE2 in those cases saves a cycle and makes them consistent
with the load hit case.
The logic in the RELOAD_WAIT_ACK case doesn't need to check
r1.req.load = '1' since we only ever use RELOAD_WAIT_ACK for loads.
There are also some whitespace fixes and a typo fix.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 19 Feb 2020 04:39:46 +0000 (15:39 +1100)]
Remove single-issue constraint for most loads and stores
This removes the constraint that loads and stores are single-issue,
at the expense of a stall of at least 2 cycles for every load and
store.
To do this, we plumb the existing stall signal that was generated
in dcache to core, where it gets ORed with the stall signal from
execute1. Execute1 generates a stall signal for the first two
cycles of each load and store, and dcache generates the stall
signal in the 3rd and subsequent cycles if it needs to.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 16 Jan 2020 02:18:56 +0000 (13:18 +1100)]
execute1: Use truth table embedded in instruction for CR logical ops
It turns out that CR logical instructions have the truth table of
the operation embedded in the instruction word. This means that we
can collect the two input operand bits into a 2-bit value and use
that as the index to select the appropriate bit from the instruction
word.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Dan Horák [Thu, 23 Jan 2020 10:37:00 +0000 (11:37 +0100)]
make the sources volume mount SELinux friendly
Signed-off-by: Dan Horák <dan@danny.cz>
Anton Blanchard [Thu, 23 Jan 2020 03:36:15 +0000 (14:36 +1100)]
Merge pull request #147 from antonblanchard/diamond-1
Some Diamond fixes
Anton Blanchard [Thu, 23 Jan 2020 00:43:25 +0000 (11:43 +1100)]
Fix a Diamond issue in decode2
By using a temporary we avoid a build issue in Diamond.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 23 Jan 2020 00:37:24 +0000 (11:37 +1100)]
Fix a Diamond build issue in writeback
Diamond doesn't like the "" & method of converting std_logic to a single bit
std_logic_vector. Thanks to Olof Kindgren for this patch.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 22 Jan 2020 04:15:48 +0000 (15:15 +1100)]
Merge pull request #146 from antonblanchard/vhpi-cleanup
Consolidate VHPI code
Anton Blanchard [Wed, 22 Jan 2020 03:50:45 +0000 (14:50 +1100)]
Consolidate VHPI code
We had many copies of the VHPI marshalling/unmarshalling code.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 22 Jan 2020 03:48:07 +0000 (14:48 +1100)]
Merge pull request #145 from antonblanchard/sim_console-fix
sim_console: Use cfmakeraw() and add option for ctrl-c to exit sim
Anton Blanchard [Wed, 22 Jan 2020 03:27:40 +0000 (14:27 +1100)]
sim_console: Use cfmakeraw() and add option for ctrl-c to exit sim
No need to open code a bunch of random termios flags, use cfmakeraw().
Most of the time we want ctrl-c to exit the current simulation, so
make that the default.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 03:09:57 +0000 (14:09 +1100)]
Update Makefile.synth after Paul's patches
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 03:09:36 +0000 (14:09 +1100)]
Merge pull request #134 from paulusmack/master
Add bypass from execute1 output to input
Anton Blanchard [Tue, 21 Jan 2020 02:30:13 +0000 (13:30 +1100)]
Merge pull request #142 from antonblanchard/ghdl-synthesis-3
Initial support for ghdl synthesis
Anton Blanchard [Tue, 21 Jan 2020 02:28:43 +0000 (13:28 +1100)]
Merge pull request #144 from antonblanchard/update-README
Add some information about GHDL backend issues
Anton Blanchard [Tue, 21 Jan 2020 02:20:23 +0000 (13:20 +1100)]
Merge pull request #143 from antonblanchard/use-docker
Add an option to use Docker
Anton Blanchard [Tue, 21 Jan 2020 02:13:41 +0000 (13:13 +1100)]
Add some information about GHDL backend issues
A number of people have tripped up on GHDL backend issues. We
require either the LLVM or gcc backend, because the mcode backend
can't link against libraries which we use for simulated memory
and UART. Make that clearer, and point people at the Docker images
if they are having issues building ghdl.
Also point at the prebuilt micropython image.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 02:03:50 +0000 (13:03 +1100)]
Add an option to use Docker
Some distros don't have a version of ghdl with the LLVM or GCC backend,
so add a Docker image as an alternative.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 17 Jan 2020 23:02:07 +0000 (10:02 +1100)]
Initial support for ghdl synthesis
A first pass at ghdl synthesis using yosys and nextpnr. It runs hello world
or micropython if the FPGA has enough block RAM (eg ECP5 85F). The hello
world testcase also loops UART rx to tx in software (ie not a hardware
loopback).
It uses Docker images, so no software needs to be installed. If you prefer
podman you can use that too. Edit Makefile.synth to configure your FPGA,
JTAG device etc.
To build:
make -f Makefile.synth
and to program:
make -f Makefile.synth prog
A few issues:
We need to add PLL support. Right now Microwatt runs at whatever the
external clock frequency is and the baud rate gets scaled by how far off
50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud
rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a
50MHz clock the UART is 115200.
It uses a large amount of resources, way more than it should. There are
still some ghdl/yosys issues to be sorted out.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 00:41:41 +0000 (11:41 +1100)]
Merge pull request #140 from antonblanchard/rework-makefile
Fix Makefile dependency issue with files in vhdl/*
Anton Blanchard [Sun, 19 Jan 2020 23:50:45 +0000 (10:50 +1100)]
Fix Makefile dependency issue with files in vhdl/*
GHDL doesn't seem to have a way to specify the location of the object
file it writes, so right now they are all ending up in the root
directory. The Makefile rules did not reflect that, so make would
continually the files in fpga/*
Fix the rules to match what GHDL is doing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 00:11:30 +0000 (11:11 +1100)]
Merge pull request #141 from antonblanchard/update-dependencies.py
Improve dependencies.py and add a --synth option
Anton Blanchard [Mon, 20 Jan 2020 23:38:48 +0000 (10:38 +1100)]
Improve dependencies.py and add a --synth option
dependencies.py was pretty terrible at actually determining
dependencies. This improves it and also adds a --synth option.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 11:44:32 +0000 (22:44 +1100)]
Merge pull request #136 from antonblanchard/uart-rx-metastability
Add a few FFs on the RX input to avoid metastability issues
Anton Blanchard [Sun, 19 Jan 2020 03:34:15 +0000 (14:34 +1100)]
Add a few FFs on the RX input to avoid metastability issues
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 11:02:56 +0000 (22:02 +1100)]
Merge pull request #139 from antonblanchard/reduce-mem
Reduce mem
Anton Blanchard [Sun, 19 Jan 2020 10:28:32 +0000 (21:28 +1100)]
Reduce simulated and default FPGA RAM to 384kB
Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 10:18:05 +0000 (21:18 +1100)]
Add log2ceil and use it in bram code
We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 10:48:34 +0000 (21:48 +1100)]
Merge pull request #138 from antonblanchard/micropython-update
Update micropython
Anton Blanchard [Sun, 19 Jan 2020 09:22:09 +0000 (20:22 +1100)]
Update micropython
The current version of micropython in tests/micropython.bin is ancient.
Bug #135 points out that more recent versions are much smaller and they
also handle restart when ctrl+D is pressed.
Save all three versions of the file (elf, bin and hex) in micropython/
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 07:40:34 +0000 (18:40 +1100)]
Merge pull request #137 from antonblanchard/hello-world
hello_world updates
Anton Blanchard [Sun, 19 Jan 2020 05:15:22 +0000 (16:15 +1100)]
hello_world updates
Shrink hello_world a bit (from 12kB to 8kB).
Include the built images
Add 0x10 and 0x100 entry points
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Tue, 14 Jan 2020 12:20:42 +0000 (23:20 +1100)]
decode1: Mark subfic as pipelined
This seems just to have been missed in commit
f291efa26690 ("decode1:
Mark ALU ops using carry as pipelined").
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 14 Jan 2020 10:55:33 +0000 (21:55 +1100)]
countzero: Add a register to help make timing
This adds a register in the middle of the countzero computation,
so that we now have two cycles to count leading or trailing zeroes
instead of just one. Execute1 now outputs a one-cycle stall signal
when it encounters a cntlz* or cnttz* instruction. With this,
the countzero path no longer fails timing on the Artix-7 at 100MHz.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>