whitequark [Mon, 12 Aug 2019 13:37:18 +0000 (13:37 +0000)]
hdl.xfrm: CEInserter→EnableInserter.
Fixes #166.
whitequark [Thu, 8 Aug 2019 10:56:23 +0000 (10:56 +0000)]
hdl.ast: hash-cons ValueKey.
This speeds up elaboration by ~10%.
whitequark [Thu, 8 Aug 2019 10:23:35 +0000 (10:23 +0000)]
tracer: use sys._getframe directly.
This speeds up elaboration by ~30-40%.
whitequark [Thu, 8 Aug 2019 08:09:28 +0000 (08:09 +0000)]
compat.fhdl.decorators: port from oMigen.
whitequark [Thu, 8 Aug 2019 07:45:34 +0000 (07:45 +0000)]
compat.fhdl.module: fix finalization of transformed compat submodules.
Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.
After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.
whitequark [Wed, 7 Aug 2019 09:25:20 +0000 (09:25 +0000)]
vendor.lattice_ice40: add iCE5LP2K support.
whitequark [Wed, 7 Aug 2019 09:06:27 +0000 (09:06 +0000)]
vendor.lattice_ice40: add iCE40UP3K support.
whitequark [Wed, 7 Aug 2019 09:00:41 +0000 (09:00 +0000)]
vendor.lattice_ice40: add iCE5LP1K support.
whitequark [Sun, 4 Aug 2019 23:27:47 +0000 (23:27 +0000)]
vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.
On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
whitequark [Sun, 4 Aug 2019 23:23:06 +0000 (23:23 +0000)]
vendor.xilinx_spartan_3_6: reconsider bitgen defaults.
Previously changed in
27063a3b.
I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
whitequark [Sun, 4 Aug 2019 14:16:02 +0000 (14:16 +0000)]
vendor.xilinx_spartan_3_6: set bitgen defaults to `-g Binary:Yes -g Compress`.
* `-g Binary:Yes` should be overridable.
* `-g Compress` is a good default.
whitequark [Sun, 4 Aug 2019 14:12:02 +0000 (14:12 +0000)]
vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen.
-w stands for "override output file", and supplying user options
should not remove it.
whitequark [Sun, 4 Aug 2019 13:48:33 +0000 (13:48 +0000)]
vendor.xilinx_spartan_3_6: do not use retiming by default.
This was added in
b404d603, probably by mistake, and is certainly
wrong given that we do not (yet) correctly mark CDC FFs.
whitequark [Sun, 4 Aug 2019 13:19:50 +0000 (13:19 +0000)]
vendor.xilinx_spartan_3_6: force use of bash on UNIX.
whitequark [Sun, 4 Aug 2019 13:18:29 +0000 (13:18 +0000)]
build.plat: allow selecting a specific UNIX shell interpreter.
Mostly because vendor tools have bashisms.
whitequark [Sun, 4 Aug 2019 00:30:50 +0000 (00:30 +0000)]
vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.
whitequark [Sat, 3 Aug 2019 23:57:50 +0000 (23:57 +0000)]
back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.
(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
whitequark [Sat, 3 Aug 2019 23:43:57 +0000 (23:43 +0000)]
back.rtlil: actually match shape of left hand side.
This comes up in code such as:
Array([Signal(1), Signal(8)]).eq(Const(0, 8))
whitequark [Sat, 3 Aug 2019 22:59:33 +0000 (22:59 +0000)]
vendor.lattice_ice40: add missing signal indexing.
whitequark [Sat, 3 Aug 2019 22:52:58 +0000 (22:52 +0000)]
build.run: use keyword-only arguments where appropriate.
whitequark [Sat, 3 Aug 2019 22:52:34 +0000 (22:52 +0000)]
compat.fhdl.specials: track changes in build.plat.
whitequark [Sat, 3 Aug 2019 18:52:24 +0000 (18:52 +0000)]
hdl.dsl: reword m.If(~True) warning to be more clear.
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
whitequark [Sat, 3 Aug 2019 18:36:58 +0000 (18:36 +0000)]
build.plat,vendor: automatically create sync domain from default_clk.
But only if it is not defined by the programmer.
Closes #57.
whitequark [Sat, 3 Aug 2019 18:19:40 +0000 (18:19 +0000)]
hdl.ir: allow adding more than one domain in missing domain callback.
This is useful for injecting complex power-on reset logic.
whitequark [Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)]
hdl.ir: don't expose as ports missing domains added via elaboratables.
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
whitequark [Sat, 3 Aug 2019 16:28:03 +0000 (16:28 +0000)]
build.plat: add default_rst, to be used with default_clk.
whitequark [Sat, 3 Aug 2019 16:18:46 +0000 (16:18 +0000)]
build.plat: add default_clk{,_constraint,_frequency}.
This is the equivalent of oMigen's default_clk and default_clk_period
except the period is taken from the resource.
whitequark [Sat, 3 Aug 2019 15:44:02 +0000 (15:44 +0000)]
hdl.ir: allow returning elaboratables from missing domain callback.
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).
See #57.
whitequark [Sat, 3 Aug 2019 15:31:00 +0000 (15:31 +0000)]
hdl.ir: raise DomainError if a domain is used but not defined.
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
whitequark [Sat, 3 Aug 2019 14:54:20 +0000 (14:54 +0000)]
hdl.ir: call back from Fragment.prepare if a clock domain is missing.
See #57.
whitequark [Sat, 3 Aug 2019 14:00:29 +0000 (14:00 +0000)]
hdl.dsl: warn on suspicious statements like `m.If(~True):`.
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.
Fixes #159.
whitequark [Sat, 3 Aug 2019 13:44:44 +0000 (13:44 +0000)]
Improve test added in
29fee01f to not leak warnings.
whitequark [Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)]
back.rtlil: fix sim-synth mismatch with assigns following switches.
Closes #155.
whitequark [Sat, 3 Aug 2019 13:21:09 +0000 (13:21 +0000)]
hdl.ast: fix typo.
whitequark [Sat, 3 Aug 2019 13:05:41 +0000 (13:05 +0000)]
hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
Fixes #148.
whitequark [Sat, 3 Aug 2019 12:44:52 +0000 (12:44 +0000)]
hdl.ast, back.rtlil: add source locations to anonymous wires.
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.
Also fixes incorrect source location on value.part().
whitequark [Sat, 3 Aug 2019 12:30:39 +0000 (12:30 +0000)]
hdl.ir: warn if .elaborate() returns None.
Fixes #164.
whitequark [Wed, 31 Jul 2019 05:19:24 +0000 (05:19 +0000)]
hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
Fixes #154.
N. Engelhardt [Sun, 21 Jul 2019 07:49:21 +0000 (15:49 +0800)]
vendor: don't emit duplicate iobuf submodule names.
These are no longer allowed after commit
698b005.
N. Engelhardt [Fri, 19 Jul 2019 12:39:47 +0000 (20:39 +0800)]
hdl.dsl: add getters to m.submodules.
Alain Péteut [Sun, 14 Jul 2019 22:28:06 +0000 (00:28 +0200)]
lib.fifo: fix typo.
Staf Verhaegen [Sun, 14 Jul 2019 19:15:09 +0000 (21:15 +0200)]
Pin: Add extra hierarchy level for name derivation
William D. Jones [Sun, 14 Jul 2019 17:28:19 +0000 (13:28 -0400)]
build.run: Ensure batch script returns proper error code.
whitequark [Fri, 12 Jul 2019 12:17:18 +0000 (12:17 +0000)]
back.pysim: correctly add gtkwave traces for signals with decoders.
William D. Jones [Wed, 10 Jul 2019 15:29:09 +0000 (11:29 -0400)]
build.dsl: Add optional name_suffix to Resource.family.
whitequark [Wed, 10 Jul 2019 12:54:59 +0000 (12:54 +0000)]
back.pysim: avoid malformed VCD files when a decoder uses tabs.
whitequark [Wed, 10 Jul 2019 12:46:46 +0000 (12:46 +0000)]
hdl.ir: make UnusedElaboratable a real warning.
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
whitequark [Tue, 9 Jul 2019 19:45:15 +0000 (19:45 +0000)]
back.rtlil: add decodings to cases when switching on a signal.
Fixes #134.
whitequark [Tue, 9 Jul 2019 19:28:09 +0000 (19:28 +0000)]
back.verilog: run proc_prune for much cleaner output.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@
44bcb7a1.
whitequark [Tue, 9 Jul 2019 19:18:02 +0000 (19:18 +0000)]
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@
93bc5aff.
Jacob Lifshay [Tue, 9 Jul 2019 07:29:01 +0000 (00:29 -0700)]
tracer: add PyPy support to get_var_name().
Fixes #141.
whitequark [Tue, 9 Jul 2019 02:44:03 +0000 (02:44 +0000)]
build.dsl: add Resource.family abstraction.
whitequark [Mon, 8 Jul 2019 11:15:04 +0000 (11:15 +0000)]
build.{dsl,res}: allow platform-dependent attributes using callables.
Fixes #132.
whitequark [Mon, 8 Jul 2019 10:59:15 +0000 (10:59 +0000)]
hdl.rec: respect modifications to signals in Record.like().
Fixes #126.
whitequark [Mon, 8 Jul 2019 10:48:07 +0000 (10:48 +0000)]
back.rtlil: don't name-prefix signals connected to instance ports.
This gives particularly pathological results on IO buffers, like:
connect \D_OUT_0 \user_led_0_user_led_0__o
Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
whitequark [Mon, 8 Jul 2019 10:41:45 +0000 (10:41 +0000)]
build.{dsl,res}: allow removing attributes from subsignals.
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.
Fixes #128.
whitequark [Mon, 8 Jul 2019 10:32:41 +0000 (10:32 +0000)]
build.dsl: allow assertions on subsignal widths.
This is useful when building abstractions around resources where
the pin names are user-specified.
Fixes #129.
whitequark [Mon, 8 Jul 2019 10:26:49 +0000 (10:26 +0000)]
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
Fixes #125.
whitequark [Mon, 8 Jul 2019 10:20:24 +0000 (10:20 +0000)]
test: fix Travis.
whitequark [Mon, 8 Jul 2019 10:12:15 +0000 (10:12 +0000)]
test: generate examples to verilog as part of unit tests.
This is to make sure
806a62c2 doesn't happen again.
whitequark [Mon, 8 Jul 2019 10:00:16 +0000 (10:00 +0000)]
examples/basic/ctr_ce: fix outdated syntax.
whitequark [Mon, 8 Jul 2019 10:03:20 +0000 (10:03 +0000)]
compat.genlib.fsm: fix after commit
dac62754.
whitequark [Mon, 8 Jul 2019 09:57:14 +0000 (09:57 +0000)]
hdl.xfrm: don't overwrite source locations on ClockDomain signals.
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
whitequark [Mon, 8 Jul 2019 09:50:07 +0000 (09:50 +0000)]
hdl.{dsl,mem,xfrm}: inject appropriate source locations.
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.
On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
whitequark [Mon, 8 Jul 2019 09:33:01 +0000 (09:33 +0000)]
back.rtlil: ignore empty source locations.
This was a bug introduced during refactoring in
2492f490.
whitequark [Mon, 8 Jul 2019 09:23:33 +0000 (09:23 +0000)]
hdl.ast: use keyword-only arguments as appropriate.
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
whitequark [Mon, 8 Jul 2019 09:09:40 +0000 (09:09 +0000)]
back.rtlil: attach source locations to switches, not processes.
This effectively reverts and reimplements half of commit
82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.
After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
whitequark [Mon, 8 Jul 2019 08:57:36 +0000 (08:57 +0000)]
back.rtlil: use a more principled approach to attributes. NFC.
This also refactors the RTLIL builder to use a more aspect-oriented
approach.
Alain Péteut [Sun, 7 Jul 2019 21:36:32 +0000 (23:36 +0200)]
vendor.xilinx_7series: generate also binary bitfile.
Fixes #139.
William D. Jones [Sun, 7 Jul 2019 20:44:48 +0000 (16:44 -0400)]
vendor.xilinx_spartan_3_6: Add Spartan3A family support.
whitequark [Sun, 7 Jul 2019 02:30:56 +0000 (02:30 +0000)]
vendor.lattice_ecp5: don't leave LUT inputs disconnected.
This causes YosysHQ/nextpnr#301.
Fixes #136.
whitequark [Sun, 7 Jul 2019 01:03:59 +0000 (01:03 +0000)]
hdl.dsl: further clarify error message for incorrect nesting.
Fixes #133.
whitequark [Sun, 7 Jul 2019 00:59:57 +0000 (00:59 +0000)]
hdl.dsl: clarify error message for incorrect nesting.
Refs #133.
whitequark [Sun, 7 Jul 2019 00:59:34 +0000 (00:59 +0000)]
hdl.dsl: gracefully handle FSM with no states.
whitequark [Sun, 7 Jul 2019 00:41:03 +0000 (00:41 +0000)]
build.plat: source a script with toolchain environment.
Fixes #131.
whitequark [Sun, 7 Jul 2019 00:18:56 +0000 (00:18 +0000)]
build.run: only use os.path on the target OS.
Before this commit, BuildPlan.add_file would use os.path.normpath,
which would be the wrong thing for cross-builds.
whitequark [Sun, 7 Jul 2019 00:07:55 +0000 (00:07 +0000)]
build.run: make BuildProducts abstract, add LocalBuildProducts.
This makes it clear that we plan to have remote builds as well.
Also, document everything in build.run.
whitequark [Sat, 6 Jul 2019 23:09:46 +0000 (23:09 +0000)]
build.plat, vendor.*: don't join strings passed as _opts overrides.
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.
Fixes #130.
whitequark [Sat, 6 Jul 2019 18:44:25 +0000 (18:44 +0000)]
build.run: make sure BuildProducts._root is not easily accessible.
Staf Verhaegen [Thu, 4 Jul 2019 15:13:56 +0000 (17:13 +0200)]
vendor.xilinx_{7series,spartan6}: Support extra VHDL files.
whitequark [Wed, 3 Jul 2019 16:34:31 +0000 (16:34 +0000)]
hdl.dsl: fix src_loc_at for FSM state signal.
whitequark [Wed, 3 Jul 2019 16:27:54 +0000 (16:27 +0000)]
back.rtlil: emit \src attributes for processes via Switch and Assign.
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
whitequark [Wed, 3 Jul 2019 15:25:14 +0000 (15:25 +0000)]
hdl.ast: fix src_loc_at for Mux().
whitequark [Wed, 3 Jul 2019 15:07:44 +0000 (15:07 +0000)]
build.res: detect physical conflicts earlier.
This is useful for two reasons:
1. nMigen can provide better error messages than the platform and
do it earlier in the build pipeline.
2. Many platforms handle diffpairs by only constraining the P pin;
the N pin is completely ignored. If this is undetected,
downstream users (human or software) can rely on this
information assuming it is correct and introduce more errors.
(Of course, this will not catch every mistake, but the most
common is a copy-paste issue, and that will handle it.)
Fixes #124.
whitequark [Wed, 3 Jul 2019 14:49:20 +0000 (14:49 +0000)]
hdl.rec: thread src_loc_at to all inner Signals and Records.
whitequark [Wed, 3 Jul 2019 14:43:03 +0000 (14:43 +0000)]
vendor: give names to IO buffer instances.
Fixes #123.
whitequark [Wed, 3 Jul 2019 14:35:48 +0000 (14:35 +0000)]
hdl.rec: accept Record(src_loc_at=...).
whitequark [Wed, 3 Jul 2019 13:28:57 +0000 (13:28 +0000)]
compat.fhdl.specials: mark CompatMemory as Elaboratable.
This suppresses a warning that is not useful in the compat context.
whitequark [Wed, 3 Jul 2019 13:25:12 +0000 (13:25 +0000)]
compat.fhdl.specials: use "sync" as default domain, not "sys".
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
whitequark [Wed, 3 Jul 2019 13:24:00 +0000 (13:24 +0000)]
compat.fhdl.specials: fix Memory.get_port() after
94e8f479.
This also makes sure the native ports are instantiated for correct
clock domain.
whitequark [Wed, 3 Jul 2019 13:19:15 +0000 (13:19 +0000)]
compat.fhdl.structure: fix If/Elif/Else after
32446831.
Sebastien Bourdeauducq [Wed, 3 Jul 2019 02:25:32 +0000 (10:25 +0800)]
lattice_ecp5: fix get_input
whitequark [Tue, 2 Jul 2019 19:02:16 +0000 (19:02 +0000)]
hdl.ast: recognize a Enum used as decoder and format it better.
whitequark [Tue, 2 Jul 2019 18:37:02 +0000 (18:37 +0000)]
hdl.mem: fix naming of registers inside unnamed memories.
Before this commit, `None` would leak into the vcd file with pysim.
Alain Péteut [Tue, 2 Jul 2019 08:44:12 +0000 (10:44 +0200)]
build.plat: add iter_extra_files method.
* vendor.*: employ iter_extra_files.
whitequark [Tue, 2 Jul 2019 18:06:50 +0000 (18:06 +0000)]
back.rtlil: emit \sig$next wires instead of \$next\sig. NFC.
Just a bit more readable.
whitequark [Tue, 2 Jul 2019 18:05:34 +0000 (18:05 +0000)]
back.rtlil: do not emit $next wires for comb signals.
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.
This change results in major improvements in Verilog readability.
See also #98.
whitequark [Tue, 2 Jul 2019 17:44:55 +0000 (17:44 +0000)]
hdl.rec: implement slicing by component names.
Fixes #121.
whitequark [Tue, 2 Jul 2019 17:35:00 +0000 (17:35 +0000)]
hdl.rec: implement Record.like.
Fixes #120.
Alain Péteut [Tue, 2 Jul 2019 07:47:40 +0000 (09:47 +0200)]
vendor.xilinx_7series: read extra .xdc files.