yosys.git
7 years agorecover_reduce: Rename recover_reduce_core to recover_reduce
Robert Ou [Sun, 27 Aug 2017 09:01:32 +0000 (02:01 -0700)]
recover_reduce: Rename recover_reduce_core to recover_reduce

Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.

Also rename to .cc (rather than .cpp) for consistency.

7 years agorecover_reduce: Add driver script for the $reduce_* recover feature
Robert Ou [Fri, 11 Aug 2017 09:00:33 +0000 (02:00 -0700)]
recover_reduce: Add driver script for the $reduce_* recover feature

Conflicts:
passes/techmap/Makefile.inc

7 years agorecover_reduce_core: Finish implementing the core function
Robert Ou [Fri, 11 Aug 2017 08:48:22 +0000 (01:48 -0700)]
recover_reduce_core: Finish implementing the core function

7 years agorecover_reduce_core: Initial commit
Robert Ou [Fri, 11 Aug 2017 07:40:31 +0000 (00:40 -0700)]
recover_reduce_core: Initial commit

Conflicts:
passes/techmap/Makefile.inc

7 years agoDon't track , ... contradictions through x/z-bits
Clifford Wolf [Fri, 25 Aug 2017 14:18:17 +0000 (16:18 +0200)]
Don't track , ... contradictions through x/z-bits

7 years agoAdd removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr
Clifford Wolf [Fri, 25 Aug 2017 14:02:15 +0000 (16:02 +0200)]
Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr

7 years agoMerge branch 'extract_fa'
Clifford Wolf [Fri, 25 Aug 2017 11:42:13 +0000 (13:42 +0200)]
Merge branch 'extract_fa'

7 years agoFurther improve extract_fa (seems to be fully functional now)
Clifford Wolf [Fri, 25 Aug 2017 11:41:54 +0000 (13:41 +0200)]
Further improve extract_fa (seems to be fully functional now)

7 years agoRename "adders" to "extract_fa"
Clifford Wolf [Fri, 25 Aug 2017 10:04:40 +0000 (12:04 +0200)]
Rename "adders" to "extract_fa"

7 years agoFix bug in write_smt2 (export logic driving hierarchical cells before exporting regs)
Clifford Wolf [Fri, 25 Aug 2017 09:44:48 +0000 (11:44 +0200)]
Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs)

7 years agoTowards more generic "adder" function extractor
Clifford Wolf [Wed, 23 Aug 2017 12:20:10 +0000 (14:20 +0200)]
Towards more generic "adder" function extractor

7 years agoAdd experimental adders pass
Clifford Wolf [Tue, 22 Aug 2017 11:48:55 +0000 (13:48 +0200)]
Add experimental adders pass

7 years agoAdd hashlib support for hashing of pools
Clifford Wolf [Tue, 22 Aug 2017 11:04:33 +0000 (13:04 +0200)]
Add hashlib support for hashing of pools

7 years agoAdd consteval support for $_ANDNOT_ and $_ORNOT_
Clifford Wolf [Tue, 22 Aug 2017 11:04:05 +0000 (13:04 +0200)]
Add consteval support for $_ANDNOT_ and $_ORNOT_

7 years agoRemove some dead code from fsm_map
Clifford Wolf [Mon, 21 Aug 2017 13:02:16 +0000 (15:02 +0200)]
Remove some dead code from fsm_map

7 years agoRename "singleton" pass to "uniquify"
Clifford Wolf [Sun, 20 Aug 2017 10:31:50 +0000 (12:31 +0200)]
Rename "singleton" pass to "uniquify"

7 years agoMore intuitive handling of "cd .." for singleton modules
Clifford Wolf [Fri, 18 Aug 2017 22:15:12 +0000 (00:15 +0200)]
More intuitive handling of "cd .." for singleton modules

7 years agoAdd "sim -zinit -rstlen"
Clifford Wolf [Fri, 18 Aug 2017 10:54:17 +0000 (12:54 +0200)]
Add "sim -zinit -rstlen"

7 years agoMerge branch 'sim'
Clifford Wolf [Fri, 18 Aug 2017 09:45:15 +0000 (11:45 +0200)]
Merge branch 'sim'

7 years agoAdd "sim" support for memories
Clifford Wolf [Fri, 18 Aug 2017 09:44:50 +0000 (11:44 +0200)]
Add "sim" support for memories

7 years agoAdd Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
Clifford Wolf [Fri, 18 Aug 2017 09:40:08 +0000 (11:40 +0200)]
Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()

7 years agoAdd support for assert/assume/cover to "sim" command
Clifford Wolf [Fri, 18 Aug 2017 08:24:14 +0000 (10:24 +0200)]
Add support for assert/assume/cover to "sim" command

7 years agoAdd writeback mode to "sim" command
Clifford Wolf [Thu, 17 Aug 2017 13:54:51 +0000 (15:54 +0200)]
Add writeback mode to "sim" command

7 years agoImprove "sim" command
Clifford Wolf [Thu, 17 Aug 2017 10:27:08 +0000 (12:27 +0200)]
Improve "sim" command

7 years agoMerge pull request #386 from azonenberg/gpak-counters
Clifford Wolf [Wed, 16 Aug 2017 13:58:29 +0000 (15:58 +0200)]
Merge pull request #386 from azonenberg/gpak-counters

Bug fixes to GP_COUNTx and GP_PGEN cells in GreenPAK technology library

7 years agoAdd "sim" command skeleton
Clifford Wolf [Wed, 16 Aug 2017 11:05:21 +0000 (13:05 +0200)]
Add "sim" command skeleton

7 years agoFixed more issues with GreenPAK counter sim models
Andrew Zonenberg [Tue, 15 Aug 2017 07:50:31 +0000 (00:50 -0700)]
Fixed more issues with GreenPAK counter sim models

7 years agoUpdated PGEN model to have level triggered reset (matches actual hardware behavior
Andrew Zonenberg [Tue, 15 Aug 2017 00:15:56 +0000 (17:15 -0700)]
Updated PGEN model to have level triggered reset (matches actual hardware behavior

7 years agoFixed bug in GP_COUNTx model
Andrew Zonenberg [Mon, 14 Aug 2017 23:28:59 +0000 (16:28 -0700)]
Fixed bug in GP_COUNTx model

7 years agoFixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
Andrew Zonenberg [Mon, 14 Aug 2017 23:08:54 +0000 (16:08 -0700)]
Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high

7 years agoMerge branch 'azonenberg-rmports'
Clifford Wolf [Tue, 15 Aug 2017 09:32:55 +0000 (11:32 +0200)]
Merge branch 'azonenberg-rmports'

7 years agoMostly coding style related fixes in rmports pass
Clifford Wolf [Tue, 15 Aug 2017 09:32:35 +0000 (11:32 +0200)]
Mostly coding style related fixes in rmports pass

7 years agoMerge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports
Clifford Wolf [Tue, 15 Aug 2017 09:19:55 +0000 (11:19 +0200)]
Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports

7 years agoMerge pull request #381 from azonenberg/countfix
Clifford Wolf [Mon, 14 Aug 2017 19:47:26 +0000 (21:47 +0200)]
Merge pull request #381 from azonenberg/countfix

Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate

7 years agoMerge pull request #383 from azonenberg/abcfnames
Clifford Wolf [Mon, 14 Aug 2017 19:46:17 +0000 (21:46 +0200)]
Merge pull request #383 from azonenberg/abcfnames

abc: Allow +/ filenames in the abc command

7 years agoMerge pull request #382 from azonenberg/jsoniofix
Clifford Wolf [Mon, 14 Aug 2017 19:45:54 +0000 (21:45 +0200)]
Merge pull request #382 from azonenberg/jsoniofix

json: Parse inout correctly rather than as an output

7 years agoMerge pull request #384 from azonenberg/crtechlib
Clifford Wolf [Mon, 14 Aug 2017 19:45:29 +0000 (21:45 +0200)]
Merge pull request #384 from azonenberg/crtechlib

CoolRunner-II technology library improvements

7 years agocoolrunner2: Add INVERT parameter to some BUFGs
Robert Ou [Mon, 7 Aug 2017 11:01:18 +0000 (04:01 -0700)]
coolrunner2: Add INVERT parameter to some BUFGs

7 years agocoolrunner2: Add FFs with clock enable to cells_sim.v
Robert Ou [Tue, 1 Aug 2017 18:58:01 +0000 (11:58 -0700)]
coolrunner2: Add FFs with clock enable to cells_sim.v

7 years agoabc: Allow +/ filenames in the abc command
Robert Ou [Fri, 11 Aug 2017 04:10:07 +0000 (21:10 -0700)]
abc: Allow +/ filenames in the abc command

7 years agojson: Parse inout correctly rather than as an output
Robert Ou [Mon, 7 Aug 2017 20:37:01 +0000 (13:37 -0700)]
json: Parse inout correctly rather than as an output

7 years agormports: Now remove ports from cell instances if we optimized them out of that cell
Andrew Zonenberg [Mon, 14 Aug 2017 18:44:05 +0000 (11:44 -0700)]
rmports: Now remove ports from cell instances if we optimized them out of that cell

7 years agoProcessModule is no longer virtual (why was it in the first place?)
Andrew Zonenberg [Mon, 14 Aug 2017 18:18:09 +0000 (11:18 -0700)]
ProcessModule is no longer virtual (why was it in the first place?)

7 years agormports now works on all modules in the design, not just the top.
Andrew Zonenberg [Mon, 14 Aug 2017 18:16:44 +0000 (11:16 -0700)]
rmports now works on all modules in the design, not just the top.

7 years agoUpdated Makefile to reflect opt_rmports being renamed to rmports
Andrew Zonenberg [Mon, 14 Aug 2017 18:04:56 +0000 (11:04 -0700)]
Updated Makefile to reflect opt_rmports being renamed to rmports

7 years agoRenamed opt_rmports pass to rmports
Andrew Zonenberg [Mon, 14 Aug 2017 18:00:18 +0000 (11:00 -0700)]
Renamed opt_rmports pass to rmports

7 years agoFixed typo in GP_COUNT8 sim model
Andrew Zonenberg [Fri, 11 Aug 2017 23:55:31 +0000 (16:55 -0700)]
Fixed typo in GP_COUNT8 sim model

7 years agoFixed typo in error message
Andrew Zonenberg [Tue, 8 Aug 2017 03:46:00 +0000 (20:46 -0700)]
Fixed typo in error message

7 years agoChanged LEVEL resets for GP_COUNTx to be properly synthesizeable
Andrew Zonenberg [Tue, 8 Aug 2017 03:42:19 +0000 (20:42 -0700)]
Changed LEVEL resets for GP_COUNTx to be properly synthesizeable

7 years agoChanged LEVEL resets to be edge triggered anyway
Andrew Zonenberg [Tue, 8 Aug 2017 03:33:08 +0000 (20:33 -0700)]
Changed LEVEL resets to be edge triggered anyway

7 years agoAdded level-triggered reset support to GP_COUNTx simulation models
Andrew Zonenberg [Tue, 8 Aug 2017 03:29:05 +0000 (20:29 -0700)]
Added level-triggered reset support to GP_COUNTx simulation models

7 years agoFixed undeclared "count" in GP_COUNT8_ADV
Andrew Zonenberg [Tue, 8 Aug 2017 03:21:55 +0000 (20:21 -0700)]
Fixed undeclared "count" in GP_COUNT8_ADV

7 years agoFixed undeclared "count" in GP_COUNT14_ADV
Andrew Zonenberg [Tue, 8 Aug 2017 03:21:18 +0000 (20:21 -0700)]
Fixed undeclared "count" in GP_COUNT14_ADV

7 years agoFixed typo in last commit
Andrew Zonenberg [Tue, 8 Aug 2017 03:20:17 +0000 (20:20 -0700)]
Fixed typo in last commit

7 years agoFinished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide...
Andrew Zonenberg [Tue, 8 Aug 2017 03:19:17 +0000 (20:19 -0700)]
Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.

7 years agoFixed typo in COUNT8 model
Andrew Zonenberg [Mon, 7 Aug 2017 22:49:30 +0000 (15:49 -0700)]
Fixed typo in COUNT8 model

7 years agoMoved GP_POR out of digital cells b/c it has delays
Andrew Zonenberg [Sun, 6 Aug 2017 15:40:23 +0000 (08:40 -0700)]
Moved GP_POR out of digital cells b/c it has delays

7 years agoImproved cells_sim_digital model for GP_COUNT8
Andrew Zonenberg [Sun, 6 Aug 2017 00:33:44 +0000 (17:33 -0700)]
Improved cells_sim_digital model for GP_COUNT8

7 years agoRefactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
Andrew Zonenberg [Sat, 5 Aug 2017 23:33:24 +0000 (16:33 -0700)]
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital

7 years agoImproved handling of constant connections in opt_rmports
Andrew Zonenberg [Fri, 11 Aug 2017 23:47:07 +0000 (16:47 -0700)]
Improved handling of constant connections in opt_rmports

7 years agoFixed handling of cell ports that aren't wires
Andrew Zonenberg [Fri, 11 Aug 2017 23:16:25 +0000 (16:16 -0700)]
Fixed handling of cell ports that aren't wires

7 years agoopt_rmports: Fixed incorrect handling of multi-bit nets
Andrew Zonenberg [Fri, 11 Aug 2017 22:07:27 +0000 (15:07 -0700)]
opt_rmports: Fixed incorrect handling of multi-bit nets

7 years agoRemoved commented out debug code
Andrew Zonenberg [Fri, 11 Aug 2017 20:46:01 +0000 (13:46 -0700)]
Removed commented out debug code

7 years agoAdded opt_rmports pass (remove unconnected ports from top-level modules)
Andrew Zonenberg [Fri, 11 Aug 2017 20:40:37 +0000 (13:40 -0700)]
Added opt_rmports pass (remove unconnected ports from top-level modules)

7 years agoAdd support for set-reset cell variants to opt_rmdff
Clifford Wolf [Wed, 9 Aug 2017 11:29:52 +0000 (13:29 +0200)]
Add support for set-reset cell variants to opt_rmdff

7 years agoAuto-detect JSON front-end
Clifford Wolf [Wed, 9 Aug 2017 11:28:52 +0000 (13:28 +0200)]
Auto-detect JSON front-end

7 years agoAdd handling of constant reset signals to opt_rmdff
Clifford Wolf [Sun, 6 Aug 2017 11:27:18 +0000 (13:27 +0200)]
Add handling of constant reset signals to opt_rmdff

7 years agoAdd "yosys-smtbmc --smtc-init --smtc-top --noinit"
Clifford Wolf [Fri, 4 Aug 2017 15:09:08 +0000 (17:09 +0200)]
Add "yosys-smtbmc --smtc-init --smtc-top --noinit"

7 years agoAdd "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"
Clifford Wolf [Fri, 4 Aug 2017 09:24:58 +0000 (11:24 +0200)]
Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"

7 years agoFix typo in "abc" pass help message
Clifford Wolf [Sat, 29 Jul 2017 14:21:58 +0000 (16:21 +0200)]
Fix typo in "abc" pass help message

7 years agoAdd merging of "past FFs" to verific importer
Clifford Wolf [Fri, 28 Jul 2017 22:07:02 +0000 (00:07 +0200)]
Add merging of "past FFs" to verific importer

7 years agoAdd consolidation of init attributes to opt_clean, some opt_clean log fixes
Clifford Wolf [Fri, 28 Jul 2017 21:11:52 +0000 (23:11 +0200)]
Add consolidation of init attributes to opt_clean, some opt_clean log fixes

7 years agoAdd minimal support for PSL in VHDL via Verific
Clifford Wolf [Fri, 28 Jul 2017 15:37:09 +0000 (17:37 +0200)]
Add minimal support for PSL in VHDL via Verific

7 years agoAdd simple VHDL+PSL example
Clifford Wolf [Fri, 28 Jul 2017 13:33:30 +0000 (15:33 +0200)]
Add simple VHDL+PSL example

7 years agoImprove Verific HDL language options
Clifford Wolf [Fri, 28 Jul 2017 13:32:54 +0000 (15:32 +0200)]
Improve Verific HDL language options

7 years agoFix handling of non-user-declared Verific netbus
Clifford Wolf [Fri, 28 Jul 2017 09:31:27 +0000 (11:31 +0200)]
Fix handling of non-user-declared Verific netbus

7 years agoImprove Verific SVA importer
Clifford Wolf [Thu, 27 Jul 2017 12:05:09 +0000 (14:05 +0200)]
Improve Verific SVA importer

7 years agoAdd counter.sv SVA test
Clifford Wolf [Thu, 27 Jul 2017 10:37:16 +0000 (12:37 +0200)]
Add counter.sv SVA test

7 years agoAdd log_warning_noprefix() API, Use for Verific warnings and errors
Clifford Wolf [Thu, 27 Jul 2017 10:17:04 +0000 (12:17 +0200)]
Add log_warning_noprefix() API, Use for Verific warnings and errors

7 years agoAdd "verific -import -n" and "verific -import -nosva"
Clifford Wolf [Thu, 27 Jul 2017 09:54:45 +0000 (11:54 +0200)]
Add "verific -import -n" and "verific -import -nosva"

7 years agoImprove SVA tests, add Makefile and scripts
Clifford Wolf [Thu, 27 Jul 2017 09:42:05 +0000 (11:42 +0200)]
Improve SVA tests, add Makefile and scripts

7 years agoImprove Verific SVA import: negedge and $past
Clifford Wolf [Thu, 27 Jul 2017 09:40:07 +0000 (11:40 +0200)]
Improve Verific SVA import: negedge and $past

7 years agoImprove Verific SVA importer
Clifford Wolf [Thu, 27 Jul 2017 08:39:39 +0000 (10:39 +0200)]
Improve Verific SVA importer

7 years agoAdd "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
Clifford Wolf [Wed, 26 Jul 2017 16:28:55 +0000 (18:28 +0200)]
Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators

7 years agoImprove Verific bindings (mostly related to SVA)
Clifford Wolf [Wed, 26 Jul 2017 16:00:01 +0000 (18:00 +0200)]
Improve Verific bindings (mostly related to SVA)

7 years agoImprove "help verific" message
Clifford Wolf [Tue, 25 Jul 2017 13:13:22 +0000 (15:13 +0200)]
Improve "help verific" message

7 years agoAdd "verific -extnets"
Clifford Wolf [Tue, 25 Jul 2017 12:53:11 +0000 (14:53 +0200)]
Add "verific -extnets"

7 years agoAdd "using std::get" to yosys.h
Clifford Wolf [Tue, 25 Jul 2017 12:52:34 +0000 (14:52 +0200)]
Add "using std::get" to yosys.h

7 years agoImprove "verific -all" handling
Clifford Wolf [Tue, 25 Jul 2017 11:33:25 +0000 (13:33 +0200)]
Improve "verific -all" handling

7 years agoAdd "verific -import -d <dump_file"
Clifford Wolf [Mon, 24 Jul 2017 11:57:16 +0000 (13:57 +0200)]
Add "verific -import -d <dump_file"

7 years agoAdd "verific -import -flatten" and "verific -import -v"
Clifford Wolf [Mon, 24 Jul 2017 09:29:06 +0000 (11:29 +0200)]
Add "verific -import -flatten" and "verific -import -v"

7 years agoAdd more SVA test cases for future Verific work
Clifford Wolf [Sat, 22 Jul 2017 14:35:46 +0000 (16:35 +0200)]
Add more SVA test cases for future Verific work

7 years agoAdd "verific -import -k"
Clifford Wolf [Sat, 22 Jul 2017 14:16:44 +0000 (16:16 +0200)]
Add "verific -import -k"

7 years agoAdd error for cell output ports that are connected to constants
Clifford Wolf [Sat, 22 Jul 2017 13:08:30 +0000 (15:08 +0200)]
Add error for cell output ports that are connected to constants

7 years agoAdd some simple SVA test cases for future Verific work
Clifford Wolf [Sat, 22 Jul 2017 10:31:08 +0000 (12:31 +0200)]
Add some simple SVA test cases for future Verific work

7 years agoImprove docs for verific bindings, add simply sby example
Clifford Wolf [Sat, 22 Jul 2017 09:58:51 +0000 (11:58 +0200)]
Improve docs for verific bindings, add simply sby example

7 years agoFix handling of empty cell port assignments (i.e. ignore them)
Clifford Wolf [Fri, 21 Jul 2017 17:32:31 +0000 (19:32 +0200)]
Fix handling of empty cell port assignments (i.e. ignore them)

7 years agoFix "read_blif -wideports" handling of cells with wide ports
Clifford Wolf [Fri, 21 Jul 2017 14:21:04 +0000 (16:21 +0200)]
Fix "read_blif -wideports" handling of cells with wide ports

7 years agoAdd a paragraph about pre-defined macros to read_verilog help message
Clifford Wolf [Fri, 21 Jul 2017 12:34:53 +0000 (14:34 +0200)]
Add a paragraph about pre-defined macros to read_verilog help message

7 years agoAdd verilator support to testbenches generated by yosys-smtbmc
Clifford Wolf [Fri, 21 Jul 2017 12:33:29 +0000 (14:33 +0200)]
Add verilator support to testbenches generated by yosys-smtbmc