Rhys Perry [Fri, 22 May 2020 14:42:12 +0000 (15:42 +0100)]
aco: fix interaction with 3f branch workaround and p_constaddr
The offset was incorrect if we inserted a nop before the p_constaddr.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>
Michel Dänzer [Tue, 26 May 2020 09:04:19 +0000 (11:04 +0200)]
gitlab-ci: Pull in GCC 9 from Debian testing in x86_test-gl/vk images
The GCC 8 packages from buster are no longer compatible with libc6 from
testing. We could use the GCC 8 packages from testing instead, but this
is easier.
v2:
* Update piglit-quick_gl test results, due to the piglit issue fixed by
https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/294
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>
Michel Dänzer [Sat, 16 May 2020 15:17:23 +0000 (17:17 +0200)]
gitlab-ci: x86_test-base image as common base for x86_test-gl/vk
Making use of the relatively recent FDO_BASE_IMAGE feature of the
templates, the x86_test-base image contents are shared as a separate
layer by the x86_test-gl/vk images (meaning the former only needs to be
downloaded once for either or both of the latter). This should be more
efficient in terms of overall network bandwidth and storage, in
particular if the base image changes less often than the -gl/vk ones.
v2:
* List x86_test-base in needs: along with x86_test-gl/vk (see parent
commit)
* Always put $STABLE/TESTING_EPHEMERAL on separate lines, will make it
easier to add any non-ephemeral packages
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>
Michel Dänzer [Sat, 16 May 2020 10:07:42 +0000 (12:07 +0200)]
gitlab-ci: Also list arm/x86_build in needs: of test jobs
Without this, the test jobs may spuriously run if the arm/x86_build
jobs fail.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>
Caio Marcelo de Oliveira Filho [Wed, 27 May 2020 15:05:41 +0000 (08:05 -0700)]
intel: Add helper to calculate GPGPU_WALKER::RightExecutionMask
Suggested by Jason.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 06:32:18 +0000 (23:32 -0700)]
iris, i965: Update limits for ARB_compute_variable_group_size
The CS compiler now produces multiple SIMD variants, so the previous
trade-off between "always using SIMD32" and "having a smaller max
invocations" is now gone.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 06:55:23 +0000 (23:55 -0700)]
iris, i965: Drop max_variable_local_size
This was used to decide which SIMD width to generate code for
ARB_compute_variable_group_size. Now that compiler will generate
multiple SIMD widths, this information is unused.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 08:56:54 +0000 (01:56 -0700)]
intel/fs: Generate multiple CS SIMD variants for variable group size
This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch. The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().
The cs_prog_data::simd_size field was removed. The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.
When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:17:27 +0000 (00:17 -0700)]
anv: Use new helper functions to pick SIMD variant for CS
Also combine the existing individual anv helpers into a single one for
all CS related parameters.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:09:19 +0000 (00:09 -0700)]
iris: Use new helper functions to pick SIMD variant for CS
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 09:34:52 +0000 (02:34 -0700)]
iris: Set CS KernelStatePointer at dispatch
There's an update for INTERFACE_DESCRIPTOR_DATA at dispatch, so we can
just move the KSP assignment there. This flexibility will later allow
variable group size to pick the right SIMD variant.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:51:44 +0000 (00:51 -0700)]
i965: Use new helper functions to pick SIMD variant for CS
Also expand the existing i965 helper to return the other CS related
paramters.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 09:26:21 +0000 (02:26 -0700)]
intel/fs: Add helper to get prog_offset and simd_size
This indirection will be used by the variable group size case in a
later change.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 17:08:12 +0000 (10:08 -0700)]
intel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders
The "no32" flag will have precedence over "do32", like is done for FS.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 21:37:44 +0000 (14:37 -0700)]
intel/fs: Remove min_dispatch_width spilling decision from RA
Move the decision one level up, let brw_compile_*() functions use the
spilling information to decide whether or not a certain width
compilation can spill (passed via run_*() functions).
The min_dispatch_width was used to compare with the dispatch_width and
decide whether "a previous shader is already available, so don't
accept spill".
This is replaced by:
- Not calling run_*() functions if it is know beforehand a smaller width
already spilled -- since the larger width will spill and fail;
- Explicitly passing whether or not a shader is allowed to spill. For
the cases where the smaller width is available and haven't spilled,
the larger width will be compiled but is only useful if it won't
spill.
Moving the decision to this level will be useful later for variable
group size, which is a case where we want all the widths to be allowed
to spill.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Eric Engestrom [Wed, 27 May 2020 20:27:17 +0000 (22:27 +0200)]
docs: update calendar, add news item, and link releases notes for 20.1.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>
Eric Engestrom [Wed, 27 May 2020 21:46:48 +0000 (23:46 +0200)]
docs: Add release notes for 20.1.0
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>
Mike Blumenkrantz [Wed, 27 May 2020 19:28:42 +0000 (15:28 -0400)]
zink: always use logical eq ops in ntv with 1bit inputs
integer and float compare ops cannot take boolean types, so the bit size
of the inputs should be checked here so that we can swap to the logical
equality functions if we're being passed a bool value
resolves tons of validator errors in glsl piglit tests
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5231>
Vinson Lee [Wed, 27 May 2020 00:26:47 +0000 (17:26 -0700)]
pan/bi: Initialize struct fma_op_info member extended.
Fix warning reported by Coverity Scan.
Uninitialized scalar variable (UNINIT)
uninit_use: Using uninitialized value info. Field info.extended is
uninitialized.
Fixes: 8c79c710d4e1 ("pan/bi: Identify extended FMA opcodes")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5224>
Erico Nunes [Sun, 17 May 2020 13:56:42 +0000 (15:56 +0200)]
lima/ppir: use a ready list in node_to_instr
After the recent optimizations in ppir lowering that increase options
for combining, node_to_instr now may have multiple options of nodes to
insert and needs to decide which is better.
For example, if an instruction uses both a varying and a texture, there
are two nodes nodes that can be inserted to the load varying slot in the
same instruction (ld_var and ld_coords). It is much more advantageous to
pipeline the load texture coords since that enables the higher precision
path for texture coordinates. However, with the current recursive
expansion, this cannot be influenced.
This simple ready list implementation in node_to_instr allows it to
choose the next node to expand based on a priority score, rather than
relying on the random order coming from the recursive expansion.
Other than preferring nodes with pipeline output (which covers ld_coords
vs ld_var), nodes using later slots in the pipeline are now expanded
first, allowing node_to_instr to make all of the earlier (pipelineable)
nodes available in the ready list so the best one can be chosen when
picking nodes for the earlier slots.
Fixes: 632a921bd0d lima/ppir: optimize tex loads with single successor
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5092>
Alyssa Rosenzweig [Wed, 27 May 2020 18:53:05 +0000 (14:53 -0400)]
pan/bi: Suppress inf/nan for now
This is a (hopefully temporary) hack. The blob does it for ES2 at any
rate.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 16:32:28 +0000 (12:32 -0400)]
pan/bi: Add CSEL.16 packing tests
Passing but let's increase coverage.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:52:57 +0000 (11:52 -0400)]
pan/bi: Pack compact vertex texturing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:43:37 +0000 (11:43 -0400)]
pan/bi: Add f16 TEXC.vtx op
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:41:42 +0000 (11:41 -0400)]
pan/bi: Allow vertex txl with lod=0 as compact
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:33:26 +0000 (11:33 -0400)]
pan/bi: Document compute_lod bit for compact tex
At least I assume this works this way.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:28:11 +0000 (11:28 -0400)]
pan/bi: Also add compact vertex texturing
This implies lod=0.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 15:24:49 +0000 (11:24 -0400)]
pan/bi: Add TEX.vtx opcode for vertex texturing
Always has an LOD.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 20:38:47 +0000 (16:38 -0400)]
pan/decode: Decode Bifrost shader flags
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 23:48:25 +0000 (19:48 -0400)]
panfrost: Set MALI_BIFROST_EARLY_Z as necessary
Fixes blending.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 20:29:01 +0000 (16:29 -0400)]
panfrost: Identify MALI_BIFROST_EARLY_Z flag
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 20:26:29 +0000 (16:26 -0400)]
panfrost: Add defines for bifrost unk1 flags
Instead of open-coding.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 20:07:00 +0000 (16:07 -0400)]
panfrost: Document Midgard Inf/NaN suppress bit
We should probably not be setting this..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Wed, 27 May 2020 14:58:17 +0000 (10:58 -0400)]
panfrost: Ensure nonlinear strides are 16-aligned
To match how they are encoded.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: bde19c0e7ba ("panfrost: Fix tiled texture "stride"s on Bifrost")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 23:48:29 +0000 (19:48 -0400)]
panfrost: Identify Bifrost texture format swizzle
We don't force w=1 for Bifrost textures. We already compose this into
the swizzle as necessary, so we can just ignore this field I think. But
let's identify it so we don't forget what it is.
The blob uses it to force w=1 for <= 3-channel formats (0x10), as well
as a flag to swap r/b for BGRA (0x4). There are probably other flags
here but it doesn't.. really matter to us.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:50:29 +0000 (18:50 -0400)]
panfrost: Set unk2 to accomodate blending
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:48:04 +0000 (18:48 -0400)]
panfrost: Share MRT blend flag calculation with Bifrost
As far as I know the field is the same.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:21:57 +0000 (18:21 -0400)]
panfrost: Force Z/S tiling on Bifrost
Like we do on SFBD since we don't know the format bits yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:20:56 +0000 (18:20 -0400)]
panfrost: Tweak Bifrost colour buffer magic
For tiled or linear.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:19:19 +0000 (18:19 -0400)]
panfrost: Tweak zsbuf magic numbers for Bifrost
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Tue, 26 May 2020 22:16:51 +0000 (18:16 -0400)]
panfrost: Adjust null_rt for Bifrost
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
Alyssa Rosenzweig [Mon, 4 May 2020 16:48:50 +0000 (12:48 -0400)]
panfrost: Fix Bifrost blending with depth-only FBO
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>
James Zhu [Tue, 26 May 2020 13:28:41 +0000 (09:28 -0400)]
ac/gpu_info: Correct Acturus cu bitmap
The cu bitmap in amd gpu info structure is
4x4 size array, and it's usually suitable for Vega
ASICs which has 4*2 SE/SH layout.
But for Arcturus, SE/SH layout is changed to 8*1.
To mostly reduce the impact, we make it compatible
with current bitmap array as below:
SE4,SH0 --> cu_bitmap[0][1]
SE5,SH0 --> cu_bitmap[1][1]
SE6,SH0 --> cu_bitmap[2][1]
SE7,SH0 --> cu_bitmap[3][1]
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5212>
Danylo Piliaiev [Thu, 14 May 2020 12:29:36 +0000 (15:29 +0300)]
intel/fs: Work around dual-source blending hangs in combination with SIMD16
It was found that dual-source blending hangs with SIMD16 dispatch in some
specific but unknown situation. Which in the wild happen when rgba
anti-aliasing is enabled for fonts.
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5037>
Erik Faye-Lund [Mon, 25 May 2020 10:06:04 +0000 (12:06 +0200)]
zink: use general-layout when blitting to/from same resource
This avoids a validator warning when for instance generating mipmaps.
Fixes: d2bb63c8d4c ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5199>
Pierre-Eric Pelloux-Prayer [Fri, 22 May 2020 16:38:24 +0000 (18:38 +0200)]
radeonsi/drirc: enable zerovram option for 7 Days to Die
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2686
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5168>
Jonathan Marek [Tue, 12 May 2020 23:51:29 +0000 (19:51 -0400)]
turnip: support VkImageDrmFormatModifierExplicitCreateInfoEXT
This will be used to import images which have different layout from what
turnip uses by default. For example non-UBWC (linear) images from the video
decoder on some hardware have a 512 pitch alignment.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>
Jonathan Marek [Tue, 12 May 2020 23:38:48 +0000 (19:38 -0400)]
freedreno/layout: add explicit offset/pitch argument to fdl6_layout
fdl6_layout will return false when the explicit pitch is not valid.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>
Timothy Arceri [Thu, 21 May 2020 03:12:34 +0000 (13:12 +1000)]
glsl: fix slow linking of uniforms in the nir linker
Currently the nir linker resizes the amount of storage needed to hold
uniform information on the fly while linking. As shaders can contain
thousands of uniforms this can be very slow. For example some Godot
shaders can take 30 seconds to compile on some machines.
In this change we count the amount of storage needed before we start
processing the uniforms. This is what the GLSL IR linker does also.
Fixes: 95f555a93a88 ("st/glsl_to_nir: make use of nir linker for linking uniforms")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2996
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5137>
Timothy Arceri [Tue, 26 May 2020 02:14:13 +0000 (12:14 +1000)]
glsl: stop cascading errors if process_parameters() fails
Generally we do not completely stop compilation as soon as we see an error,
instead we continue on to attemp to find any futher errors.
This means we shouldn't be checking state->error to see if any error has
happened during the compilation process, doing so was causing
process_parameters() to fail on completely valid functions if there was
any error found in the shader previously. This then caused the valid
functions not to be found because the paramlist was considered empty,
resulting in the compiler spewing out misleading error messages.
Here we simply add the IR error value to the param list when we have
an issue with processing a parameter, this leads to much better error
messaging.
Fixes: 53e4159eaaf6 ("glsl: stop processing function parameters if error happened")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5205>
Vinson Lee [Tue, 26 May 2020 23:09:03 +0000 (16:09 -0700)]
freedreno: Add missing va_end.
Fix warning reported by Coverity Scan.
Missing varargs init or cleanup (VARARGS)
missing_va_end: va_end was not called for ap.
Fixes: a0ca1462f317 ("freedreno: add logging infrastructure")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5221>
Jason Ekstrand [Tue, 26 May 2020 20:58:56 +0000 (15:58 -0500)]
nir: Fix sources for image atomic fadd
Somehow we ended up with an extra scalar source up-front. It doesn't
look like any drivers use this opcode yet so no real harm has been done
by it being wrong.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5218>
Alyssa Rosenzweig [Fri, 22 May 2020 18:56:49 +0000 (14:56 -0400)]
pan/decode: Dump unknown2
Looks to be 0.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>
Alyssa Rosenzweig [Fri, 22 May 2020 18:53:27 +0000 (14:53 -0400)]
pan/decode: Dump missing field on Bifrost
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>
Alyssa Rosenzweig [Tue, 26 May 2020 22:10:39 +0000 (18:10 -0400)]
pan/decode: Fix tiler warning
../src/panfrost/pandecode/decode.c:1176:60: warning: taking address of
packed member of ‘struct mali_framebuffer’ may result in an unaligned
pointer value [-Waddress-of-packed-member]
1176 |
pandecode_midgard_tiler_descriptor(&fb->tiler, fb->width1 + 1,
fb->height1 + 1, is_fragment, true);
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>
Alyssa Rosenzweig [Tue, 26 May 2020 22:03:26 +0000 (18:03 -0400)]
pan/decode: Fix unused variable warning
Check unused for now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>
Alyssa Rosenzweig [Tue, 19 May 2020 15:14:21 +0000 (11:14 -0400)]
nouveau: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:11:07 +0000 (11:11 -0400)]
etnaviv: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:11:17 +0000 (11:11 -0400)]
iris: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:11:41 +0000 (11:11 -0400)]
i965: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:09:41 +0000 (11:09 -0400)]
intel: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:11:25 +0000 (11:11 -0400)]
softpipe: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:02:09 +0000 (11:02 -0400)]
panfrost: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:14:12 +0000 (11:14 -0400)]
glsl: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:10:56 +0000 (11:10 -0400)]
gallium/draw: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:09:02 +0000 (11:09 -0400)]
mesa/swrast: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:08:51 +0000 (11:08 -0400)]
mesa: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Tue, 19 May 2020 15:14:52 +0000 (11:14 -0400)]
util/format: Use SATURATE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Alyssa Rosenzweig [Thu, 14 May 2020 16:34:35 +0000 (12:34 -0400)]
util: Add SATURATE macro
Equivalent to clamp(x, 0.0, 1.0) or fsat in NIR. Useful for format
packing, among other uses given the variety of substituions in-tree.
v2: Drop brackets (Eric).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 21:30:01 +0000 (14:30 -0700)]
intel/fs: Remove redundant assert()
This is covered by the two previous similar asserts. Each time `v` is
assigned this is asserted.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 16:44:55 +0000 (09:44 -0700)]
intel/fs: Early return when can't satisfy explicit group size
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>
Caio Marcelo de Oliveira Filho [Wed, 20 May 2020 09:37:49 +0000 (02:37 -0700)]
intel/fs: Remove unused state from brw_nir_lower_cs_intrinsics
After
2663759af0e ("intel/fs: Add and use a new load_simd_width_intel
intrinsic") the local_workgroup_size is not used anymore except for
assertions at the pass' start, so drop it from state struct.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 08:03:57 +0000 (01:03 -0700)]
intel/fs: Remove unused emission of load_simd_with_intel
The nir_intrinsic_load_simd_width_intel is always lowered by the
brw_nir_lower_simd() pass before the emission happens. This is likely
a "leftover" from patch rewriting/squashing that happened when this
intrinsic was added.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>
Kristian H. Kristensen [Fri, 22 May 2020 21:56:08 +0000 (14:56 -0700)]
egl/android: Drop unused variable
src/egl/drivers/dri2/platform_android.c:332:29: warning: unused
variable 'dri2_dpy' [-Wunused-variable]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:55:29 +0000 (14:55 -0700)]
egl/android: Move get_format under HAVE_DRM_GRALLOC guard where it's used
src/egl/drivers/dri2/platform_android.c:159:12: warning: unused
function 'get_format' [-Wunused-function]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:47:30 +0000 (14:47 -0700)]
mesa/st: Use memset to zero out struct
This is a non-stop source of warnings and build breakage. memset works
everywhere.
src/mesa/state_tracker/st_tgsi_lower_depth_clamp.c:354:45: warning:
suggest braces around initialization of subobject [-Wmissing-braces]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:37:38 +0000 (14:37 -0700)]
mapi: Fix a couple of warning in generated code
safe_mul may not be used and clang doesn't understand the "optimize"
attribute.
src/mapi/glapi/gen/marshal_generated0.c:1216:16: warning: unknown
attribute 'optimize' ignored [-Wunknown-attributes]
src/mapi/glapi/gen/marshal_generated0.c:36:19: warning: unused
function 'safe_mul' [-Wunused-function]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:33:17 +0000 (14:33 -0700)]
src/util: Remove out-of-range comparison
Silence the warning about this always-true comparison.
src/util/softfloat.c:214:42: warning: comparison of constant 32768
with expression of type 'int16_t' (aka 'short') is always false
[-Wtautological-constant-out-of-range-compare]
} else if ((e > 0x1d) || (0x8000 <= m)) {
~~~~~~ ^ ~
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:30:54 +0000 (14:30 -0700)]
freedreno/ir3: Avoid {0} initializer for struct reginfo
First element is not a scalar. Just initialize the struct like we do
elsewhere.
src/freedreno/ir3/disasm-a3xx.c:958:33: warning: suggest braces around
initialization of subobject [-Wmissing-braces]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 21:00:38 +0000 (14:00 -0700)]
turnip: Use {} initializer to silence warning
We're already using the {} syntax elsewhere in turnip.
src/freedreno/vulkan/tu_formats.c:828:71: warning: suggest braces
around initialization of subobject [-Wmissing-braces]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 20:57:53 +0000 (13:57 -0700)]
turnip: Use tu6_reduction_mode() to avoid warning
This makes it a little more explicit that the values line up.
src/freedreno/vulkan/tu_device.c:2209:75: warning: implicit conversion
from enumeration type 'const VkSamplerReductionMode' (aka 'const enum
VkSamplerReductionMode') to different enumeration type 'enum
a6xx_reduction_mode' [-Wenum-conversion]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Kristian H. Kristensen [Fri, 22 May 2020 20:56:13 +0000 (13:56 -0700)]
turnip: Use hw enum when emitting A6XX_RB_STENCIL_CONTROL
We're hard-coding this value, so let's use the hw enum and avoid a
warning.
src/freedreno/vulkan/tu_clear_blit.c:2091:19: warning: implicit
conversion from enumeration type 'enum VkStencilOp' to different
enumeration type 'enum adreno_stencil_op' [-Wenum-conversion]
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>
Rob Clark [Sat, 23 May 2020 19:42:00 +0000 (12:42 -0700)]
freedreno/gmem: split out helper to calc # of bins
Gets the `nbins_x`/`y` local vars out of the main layout function,
to prevent any confusion like what was fixed in the previous patch
from sneaking back in.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Sat, 23 May 2020 19:27:17 +0000 (12:27 -0700)]
freedreno/gmem: fix nbins_x/y mismatch
`layout_gmem()` recalculates the # of bins in x/y dimensions after
aligning the bin width/height to required dimensions. Because of this,
the resulting gmem config could have fewer bins in either dimension.
But the tile/bin layout and the pipe assignment logic were still using
the original values. Which could result in extraneous bins with a
width and/or height of zero.
Because the gmem rendering code uses `gmem->bin_w`/`h` to determine
the number of bins, this could result in some zero size bins being
executed, while later valid bins are skipped. Which can leave un-
rendered portions of the screen (generally lower-right).
To fix this, be sure to use `gmem->bin_w`/`h` rather than the local
variables.
Fixes: 1bd38746d5a ("freedreno/gmem: rework gmem layout algo")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Sat, 23 May 2020 19:21:20 +0000 (12:21 -0700)]
freedreno/gmem: add some asserts
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Sat, 23 May 2020 19:03:14 +0000 (12:03 -0700)]
freedreno/gmemtool: add verbose mode
And real getopt arg parsing.. now that we have one.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Sat, 23 May 2020 18:52:29 +0000 (11:52 -0700)]
freedreno/gmemtool: add a405
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Sat, 23 May 2020 18:50:14 +0000 (11:50 -0700)]
freedreno/gmemtool: make GMEM alignment per-gen
`gmem_page_align` is generation specific (with the exception of a2xx
which has a different value for fast-clear). So we should override the
value from the captured gmem_key according to the gpu we are emulating
for the purposes of calculating gmem config.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5189>
Rob Clark [Fri, 22 May 2020 19:28:38 +0000 (12:28 -0700)]
freedreno/gmem: make noscis debug actually do something on a6xx
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5188>
Rob Clark [Sat, 23 May 2020 17:56:56 +0000 (10:56 -0700)]
freedreno: handle PIPE_TRANSFER_MAP_DIRECTLY
Just something I noticed in the process of debugging the issue fixed in
the previous commit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5188>
Rob Clark [Sat, 23 May 2020 17:52:52 +0000 (10:52 -0700)]
freedreno: clear last_fence after resource tracking
The resource tracking in the clear/draw_vbo/blit paths could itself
trigger a flush. Which would update last_fence. So we need to clear
last_fence *after* all the dependency tracking.
Fixes: ddb7fadaf8b ("freedreno: avoid no-op flushes by re-using last-fence")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2992
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5188>
Rob Clark [Sat, 23 May 2020 18:00:40 +0000 (11:00 -0700)]
freedreno: add batch debugging
Something I cooked up in the process of debugging the issue fixed in the
next commit. Might come in useful again in the future.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5188>
Rhys Perry [Tue, 26 May 2020 17:08:17 +0000 (18:08 +0100)]
nir: fix lowering to scratch with boolean access
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 18ed82b084c79bf63666f2da22e5d675fb01aa26
('nir: Add a pass for selectively lowering variables to scratch space')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5214>
Kristian H. Kristensen [Fri, 22 May 2020 20:36:38 +0000 (13:36 -0700)]
freedreno: Use explicit *_NONE enum for undefined formats
This adds RB, VFMT and TFMT NONE values for a3xx-a5xx and FMT6_NONE
for a6xx. Use those values instead of open coded (enum xxx) ~0 or
sometimes even ~0, which triggers out-of-enum range warnings.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5173>
Eric Anholt [Tue, 21 Jan 2020 22:36:32 +0000 (14:36 -0800)]
freedreno/ir3: Use RESINFO for a6xx image size queries.
The closed GL driver uses resinfo on images with the writeonly flag (using
the texture-path's getsize only for readonly images). The closed vulkan
driver seems to use resinfo regardless. Using resinfo doesn't need any
fixups after the instruction. It also avoids one of the needs for the
TEX_CONST state for the image, which is awkward to set up in the GL
driver.
The new handler goes into ir3_a6xx to be next to the other current image
code, but the a4xx version is left in place because it wants a bunch of
sampler helpers.
Fixes assertion failure in dEQP-VK.image.image_size.buffer.readonly_32.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
Eric Anholt [Wed, 20 May 2020 21:00:33 +0000 (14:00 -0700)]
freedreno/ir3: Move handle_bindless_cat6 to compiler_nir and reuse.
There was an open coded version for ldc, and now we can drop that. I
needed to do it for resinfo as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
Eric Anholt [Wed, 20 May 2020 20:40:29 +0000 (13:40 -0700)]
freedreno/ir3: Refactor out IBO source references.
All the users of the unsigned result just wanted an ir3_instruction to
reference. Move a6xx's helpers to ir3_image.c and inline the old unsigned
results version.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
Eric Anholt [Wed, 20 May 2020 22:29:14 +0000 (15:29 -0700)]
freedreno: Set the immediate flag in a4/a5xx resinfos.
Noticed comparing our RESINFO asm to qcom's for the same test, and if I
drop this bit their disasm switches from immediate to reg. ldgb seems to
have the same behavior.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
Eric Anholt [Wed, 20 May 2020 20:25:32 +0000 (13:25 -0700)]
freedreno: Fix resinfo asm, which doesn't have srcs besides IBO number.
In the process, clarify what's going on with the LDC/LDIB case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
Eric Anholt [Wed, 20 May 2020 20:21:44 +0000 (13:21 -0700)]
freedreno: Add more resinfo/ldgb testcases.
Since I'm going to start using the resinfo opcode, make sure we can disasm
the blob's instances of it that I've found. And, since resinfo disasm
will impact ldgb on pre-a6xx, include some of those too.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3501>
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