Curtis Dunham [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: refactor page table walking
Introduce and use a lookup table.
Using fetchDescriptor() rather than DMA cleanly handles nested paging.
Change-Id: I69ec762f176bd752ba1040890e731826b58d15a6
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: warn not fail on use of missing miscreg CNTHCTL_EL2
During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this
miscreg has not been implemented, the simulation would end there. This
patch causes the simulation to warn about the read/write instead of fail.
Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Check TLB stage 2 permissions in AArch64
This fixes a bug where stage 2 lookups used the AArch32
permissions rules even if we were executing in AArch64 mode.
Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: correctly assign faulting IPA's to HPFAR_EL2
This patch corrects IPA reporting if the translation faults in a
stage 2 lookup.
Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Add TLBI instruction for stage 2 IPA's
This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.
Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Fix stage 2 memory attribute checking in AArch64
Change-Id: I14c93a5460550051a12129e792a9a9bd522a145c
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Fix trapping to Hypervisor during MSR/MRS read/write
This patch restricts trapping to hypervisor only if we are in the
correct exception level for the trap to happen.
Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix secure state checking in various places
Faults that could potentially be routed to the hypervisor checked
whether or not they were in a secure state without checking if security
was enabled or not. This caused faults not to be routed correctly. This
patch causes secure state checking to first ask if security is enabled.
Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix stage 2 determination in table walker
We recompute if we are doing a stage 2 walk inside of the table walker
but we have already figured it out in the tlb. Pass the information in
to the walk instead of recomputing it.
Change-Id: I39637ce99309b2ddbc30344d45ac9ebf6a203401
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Refactor aarch64 table walk logic to remove redundancy
The functional case is already handled within the fetchDescriptor()
function. We can thus use that function for both atomic and functional
mode when we start the table walk.
Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Add check to fault routing for hypervisor/virtualization
This patch adds the option for faults to be routed to the hypervisor
using the pre-existing routeToHyp() functions that are present in each
fault type.
Change-Id: I9735512c094457636b9870456a5be5432288e004
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix EL perceived at TLB for address translation instructions
During address translation instructions (such as AT S1E1R_Xt) the exception
level can be different than the current exception level. This patch fixes
how the TLB determines what EL to use during these instructions.
Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Add AArch64 hypervisor call instruction 'hvc'
This patch adds the AArch64 instruction hvc which raises an exception
from EL1 into EL2. The host OS uses this instruction to world switch
into the guest.
Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
Curtis Dunham [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
Dylan Johnson [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
Dylan Johnson [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: change instruction classes to catch hyp traps
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
Andreas Sandberg [Fri, 22 Jul 2016 14:24:20 +0000 (15:24 +0100)]
tests: Add regex-based ignore rules for ref files
There are cases where we need to ignore files with specific extensions
(e.g., when Mercurial litters the file system with patch
rejects). Implement this functionality using a helper class
(FileIgnoreList) that supports both regular expressions and basic
string comparisons.
Change-Id: I34549754bd2e10ed230ffb2dc057403349f8fa78
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Thu, 21 Jul 2016 16:19:18 +0000 (17:19 +0100)]
stats: update references
Gabor Dozsa [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
arm, config: Add an example ARM big.LITTLE(tm) configuration script
An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.
Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Mitch Hayenga [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
cpu: Fix Minor SMT WFI/drain interaction issues
The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI. This patch makes WFI drain. If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc. This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.
Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
Mitch Hayenga [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
cpu: Add SMT support to MinorCPU
This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.
Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
Mitch Hayenga [Thu, 21 Jul 2016 16:19:15 +0000 (17:19 +0100)]
isa: Modify get/check interrupt routines
Make it so that getInterrupt *always* returns an interrupt if
checkInterrupts() returns true. This fixes/simplifies handling
of interrupts on the SMT FS CPUs (currently minor).
David Guillen Fandos [Thu, 21 Jul 2016 16:19:15 +0000 (17:19 +0100)]
base: Add total() to Vector2D stat
This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.
David Guillen Fandos [Thu, 21 Jul 2016 16:19:14 +0000 (17:19 +0100)]
mem: Add snoop traffic statistic
Jakub Jermar [Tue, 19 Jul 2016 14:52:46 +0000 (09:52 -0500)]
config: Allow SPARC FS image to be specified on the command line
At the moment the SPARC FS machine configuration comes with a hardcoded
value for using the Solaris 10 disk image from the OpenSPARC tarball. The
--disk-image option is completely ignored for SPARC. This simple patch
modifies the behavior so that --disk-image option is both taken into
account and also required. This makes it possible to easily change SPARC FS
images without having to modify the configuration files.
Mohammad Alian [Tue, 19 Jul 2016 14:48:56 +0000 (09:48 -0500)]
dev, dist: Fixed a scheduling bug in the etherswitch
This patch fixes a bug in etherswitch. When a packet gets inserted
in the output fifo, the txEvent has to always be reschedule,
not only when an event is already scheduled. This can raise
the assertion in the reschedule function.
Andreas Sandberg [Mon, 11 Jul 2016 15:30:35 +0000 (16:30 +0100)]
base: Fix inverted check in ELF .text size warning
Andreas Sandberg [Mon, 11 Jul 2016 09:39:56 +0000 (10:39 +0100)]
arm: Don't consult the TLB test iface for functional translations
Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.
Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Mon, 11 Jul 2016 09:39:30 +0000 (10:39 +0100)]
base: Convert ELF .text size check assertion to a warning
The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.
Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Nikos Nikoleris [Mon, 11 Jul 2016 09:39:22 +0000 (10:39 +0100)]
mem: Remove stale argument from a DPRINTF in the cache code
Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Jason Lowe-Power [Fri, 1 Jul 2016 15:37:57 +0000 (10:37 -0500)]
misc: merge with sytle checker fix
Oops.
Matthew Poremba [Fri, 1 Jul 2016 15:31:37 +0000 (10:31 -0500)]
ruby: Fix double statistic registration in garnet
Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.
Committed by Jason Lowe-Power <jason@lowepower.com>
Matthias Jung [Fri, 1 Jul 2016 15:31:36 +0000 (10:31 -0500)]
ext: Update DRAMPower
Sync DRAMPower to external tool
This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.
The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07. May. 2016.
Committed by Jason Lowe-Power <jason@lowepower.com>
Matthias Jung [Fri, 1 Jul 2016 15:31:33 +0000 (10:31 -0500)]
misc: SystemC Elastic Trace Player Example.
This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.
Committed by Jason Lowe-Power <jason@lowepower.com>
Christian Menard [Fri, 1 Jul 2016 14:50:18 +0000 (09:50 -0500)]
misc: fix a compile error due to incompability with SystemC 2.3.1
This patch fixes an ambigous call compile error
Committed by Jason Lowe-Power <jason@lowepower.com>
Abdul Mutaal Ahmad [Fri, 1 Jul 2016 14:48:43 +0000 (09:48 -0500)]
mem: tester for new HMC configuration
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.
Committed by Jason Lowe-Power <jason@lowepower.com>
Abdul Mutaal Ahmad [Fri, 1 Jul 2016 14:45:21 +0000 (09:45 -0500)]
mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.
Highlights
1- It explores 3 different HMC architectures
2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This will connect vaults to serial links
3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports
4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink
Committed by Jason Lowe-Power <jason@lowepower.com>
Andreas Sandberg [Fri, 1 Jul 2016 14:35:52 +0000 (15:35 +0100)]
style: Fix incorrect references style verifiers
The style checker for spacing around control statements (ControlSpace)
and the whitespace checker (Whitespace) didn't refer to some of their
configuration variables correctly. This changeset fixes those issues.
Reported-by: Jason Lowe-Power <power.jg@gmail.com>
--HG--
extra : amend_source :
05d82d27d4c42aacd78b514d3ca35ca5744164bb
Abdul Mutaal Ahmad [Fri, 1 Jul 2016 14:30:15 +0000 (09:30 -0500)]
misc: Separate stats file for SystemC-gem5 co-simulation
In previous versions of systemC-gem5 coupling statistics were not updated
for the systemc-gem5 simulation. systemC-gem5 simulation only need the
previously built config.ini file and normal gem5 simulation has to be run
once to generate config.ini file. Thus stats.txt inside the m5out folder is
redundant for systemC-gem5 simulation. A new stats file is now generated
with the all the statistics for systemC-gem5 simulation. This will also
resolve the stats issue in tlm-sysmtemC simulation.
Committed by Jason Lowe-Power <jason@lowepower.com>
Andreas Hansson [Tue, 28 Jun 2016 07:50:00 +0000 (03:50 -0400)]
scons: Track swig packages when loading embedded swig code
This patch changes how the embedded swig code is loaded to ensure that
gem5 works with swig 3.0.9. For Python 2.7 and above, swig 3.0.9 now
relies on importlib, and actually looks in the appropriate packages,
even for the wrapped C code. However, the swig wrapper does not
explicitly place the module in the right package (it just calls
Py_InitModule), and we have to take explicit action to ensure that the
swig code can be loaded. This patch adds the information to the
generated wrappers and the appropriate calls to set the context as
part of the swig initialisation.
Previous versions of swig used to fall back on looking in the global
namespace for the wrappers (and still do for Python 2.6), but
technically things should not work without the functionality in this
patch.
Andreas Sandberg [Tue, 21 Jun 2016 15:42:04 +0000 (16:42 +0100)]
stats: Update stats to reflect ARM changes
Nikos Nikoleris [Mon, 20 Jun 2016 14:51:31 +0000 (15:51 +0100)]
arm: Mark uninitialized new TLB entries as not valid
Previously when we initialized the TLB we would allocate a number of
TLB entries which would be marked as valid. As a result the TLB
contained an entry which would be considered a valid entry for the 0
page.
Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reiley Jeapaul [Mon, 20 Jun 2016 14:34:41 +0000 (15:34 +0100)]
sim: Added library include to fix build errors on clang-703.0.31
The use of array tuples, requires an explicit include of the array library
Change-Id: I06730051777a97edf80e41a5604184b387b12239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Mon, 20 Jun 2016 14:11:18 +0000 (15:11 +0100)]
mem: Fix the snoop filter when there is a downstream addr mapper
The snoop filter handles requests in two steps which preceed and
follow the call to send the packet downstream. An address mapper could
possibly change the address of the packet when it is sent downstream
breaking the snoop filter assumption that the address is unchanged
Change-Id: Ib2db755e9ebef4f2f7c0169a46b1b11185ffbe79
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Mon, 20 Jun 2016 13:50:43 +0000 (14:50 +0100)]
tests: Add a test command to get test status as an exit code
Add a "test" command to tests.py that queries a test pickle file and
returns different exit codes depending on the outcome of the tests in
the file. The following exit codes can currently be returned:
* 0: All tests were successful or skipped.
* 1: General fault in the script such as incorrect parameters or
failing to parse a pickle file.
* 2: At least one test failed to run. This is what the summary
formatter usually shows as a 'FAILED'.
* 3: All tests ran correctly, but at least one failed to verify
its output. When displaying test output using the summary
formatter, such a test would show up as 'CHANGED'.
The command can be invoked like this:
./tests/tests.py test `find build/ARM/tests/opt/ -name status.pickle`
Change-Id: I7e6bc661516f38ff08dfda7c4359a1e10bf97864
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Mon, 20 Jun 2016 13:50:34 +0000 (14:50 +0100)]
tests: Split test results into running and verification
The test base class already assumes that test cases consists of a run
stage and a verification stage. Reflect this in the results class to
make it possible to detect cases where a run was successful, but
didn't verify.
Change-Id: I31ef393e496671221c5408aca41649cd8dda74ca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Gabor Dozsa [Mon, 20 Jun 2016 13:49:52 +0000 (14:49 +0100)]
style: catch trailing white spaces in make and dts files
Change-Id: I2a4f1893919660e51599902b972a6f3f5717e305
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Mon, 20 Jun 2016 13:49:37 +0000 (14:49 +0100)]
mem: Resolve TrafficGen trace relative to the config
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.
Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Hansson [Mon, 20 Jun 2016 13:39:49 +0000 (14:39 +0100)]
config: Fix omission of walker cache in config scripts
This patch ensures a walker cache is instantiated if specfied.
Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Andreas Sandberg [Mon, 20 Jun 2016 13:39:49 +0000 (14:39 +0100)]
kern, arm: Dump dmesg on kernel panic/oops
Add helper functions to dump the guest kernel's dmesg buffer to a text
file in m5out. This functionality is split into two parts. First, a
dmesg dump function that can be used in other places:
void Linux::dumpDmesg(ThreadContext *, std::ostream &)
This function is used to implement two PCEvents: DmesgDumpEvent and
KernelPanic event. The only difference between the two is that the
latter produces a gem5 panic instead of a warning in addition to
dumping the kernel log.
Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Andreas Sandberg [Mon, 20 Jun 2016 13:39:48 +0000 (14:39 +0100)]
base: Fix multiple names to one address bug in SymbolTable
The SymbolTable class currently assumes that at most one symbol can
point to a given address. If multiple symbols point to the same
address, only the first one gets added to the internal symbol table
since there is already a match in the address table.
This changeset converts the address table from a map into a multimap
to be able to handle cases where an address maps to multiple
symbols. Additionally, the insert method is changed to not fail if
there is a match in the address table.
Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Tuan Ta [Sat, 18 Jun 2016 17:02:13 +0000 (13:02 -0400)]
gpu-compute: Fixed a bug in decoding Atomic ST
There is a mismatch between DataType and SrcDataType in constructing
Atomic ST instruction. The mismatch causes atomic_store and
atomic_store_explicit function to store incorrect value in memory.
Steve Reinhardt [Mon, 13 Jun 2016 00:02:49 +0000 (20:02 -0400)]
stats: update EIO stats
jkalamat [Thu, 9 Jun 2016 15:24:55 +0000 (11:24 -0400)]
gpu-compute: parametrize Wavefront size
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.
Mohammad Alian [Wed, 8 Jun 2016 14:12:41 +0000 (09:12 -0500)]
dist, dev: Fixed the packet ordering in etherswitch
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations
Committed by Jason Lowe-Power <power.jg@gmail.com>
Andreas Hansson [Tue, 7 Jun 2016 13:27:49 +0000 (14:27 +0100)]
sim: Make clang happy
Once again appeasing clang.
Sergei Trofimov [Tue, 7 Jun 2016 13:27:35 +0000 (14:27 +0100)]
sim: added missing include to mathexpr.hh
mathexpr.hh uses std::function<> but was not including the appropriate
header, which resulted in an error
build/ARM/sim/mathexpr.hh:51:18: error: 'function' in namespace 'std'
does not name a template type
typedef std::function<double(std::string)> EvalCallback;
This commit adds the missing include.
Change-Id: I6c01d77d4354c6de838538f137a38f75f9866166
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Mon, 6 Jun 2016 16:16:44 +0000 (17:16 +0100)]
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Andreas Sandberg [Mon, 6 Jun 2016 16:16:44 +0000 (17:16 +0100)]
sim: Only print the power state transition warning once
A lot of objects seem to request no-op power transitions which
currently results in large amounts of warnings. These warnings are
benign and risk hiding more serious warnings. Make the warning a
warn_once to prevent console flooding.
Change-Id: I86c74b4224b167f14469250ef86ab69fde7a227e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
David Guillen Fandos [Mon, 6 Jun 2016 16:16:44 +0000 (17:16 +0100)]
pwr: Closing power and thermal feedback loop
This patch makes thermal models use the power figures
calculated by power models. Since there is a circular
dependency between power and thermal (and thermal was
pushed before) this patch closes that loop.
Change-Id: I8bd5acf6a5026fdbbcfac47e33d27397f24a6f7d
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
David Guillen Fandos [Mon, 6 Jun 2016 16:16:44 +0000 (17:16 +0100)]
sim: Adding support for power models
This patch adds some basic support for power models in gem5.
The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.
The model allows it to be extended to use other kinds of models.
Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
David Guillen Fandos [Mon, 6 Jun 2016 16:16:43 +0000 (17:16 +0100)]
pwr: Low-power idle power state for idle CPUs
Add functionality to the BaseCPU that will put the entire CPU
into a low-power idle state whenever all threads in it are idle.
Change-Id: I984d1656eb0a4863c87ceacd773d2d10de5cfd2b
Andreas Sandberg [Mon, 6 Jun 2016 16:16:43 +0000 (17:16 +0100)]
stats: Silence unused power stats
The power stats are currently very noisy even if no power model has
been loaded. Silence stats that are either zero or nan.
Change-Id: I7d0220c2fcf01131084a219228f140cfaddaf95b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
David Guillen Fandos [Mon, 6 Jun 2016 16:16:43 +0000 (17:16 +0100)]
pwr: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access
functions to check and update the power state. Default power state
is UNDEFINED, it is responsibility of the respective simulation
model to provide the startup state and any other logic for state
change. Add number of transition stat. Add distribution of time
spent in clock gated state. Add power state residency stat. Add
dump call back function to allow stats update of distribution
and residency stats.
Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
David Guillen Fandos [Mon, 6 Jun 2016 16:16:43 +0000 (17:16 +0100)]
stats: Fixing regStats function for some SimObjects
Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).
Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Stephan Diestelhorst [Mon, 6 Jun 2016 16:16:43 +0000 (17:16 +0100)]
sim: Call regStats of base-class as well
We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well. For now, these are
empty, but generic stats will be added there.
Patch originally provided by Akash Bagdia at ARM Ltd.
Steve Reinhardt [Mon, 6 Jun 2016 04:18:34 +0000 (00:18 -0400)]
stats: update EIO stats
Tuan Ta [Fri, 3 Jun 2016 20:20:08 +0000 (16:20 -0400)]
gpu-compute: Fixed a bug in global memory pipeline
Added a condition when inflightStores is incremented to prevent a deadlock
caused by many memory fence requests generated by a CU
Marco Elver [Fri, 3 Jun 2016 20:20:08 +0000 (16:20 -0400)]
ruby: Implement SwapReq support
This implements SwapReq for Ruby memory.
A SwapReq should be treated like a write, except that the response
packet contains the overwritten data.
Note that, in particular, the conditional checking for isStore/isLoad
needs to be reversed, as a SwapReq is both.
Andreas Sandberg [Thu, 2 Jun 2016 19:34:39 +0000 (20:34 +0100)]
stats: Update ref stats to match ARM TLB changes
Curtis Dunham [Thu, 2 Jun 2016 15:44:57 +0000 (16:44 +0100)]
arm: refactor page table format determination
In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64
memory translation must be used. This is essential for typical
AArch64/32 interworking use cases.
Andreas Sandberg [Thu, 2 Jun 2016 14:20:24 +0000 (15:20 +0100)]
tests: Remove working dir assumption in tgen tests
The traffic generator tests currently assume that they are run from
the root of the source directory. This sometimes breaks tests when
they are run using the new test framework.
Change-Id: I6538a7902694c5d2c980295e076ea1c09acc4291
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Thu, 2 Jun 2016 13:14:36 +0000 (14:14 +0100)]
stats: Update to match ARM ISA changes
Andreas Sandberg [Thu, 2 Jun 2016 12:41:26 +0000 (13:41 +0100)]
arm: Rewrite ERET to behave according to the ARMv8 ARM
The ERET instruction doesn't set PSTATE correctly in some cases
(particularly when returning to aarch32 code). Among other things,
this breaks EL0 thumb code when using a 64-bit kernel. This changeset
updates the ERET implementation to match the ARM ARM.
Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Andreas Sandberg [Thu, 2 Jun 2016 12:38:30 +0000 (13:38 +0100)]
arm: Correctly check FP/SIMD access permission in aarch32
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.
Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Curtis Dunham [Thu, 2 Jun 2016 09:50:52 +0000 (10:50 +0100)]
tests: add 'CHANGED' output to pickle viewer
Change-Id: I64c69fde8657c273adea69122877c5348a4f867a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 2 Jun 2016 09:48:45 +0000 (10:48 +0100)]
tests: Only run Ruby tests when testing Ruby targets
Limit the test configs to Ruby-only configs when testing a Ruby target
that isn't MI_example. This avoids re-running configs that has already
been tested by the generic (non-Ruby) ISA target. This behavior was
the expected behavior prior to switching to the new test framework.
Change-Id: I3f138dbf9c7071ce862d1073aaec57c59afbc921
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Gabor Dozsa [Thu, 2 Jun 2016 09:48:20 +0000 (10:48 +0100)]
style: remove extra newline from white space verifier fix method
Change-Id: I7bce7d1cb04efe20d31445eb67ea5ffd2a4a41f4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Thu, 2 Jun 2016 09:48:16 +0000 (10:48 +0100)]
style: respect per verifier ignores for git commit
Change-Id: Id00379bdb17594e627ee49c077fb75f499ea550e
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 2 Jun 2016 09:37:16 +0000 (10:37 +0100)]
style: Move the last bits of file_types.py to the style package
The commit that refactored the style checkers into a new Python
package (style: Refactor the style checker as a Python package)
accidentally left a fragment of file_types.py in the old location
(util/style.py). This was caused by a race between the commit that
moved the file and Nate's commit that added a copyright header to the
file.
This commit moves the last fragment (the copyright header) and removes
the old file.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
946f1f6fee034ae79bd50ea7dfc3299a60f070c0
Curtis Dunham [Tue, 31 May 2016 15:55:47 +0000 (16:55 +0100)]
stats: update and fix
e273e86a873d
Andreas Sandberg [Tue, 31 May 2016 11:14:40 +0000 (12:14 +0100)]
arm: Enable LPAE support by default
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's
enable it by default.
Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Andreas Sandberg [Tue, 31 May 2016 11:14:37 +0000 (12:14 +0100)]
arm: Correctly check translation mode (aarch64/aarch32)
According to the ARM ARM (see AArch32.TranslateAddress in the
pseudocode library), the TLB should be operating in aarch64 mode if
the EL0 is aarch32 and EL1 is aarch64. This is currently not the case
in gem5, which breaks 64/32 interprocessing. Update the check to match
the reference manual.
Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Tue, 31 May 2016 10:27:00 +0000 (11:27 +0100)]
scons: Use the new test framework from scons
Rewrite the SCons script responsible for launching tests to use the
new test framework. The biggest visible change after this changeset is
that SCons no longer produces a "status" file in test build
directories. Instead, it creates a status.pickle file. That file can
be inspected using the new tests.py script. Another visible change is
that timed out tests are now reported as failed rather than a using a
separate summary message.
Since the pickle file will remain in the build directory after running
tests, it's now possible to convert the test results into other
formats. For example:
./tests/tests.py show --format junit -o junit.xml \
`find build/ -name status.pickle`
To better facilitate running outside of scons, there is now a set of
targets that generate test listings that can be used by the test
script. There are currently three targets, quick.list, long.list, and
all.list. For example:
scons build/ARM/tests/opt/all.list
for F in `cat build/ARM/tests/opt/all.list`; do
./tests/tests.py run build/ARM/gem5.opt $F
done
Change-Id: I2c0f8ca0080d7af737362e198eda4cb3a72e6c36
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Tue, 31 May 2016 10:26:59 +0000 (11:26 +0100)]
tests: Fix incorrect stat.txt ignore when updating refs
ClassicTest was incorrectly ignoring stats.txt when updating reference
statistics. This was caused by ignore rules being applied too
aggressively when listing reference files. This changeset splits the
ignore rules into two different lists: 1) diff_ignore_files that lists
the files that shouldn't be diff:ed using the normal diff tool, and 2)
ref_ignore_files which lists files that should be ignored by the test
system.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Tue, 31 May 2016 10:07:18 +0000 (11:07 +0100)]
stats: update for snoop filter tweak
--HG--
extra : source :
2323557eb4f4866fa1ea1575a9f5969e0022adc1
Stephan Diestelhorst [Fri, 27 May 2016 16:05:58 +0000 (17:05 +0100)]
mem, config: Selective use of snoop filter
Disable the default snoop filter in the SystemXBar so that the
typical membus does not have a snoop filter by default. Instead,
add the snoop filter only when there are caches added to the system
(with the caches / l2cache options).
The underlying problem is that the snoop filter grows without
bounds (for now) if there are no caches to tell it that lines have
been evicted. This causes slow regression runs for all the atomic
regressions. This patch fixes this behaviour.
--HG--
extra : source :
f97c20511828209757440839ed48d741d02d428f
Andreas Hansson [Mon, 30 May 2016 06:10:48 +0000 (02:10 -0400)]
scons: Bump minimum gcc version to 4.8
After reaching consensus on the mailing list, this patch officially
makes gcc 4.8 the minimum.
A few checks in the SConstruct are cleaned up as a result. This patch
also adds "-fno-omit-frame-pointer" when using ASAN (which is part of
the gcc/clang recommended flags).
Ilias Vougioukas [Fri, 27 May 2016 15:55:01 +0000 (16:55 +0100)]
cpu: fix lastStopped unserialisation
MinorCPU fix for corrupt numCycles when resuming from a previous simulation.
---
src/cpu/minor/cpu.cc | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
Akash Bagdia [Fri, 27 May 2016 15:54:59 +0000 (16:54 +0100)]
power: Allow voltage to be configured via cmd line
---
src/python/m5/params.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Matteo Andreozzi [Fri, 27 May 2016 15:46:03 +0000 (16:46 +0100)]
scons: Enable override suggestions on gcc 5.0+
---
SConstruct | 4 ++++
1 file changed, 4 insertions(+)
Andreas Sandberg [Fri, 27 May 2016 14:02:01 +0000 (15:02 +0100)]
arm: Use the target EL state when determining fault format
We currently check the current state instead of the state of the
target EL when determining how we report a fault. This breaks
interprocessing since EL0 in aarch32 would report its fault status
using the aarch32 registers even if EL1 is in aarch64. Fix this to
report the fault using the format of the target EL.
Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Andreas Sandberg [Thu, 26 May 2016 16:38:15 +0000 (17:38 +0100)]
arm: Fix incorrect TLB permission check in aarch32
The TLB currently assumes that the pxn bit in an LPAE page descriptor
disables execution from unprivileged mode. However, according to the
architecture manual, this bit should disable execution from privileged
modes. Update the TLB implementation to reflect this behavior.
Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Thu, 26 May 2016 16:33:38 +0000 (17:33 +0100)]
arm: Make EL checks available in SE mode
A lot of code assumes that it is possible to test what the highest EL
is and if it is 64 bit. These calls currently don't work in SE mode
since they rely on an instance of an ArmSystem.
Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Fix memory leak in handling of deferred snoops
This patch fixes a memory leak where deferred snoop packets never got
deallocated. On the call to MSHR::handleSnoop these snoops were
treated as if a response will be sent, as the MSHR was
pendingModified. Consequently, a copy of the packet was created and
added to the MSHR targets. However, an preceeding target to the same
MSHR, originally from a CPU, was serviced before the snoop, and caused
the block to be invalidated. This happens for ReadExReq and
UpgradeReq.
Note that the original snoop will receive a response, just not from
the cache in question, but instead from the cache upstream that issued
the ReadExReq or UpgradeReq.
Change-Id: I4ac012fbc8a46cf693ca390fe9476105d444e6f4
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
dev, arm: Add a flag to enable/disable gem5 GIC extensions
Make it possible to disable gem5 gic extensions by setting the
gem5_extensions param to False from Python.
Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
cpu: Add a basic progress check to the TrafficGen
This patch adds a progress check to the TrafficGen so that it is
easier to detect deadlock scenarios where the generator gets stuck
waiting for a retry, and makes no further progress.
Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Do not set cacheResponding on MSHR snoop if not responding
This patch changes the flow control for HSHR::handleSnoop to ensure
that we only set cacheResponding on the snoop packet if we are
actually responding. This avoids situations where a responder is
stalling indefinitely on a response that never arrives.
Change-Id: I691dd01755b614b30203581aa74fc743b350eacc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Fix MemChecker unique_ptr type mismatch
This patch fixes the type of the unique_ptr instances, to ensure that
the data that is allocated with new[] is also deleted with
delete[]. The issue was highlighted by ASAN.
Change-Id: I2c5510424959d862a9954d83e728d901bb18d309
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>