bugzilla-daemon [Thu, 21 May 2020 18:23:04 +0000 (18:23 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
Cole Poirier [Thu, 21 May 2020 18:01:32 +0000 (11:01 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 21may2020
bugzilla-daemon [Thu, 21 May 2020 17:55:55 +0000 (17:55 +0000)]
[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon [Thu, 21 May 2020 17:50:25 +0000 (17:50 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 17:48:16 +0000 (17:48 +0000)]
[libre-riscv-dev] [Bug 328] move decoder RB exts function into nmutil
bugzilla-daemon [Thu, 21 May 2020 17:46:02 +0000 (17:46 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 17:39:24 +0000 (17:39 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 17:32:37 +0000 (17:32 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 17:23:27 +0000 (17:23 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 16:48:51 +0000 (16:48 +0000)]
[libre-riscv-dev] [Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type
bugzilla-daemon [Thu, 21 May 2020 16:36:19 +0000 (16:36 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Thu, 21 May 2020 16:35:52 +0000 (16:35 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Thu, 21 May 2020 16:24:42 +0000 (16:24 +0000)]
[libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero
bugzilla-daemon [Thu, 21 May 2020 16:02:24 +0000 (16:02 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Luke Kenneth Casson Leighton [Thu, 21 May 2020 15:35:58 +0000 (16:35 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 21may2020
Michael Nolan [Thu, 21 May 2020 13:52:06 +0000 (09:52 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 21may2020
Luke Kenneth Casson Leighton [Thu, 21 May 2020 13:42:45 +0000 (14:42 +0100)]
[libre-riscv-dev] daily kan-ban update 21may2020
bugzilla-daemon [Thu, 21 May 2020 13:05:59 +0000 (13:05 +0000)]
[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA
bugzilla-daemon [Thu, 21 May 2020 13:05:46 +0000 (13:05 +0000)]
[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Thu, 21 May 2020 13:04:53 +0000 (13:04 +0000)]
[libre-riscv-dev] [Bug 335] New: Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Thu, 21 May 2020 13:02:18 +0000 (13:02 +0000)]
[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA
bugzilla-daemon [Thu, 21 May 2020 13:01:53 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Thu, 21 May 2020 13:01:46 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Thu, 21 May 2020 13:01:35 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Thu, 21 May 2020 13:01:27 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Thu, 21 May 2020 12:58:12 +0000 (12:58 +0000)]
[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon [Thu, 21 May 2020 12:05:32 +0000 (12:05 +0000)]
[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon [Thu, 21 May 2020 10:31:40 +0000 (10:31 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 21 May 2020 02:05:38 +0000 (02:05 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Thu, 21 May 2020 01:57:16 +0000 (01:57 +0000)]
[libre-riscv-dev] [Bug 334] New: POWER decode A=zero needs to be set as a flag in Execute1Type
bugzilla-daemon [Thu, 21 May 2020 00:57:26 +0000 (00:57 +0000)]
[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline
bugzilla-daemon [Thu, 21 May 2020 00:25:10 +0000 (00:25 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Thu, 21 May 2020 00:19:36 +0000 (00:19 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 22:20:28 +0000 (22:20 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 22:18:49 +0000 (22:18 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 22:14:26 +0000 (22:14 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Wed, 20 May 2020 19:53:39 +0000 (19:53 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 19:28:39 +0000 (19:28 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 20 May 2020 19:46:21 +0000 (19:46 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Luke Kenneth Casson Leighton [Wed, 20 May 2020 19:44:03 +0000 (20:44 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 19:42:50 +0000 (19:42 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 19:42:27 +0000 (19:42 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 19:39:19 +0000 (19:39 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Cole Poirier [Wed, 20 May 2020 19:34:26 +0000 (12:34 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 19:28:39 +0000 (19:28 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 19:27:55 +0000 (19:27 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Wed, 20 May 2020 19:27:37 +0000 (19:27 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 19:27:30 +0000 (19:27 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 19:27:15 +0000 (19:27 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 19:26:45 +0000 (19:26 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
Luke Kenneth Casson Leighton [Wed, 20 May 2020 19:17:27 +0000 (20:17 +0100)]
Re: [libre-riscv-dev] monorepo
Luke Kenneth Casson Leighton [Wed, 20 May 2020 19:08:52 +0000 (20:08 +0100)]
Re: [libre-riscv-dev] monorepo
bugzilla-daemon [Wed, 20 May 2020 18:59:40 +0000 (18:59 +0000)]
[libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags
bugzilla-daemon [Wed, 20 May 2020 18:59:40 +0000 (18:59 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 18:59:26 +0000 (18:59 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 18:52:28 +0000 (18:52 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 18:46:33 +0000 (18:46 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 18:45:48 +0000 (18:45 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Jacob Lifshay [Wed, 20 May 2020 18:43:32 +0000 (11:43 -0700)]
[libre-riscv-dev] monorepo
bugzilla-daemon [Wed, 20 May 2020 18:37:56 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 18:16:31 +0000 (18:16 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 18:13:03 +0000 (18:13 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 18:07:50 +0000 (18:07 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 17:55:31 +0000 (17:55 +0000)]
[libre-riscv-dev] [Bug 333] New: investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Wed, 20 May 2020 17:49:48 +0000 (17:49 +0000)]
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
bugzilla-daemon [Wed, 20 May 2020 17:48:35 +0000 (17:48 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Wed, 20 May 2020 17:34:41 +0000 (17:34 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
Luke Kenneth Casson Leighton [Wed, 20 May 2020 17:22:11 +0000 (18:22 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Luke Kenneth Casson Leighton [Wed, 20 May 2020 17:05:59 +0000 (18:05 +0100)]
Re: [libre-riscv-dev] RISCV-V Extension
Staf Verhaegen [Wed, 20 May 2020 16:44:06 +0000 (18:44 +0200)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
bugzilla-daemon [Wed, 20 May 2020 16:35:30 +0000 (16:35 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 16:34:59 +0000 (16:34 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 20 May 2020 16:34:09 +0000 (16:34 +0000)]
[libre-riscv-dev] [Bug 332] New: Formal correctness proof needed for CR pipeline
Yehowshua [Wed, 20 May 2020 16:31:30 +0000 (12:31 -0400)]
[libre-riscv-dev] RISCV-V Extension
bugzilla-daemon [Wed, 20 May 2020 16:28:36 +0000 (16:28 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
Luke Kenneth Casson Leighton [Wed, 20 May 2020 16:23:45 +0000 (17:23 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 16:00:10 +0000 (16:00 +0000)]
[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline
bugzilla-daemon [Wed, 20 May 2020 15:59:57 +0000 (15:59 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
Michael Nolan [Wed, 20 May 2020 15:50:47 +0000 (11:50 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 15:22:59 +0000 (15:22 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Wed, 20 May 2020 15:21:34 +0000 (15:21 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Wed, 20 May 2020 15:21:15 +0000 (15:21 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Wed, 20 May 2020 15:20:58 +0000 (15:20 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Wed, 20 May 2020 15:20:43 +0000 (15:20 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Wed, 20 May 2020 15:20:43 +0000 (15:20 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Wed, 20 May 2020 15:20:37 +0000 (15:20 +0000)]
[libre-riscv-dev] [Bug 331] New: Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Wed, 20 May 2020 15:19:44 +0000 (15:19 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 20 May 2020 15:19:44 +0000 (15:19 +0000)]
[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline
bugzilla-daemon [Wed, 20 May 2020 15:19:34 +0000 (15:19 +0000)]
[libre-riscv-dev] [Bug 330] New: create POWER9 Logic Pipeline
Luke Kenneth Casson Leighton [Wed, 20 May 2020 15:14:39 +0000 (16:14 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
Cole Poirier [Wed, 20 May 2020 14:50:54 +0000 (07:50 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 14:40:05 +0000 (14:40 +0000)]
[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon [Wed, 20 May 2020 14:16:50 +0000 (14:16 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
Luke Kenneth Casson Leighton [Wed, 20 May 2020 14:14:11 +0000 (15:14 +0100)]
[libre-riscv-dev] daily kan-ban update 20may2020
bugzilla-daemon [Wed, 20 May 2020 14:01:33 +0000 (14:01 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 20 May 2020 12:20:46 +0000 (12:20 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Wed, 20 May 2020 12:41:38 +0000 (12:41 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Wed, 20 May 2020 12:34:24 +0000 (12:34 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Wed, 20 May 2020 12:33:51 +0000 (12:33 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Wed, 20 May 2020 12:33:22 +0000 (12:33 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
projects / libre-riscv-dev.git / log