Nilay Vaish [Thu, 6 Nov 2014 06:55:09 +0000 (00:55 -0600)]
ruby: dma sequencer: remove RubyPort as parent class
As of now DMASequencer inherits from the RubyPort class. But the code in
RubyPort class is heavily tailored for the CPU Sequencer. There are parts of
the code that are not required at all for the DMA sequencer. Moreover, the
next patch uses the dma sequencer for carrying out memory accesses for all the
io devices. Hence, it is better to have a leaner dma sequencer.
Ali Saidi [Mon, 3 Nov 2014 16:14:42 +0000 (10:14 -0600)]
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
Ali Saidi [Thu, 30 Oct 2014 05:04:12 +0000 (00:04 -0500)]
arm, tests: Forgot the system.terminal files for the new regressions.
Ali Saidi [Thu, 30 Oct 2014 04:50:15 +0000 (23:50 -0500)]
arm, tests: Add 64-bit ARM regression tests
Ali Saidi [Thu, 30 Oct 2014 04:22:26 +0000 (23:22 -0500)]
automated merge
Ali Saidi [Thu, 30 Oct 2014 04:18:29 +0000 (23:18 -0500)]
tests: Update regressions for the new kernels and various preceeding fixes.
Ali Saidi [Thu, 30 Oct 2014 04:18:27 +0000 (23:18 -0500)]
arm, tests: Update config files to more recent kernels and create 64-bit regressions.
This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.
In addition a set of 64-bit ARM regressions have been added to the regression system.
Mitch Hayenga [Thu, 30 Oct 2014 04:18:27 +0000 (23:18 -0500)]
cpu: Add writeback modeling for drain functionality
It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform a writeback. This
patch re-adds tracking of in-flight instructions to prevent
falsely signaling a drained event.
Mitch Hayenga [Thu, 30 Oct 2014 04:18:26 +0000 (23:18 -0500)]
cpu: Add drain check functionality to IEW
IEW did not check the instQueue and memDepUnit to ensure
they were drained. This caused issues when drainSanityCheck()
did check those structures after asserting IEW was drained.
Ali Saidi [Thu, 30 Oct 2014 04:18:26 +0000 (23:18 -0500)]
arm, mem: Fix drain bug and provide drain prints for more components.
Ali Saidi [Thu, 30 Oct 2014 04:18:26 +0000 (23:18 -0500)]
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
Ali Saidi [Thu, 30 Oct 2014 04:18:26 +0000 (23:18 -0500)]
arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the old scheme
that no-longer works. This change unifies the code so there aren't any differences.
Ali Saidi [Thu, 30 Oct 2014 04:18:24 +0000 (23:18 -0500)]
arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
Ali Saidi [Thu, 30 Oct 2014 04:18:24 +0000 (23:18 -0500)]
cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
Andrew Bardsley [Thu, 30 Oct 2014 04:18:24 +0000 (23:18 -0500)]
cpu: Fix barrier push to store buffer when full bug in Minor
This patch fixes a bug where a completing load or store which is also a
barrier can push a barrier into the store buffer without first checking
that there is a free slot.
The bug was not fatal but would print a warning that the store buffer
was full when inserting.
Curtis Dunham [Tue, 21 Oct 2014 22:04:41 +0000 (17:04 -0500)]
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
WriteInvalidate semantics depend on the unconditional writeback
or they won't complete. Also, there's no point in deferring snoops
on their MSHRs, as they don't get new data at the end of their life
cycle the way other transactions do.
Add comment in the cache about a minor inefficiency re: WriteInvalidate.
Curtis Dunham [Thu, 30 Oct 2014 04:18:24 +0000 (23:18 -0500)]
mem: have WriteInvalidate obsolete MSHRs
Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed. This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
Steve Reinhardt [Tue, 2 Sep 2014 21:07:50 +0000 (16:07 -0500)]
syscall_emul: add retry flag to SyscallReturn
This hook allows blocking emulated system calls to indicate
that they would block, but return control to the simulator
so that the simulation does not hang. The actual retry
functionality requires additional support, to be provided
in a future changeset.
Steve Reinhardt [Wed, 22 Oct 2014 22:53:34 +0000 (15:53 -0700)]
syscall_emul: minor style fix to LiveProcess constructor
Steve Reinhardt [Wed, 22 Oct 2014 22:53:34 +0000 (15:53 -0700)]
syscall_emul: devirtualize BaseBufferArg methods
Not clear why they were marked virtual to begin with,
but that doesn't appear to be necessary.
Steve Reinhardt [Wed, 22 Oct 2014 22:53:34 +0000 (15:53 -0700)]
syscall_emul: Put BufferArg classes in a separate header.
Move the BufferArg classes that support syscall buffer args
(i.e., pointers into simulated user space) out of syscall_emul.hh
and into a new header syscall_emul_buf.hh so they are accessible
to emulated driver implementations.
Take the opportunity to add some comments as well.
Steve Reinhardt [Wed, 22 Oct 2014 22:53:34 +0000 (15:53 -0700)]
syscall_emul: add EmulatedDriver object
Fake SE-mode device drivers can now be added by
deriving from this abstract object.
Nilay Vaish [Wed, 22 Oct 2014 20:59:57 +0000 (15:59 -0500)]
sim: revert
6709bbcf564d
The identifier SYS_getdents is not available on Mac OS X. Therefore, its use
results in compilation failure. It seems there is no straight forward way to
implement the system call getdents using readdir() or similar C functions.
Hence the commit
6709bbcf564d is being rolled back.
Andreas Hansson [Mon, 20 Oct 2014 22:03:56 +0000 (18:03 -0400)]
x86: Fixes to avoid LTO warnings
This patch fixes a few minor issues that caused link-time warnings
when using LTO, mainly for x86. The most important change is how the
syscall array is created. Previously gcc and clang would complain that
the declaration and definition types did not match. The organisation
is now changed to match how it is done for ARM, moving the code that
was previously in syscalls.cc into process.cc, and having a class
variable pointing to the static array.
With these changes, there are no longer any warnings using gcc 4.6.3
with LTO.
Andreas Hansson [Mon, 20 Oct 2014 22:03:55 +0000 (18:03 -0400)]
misc: Use gmtime for conversion to UTC to avoid getenv/setenv
This patch changes how we turn time into UTC. Previously we
manipulated the TZ environment variable, but this has issues as the
strings that are manipulated could be tainted (see e.g. CERT
ENV34-C). Now we simply rely on the built-in gmtime function and avoid
touching getenv/setenv all together.
Omar Naji [Mon, 20 Oct 2014 22:03:55 +0000 (18:03 -0400)]
mem: Fix DRAM activationlLimit bug
Ensure that we do the proper event scheduling also when the activation
limit is disabled.
Andreas Hansson [Mon, 20 Oct 2014 22:03:54 +0000 (18:03 -0400)]
base: Fix for stats node on gcc < 4.6.3
This patch adds an explicit function to get the underlying node as gcc
4.6.1 and 4.6.2 have issues otherwise.
Andreas Hansson [Mon, 20 Oct 2014 22:03:53 +0000 (18:03 -0400)]
ext: Bump DRAMPower to avoid compilation issues
This patch bumps DRAMPower to commit
19433a6897ede4bbb19b06694faa8589b5a6569a which contains a small fix
for clang, and a work-around for LTO with gcc 4.6.
Omar Naji [Mon, 20 Oct 2014 22:03:52 +0000 (18:03 -0400)]
mem: Add DRAM device size and check against config
This patch adds the size of the DRAM device to the DRAM config. It
also compares the actual DRAM size (calculated using information from
the config) to the size defined in the system. If these two values do
not match gem5 will print a warning. In order to do correct DRAM
research the size of the memory defined in the system should match the
size of the DRAM in the config. The timing and current parameters
found in the DRAM configs are defined for a DRAM device with a
specific size and would differ for another device with a different
size.
Nilay Vaish [Mon, 20 Oct 2014 21:48:19 +0000 (16:48 -0500)]
stats: updates due to previous mmap and exit_group patches.
Nilay Vaish [Mon, 20 Oct 2014 21:47:55 +0000 (16:47 -0500)]
cpu: o3: corrects base FP and CC register index in removeThread()
Tom Jablin [Mon, 20 Oct 2014 21:45:25 +0000 (16:45 -0500)]
sim: invalid alignment checks in mmap and mremap
Presently, the alignment checks in the mmap and mremap implementations
in syscall_emul.hh are wrong. The checks are implemented as:
if ((start % TheISA::PageBytes) != 0 ||
(length % TheISA::PageBytes) != 0) {
warn("mmap failing: arguments not page-aligned: "
"start 0x%x length 0x%x",
start, length);
return -EINVAL;
}
This checks that both the start and the length arguments of the mmap
syscall are checked for page-alignment. However, the POSIX specification says:
The off argument is constrained to be aligned and sized according to the value
returned by sysconf() when passed _SC_PAGESIZE or _SC_PAGE_SIZE. When MAP_FIXED
is specified, the application shall ensure that the argument addr also meets
these constraints. The implementation performs mapping operations over whole
pages. Thus, while the argument len need not meet a size or alignment
constraint, the implementation shall include, in any mapping operation, any
partial page specified by the range [pa,pa+len).
So the length parameter should not be checked for page-alignment. By contrast,
the current implementation fails to check the offset argument, which must be
page aligned.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Michael Adler [Mon, 20 Oct 2014 21:45:08 +0000 (16:45 -0500)]
sim: mmap: correct behavior for fixed address
Change mmap fixed address request to return an error if the mapping is
impossible due to conflict instead of what I believe used to be silent
corruption.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Michael Adler [Mon, 20 Oct 2014 21:44:53 +0000 (16:44 -0500)]
sim: implement getdents/getdents64 in user mode
Has been tested only for alpha.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
x86: syscall: implementation of exit_group
On exit_group syscall, we used to exit the simulator. But now we will only
halt the execution of threads that belong to the group.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andreas Hansson [Thu, 16 Oct 2014 09:50:01 +0000 (05:50 -0400)]
mem: Modernise PhysicalMemory with C++11 features
Bring the PhysicalMemory up-to-date by making use of range-based for
loops and vector intialisation where possible.
Andreas Hansson [Thu, 16 Oct 2014 09:49:59 +0000 (05:49 -0400)]
misc: Move AddrRangeList from port.hh to addr_range.hh
The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.
Andreas Sandberg [Thu, 16 Oct 2014 09:49:58 +0000 (05:49 -0400)]
ext: Update fputils to rev
6a47fd8358
This patch updates fputils to the latest revision (
6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
Geoffrey Blake [Thu, 16 Oct 2014 09:49:57 +0000 (05:49 -0400)]
dev: refactor pci config space for sysfs scanning
Sysfs on ubuntu scrapes the entire PCI config space
when it discovers a device using 4 byte accesses.
This was not supported by our devices, in particular the NIC
that implemented the extended PCI config space. This change
allows the extended PCI config space to be accessed by
sysfs properly.
Andrew Bardsley [Thu, 16 Oct 2014 09:49:56 +0000 (05:49 -0400)]
mem: Add ExternalMaster and ExternalSlave ports
This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
Andrew Bardsley [Thu, 16 Oct 2014 09:49:54 +0000 (05:49 -0400)]
sim: SystemC hosting
This patch hosts gem5 onto SystemC scheduler. There's already an upstream
review board patch that does something similar but this patch ...:
1) is less obtrusive to the existing gem5 code organisation. It's divided
into the 'generic' preparatory patches (already submitted) and this patch
which affects no existing files
2) does not try to exactly track the gem5 event queue with notifys into
SystemC and so doesn't requive the event queue to be modified for
anything other than 'out of event queue' scheduling events
3) supports debug logging with SC_REPORT
The patch consists of the files:
util/systemc/
sc_gem5_control.{cc,hh} -- top level objects to use to
instantiate gem5 Systems within
larger SystemC test harnesses as
sc_module objects
sc_logger.{cc,hh} -- logging support
sc_module.{cc,hh} -- a separated event loop specific to
SystemC
stats.{cc,hh} -- example Stats handling for the sample
top level
main.{cc,hh} -- a sample top level
On the downside this patch is only currently functional with C++
configuration at the top level.
The above sc_... files are indended to be compiled alongside gem5 (as a
library, see main.cc for a command line and util/systemc/README for
more details.)
The top-level system instantiation in sc_gem5_control.{cc,hh} provides
two classes: Gem5Control and Gem5System
Gem5Control is a simulation control class (from which a singleton
object should be created) derived from Gem5SystemC::Module which
carries the top level simulation control interface for gem5. This
includes hosting a system-building configuration file and
instantiating the Root object from that file.
Gem5System is a base class for instantiating renamed gem5 Systems
from the config file hosted by the Gem5Control object. In use, a
SystemC module class should be made which represents the desired,
instantiable gem5 System. That class's instances should create
a Gem5System during their construction, set the parameters of that
system and then call instantiate to build that system. If this
is all carried out in the sc_core::sc_module-derived classes
constructor, the System's external ports will become children of
that module and can then be recovered by name using sc_core::
sc_find_object.
It is intended that this interface is used with dlopen. To that
end, the header file sc_gem5_control.hh includes no other header
files from gem5 (and so can be easily copied into another project).
The classes Gem5System and Gem5Control have all their member
functions declared `virtual' so that those functions can be called
through the vtable acquired by building the top level Gem5Control
using dlsym(..., "makeGem5Control") and `makeSystem' on the
Gem5Control.
Andreas Hansson [Thu, 16 Oct 2014 09:49:53 +0000 (05:49 -0400)]
sim: EventQueue wakeup on events scheduled outside the event loop
This patch adds a 'wakeup' member function to EventQueue which should be
called on an event queue whenever an event is scheduled on the event queue
from outside code within the call tree of the gem5 event loop.
This clearly isn't necessary for normal gem5 EventQueue operation but
becomes the minimum necessary interface to allow hosting gem5's event loop
onto other schedulers where there may be calls into gem5 from external
code which schedules events onto an EventQueue between the current time and
the time of the next scheduled event.
The use case I have in mind is a SystemC hosting where the event loop is:
while (more events) {
wait(time_to_next_event or wakeup)
setCurTick
service events at this time
}
where the 'wait' needs to be woken up if time_to_next_event becomes shorter
due to a scheduled event from SystemC arriving in a gem5 object.
Requiring 'wakeup' to be called is a more efficient interface than
requiring all gem5 event scheduling actions to affect the host scheduler.
This interface could be located elsewhere, say on another global object,
or by being passed by the host scheduler to objects which will schedule
such events, but it seems cleanest to put it on EventQueue as it is
actually a signal to the queue.
EventQueue::wakeup is called for async_event events on event queue 0 as
it's only important that *some* queue be triggered for such events.
Andrew Bardsley [Thu, 16 Oct 2014 09:49:53 +0000 (05:49 -0400)]
base: Reimplement the DPRINTF mechanism in a Logger class
This patch adds a Logger class encapsulating dprintf. This allows
variants of DPRINTF logging to be constructed and substituted in
place of the default behaviour.
The Logger provides a logMessage(when, name, format, ...) member
function like Trace::dprintf and a getOstream member function to
use a raw ostream for logging.
A class OstreamLogger is provided which generates the customary
debugging output with Trace::OstreamLogger::logMessage being the
old Trace::dprintf.
Andreas Hansson [Thu, 16 Oct 2014 09:49:51 +0000 (05:49 -0400)]
arch: Use shared_ptr for all Faults
This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".
Andreas Hansson [Thu, 16 Oct 2014 09:49:49 +0000 (05:49 -0400)]
o3: Use shared_ptr for MemDepEntry
This patch transitions the o3 MemDepEntry from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly replacing "new" with
"make_shared".
Andreas Hansson [Thu, 16 Oct 2014 09:49:49 +0000 (05:49 -0400)]
mem: Use shared_ptr for Ruby Message classes
This patch transitions the Ruby Message and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".
The cloning of derived messages is slightly changed as they previously
relied on overriding the base-class through covariant return types.
Andreas Hansson [Thu, 16 Oct 2014 09:49:48 +0000 (05:49 -0400)]
base: Use shared_ptr for stat Node
This patch transitions the stat Node and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".
Andreas Hansson [Thu, 16 Oct 2014 09:49:47 +0000 (05:49 -0400)]
base: Transition CP annotate to use shared_ptr
Andreas Hansson [Thu, 16 Oct 2014 09:49:46 +0000 (05:49 -0400)]
dev: Use shared_ptr for EthPacketData
This patch transitions the EthPacketData from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly replacing "new" with
"make_shared".
The bool casting operator for the shared_ptr is explicit, and we must
therefore either cast it, compare it to NULL (p != nullptr), double
negate it (!!p) or do a (p ? true : false).
Andreas Hansson [Thu, 16 Oct 2014 09:49:45 +0000 (05:49 -0400)]
dev: Use shared_ptr for Arguments::Data
This patch takes a first few steps in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly introducing the
use of make_shared.
Note that the class could use unique_ptr rather than shared_ptr, was
it not for the postfix increment and decrement operators.
Andreas Hansson [Thu, 16 Oct 2014 09:49:44 +0000 (05:49 -0400)]
arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.
--HG--
rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
Andreas Hansson [Thu, 16 Oct 2014 09:49:43 +0000 (05:49 -0400)]
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
Andreas Sandberg [Thu, 16 Oct 2014 09:49:42 +0000 (05:49 -0400)]
arm: Add helper methods to setup architected PMU events
Andreas Sandberg [Thu, 16 Oct 2014 09:49:41 +0000 (05:49 -0400)]
cpu: Probe points for basic PMU stats
This changeset adds probe points that can be used to implement PMU
counters for CPU stats. The following probes are supported:
* BaseCPU::ppCycles / Cycles
* BaseCPU::ppRetiredInsts / RetiredInsts
* BaseCPU::ppRetiredLoads / RetiredLoads
* BaseCPU::ppRetiredStores / RetiredStores
* BaseCPU::ppRetiredBranches RetiredBranches
Andreas Sandberg [Thu, 16 Oct 2014 09:49:41 +0000 (05:49 -0400)]
arm: Add TLB PMU probes
This changeset adds probe points that can be used to implement PMU
counters for TLB stats. The following probes are supported:
* ArmISA::TLB::ppRefills / TLB Refills (TLB insertions)
Andreas Sandberg [Thu, 16 Oct 2014 09:49:40 +0000 (05:49 -0400)]
cpu: Add branch predictor PMU probe points
This changeset adds probe points that can be used to implement PMU
counters for branch predictor stats. The following probes are
supported:
* BPRedUnit::ppBranches / Branches
* BPRedUnit::ppMisses / Misses
Andreas Sandberg [Thu, 16 Oct 2014 09:49:39 +0000 (05:49 -0400)]
arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as
described in the ARMv8 reference manual. It supports most of the
features of the PMU, however the following features are known to be
missing:
* Event filtering (e.g., from different privilege levels).
* Access controls (the PMU currently ignores the execution level).
* The chain counter (event no. 0x1E) is unimplemented.
The PMU itself does not implement any events, it merely provides an
interface for the configuration scripts to hook up probes that drive
events. Configuration scripts should call addEventProbe() to configure
custom events or high-level methods to configure architected
events. The Python implementation of addEventProbe() automatically
delays event type registration until after instantiation.
In order to support CPU switching and some combined counters (e.g.,
memory references synthesized from loads and stores), the PMU allows
multiple probes per event type. When creating a system that switches
between CPU models that share the same PMU, PMU events for all of the
CPU models can be registered with the PMU.
Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
Andreas Sandberg [Thu, 16 Oct 2014 09:49:38 +0000 (05:49 -0400)]
sim: Add typedefs for PMU probe points
In order to show make PMU probe points usable across different PMU
implementations, we want a common probe interface. This patch the
namespace ProbePoins that contains typedefs for probe points that are
shared between multiple SimObjects. It also adds typedefs for the PMU
probe interface.
Andreas Sandberg [Thu, 16 Oct 2014 09:49:37 +0000 (05:49 -0400)]
sim: Add support for serializing BitUnionXX
BitUnion instances can normally not be used with the SERIALIZE_SCALAR
and UNSERIALIZE_SCALAR macros due to the way they are converted
between their storage type and their actual type. This changeset adds
a set of parm(In|Out) functions specifically for gem5 bit unions to
work around the issue.
Andreas Hansson [Thu, 16 Oct 2014 09:49:37 +0000 (05:49 -0400)]
config: Add the ability to read a config file using C++ and Python
This patch adds the ability to load in config.ini files generated from
gem5 into another instance of gem5 built without Python configuration
support. The intended use case is for configuring gem5 when it is a
library embedded in another simulation system.
A parallel config file reader is also provided purely in Python to
demonstrate the approach taken and to provided similar functionality
for as-yet-unknown use models. The Python configuration file reader
can read both .ini and .json files.
C++ configuration file reading:
A command line option has been added for scons to enable C++ configuration
file reading: --with-cxx-config
There is an example in util/cxx_config that shows C++ configuration in action.
util/cxx_config/README explains how to build the example.
Configuration is achieved by the object CxxConfigManager. It handles
reading object descriptions from a CxxConfigFileBase object which
wraps a config file reader. The wrapper class CxxIniFile is provided
which wraps an IniFile for reading .ini files. Reading .json files
from C++ would be possible with a similar wrapper and a JSON parser.
After reading object descriptions, CxxConfigManager creates
SimObjectParam-derived objects from the classes in the (generated with this
patch) directory build/ARCH/cxx_config
CxxConfigManager can then build SimObjects from those SimObjectParams (in an
order dictated by the SimObject-value parameters on other objects) and bind
ports of the produced SimObjects.
A minimal set of instantiate-replacing member functions are provided by
CxxConfigManager and few of the member functions of SimObject (such as drain)
are extended onto CxxConfigManager.
Python configuration file reading (configs/example/read_config.py):
A Python version of the reader is also supplied with a similar interface to
CxxConfigFileBase (In Python: ConfigFile) to config file readers.
The Python config file reading will handle both .ini and .json files.
The object construction strategy is slightly different in Python from the C++
reader as you need to avoid objects prematurely becoming the children of other
objects when setting parameters.
Port binding also needs to be strictly in the same port-index order as the
original instantiation.
Andreas Hansson [Thu, 16 Oct 2014 09:49:36 +0000 (05:49 -0400)]
scons: Add Undefined Behavior Sanitizer (UBSan) option
This patch adds the Undefined Behavior Sanitizer (UBSan) for clang and
gcc >= 4.9. Due to the performance impact, the usage is guarded by a
command-line option.
Curtis Dunham [Mon, 22 Sep 2014 19:37:23 +0000 (14:37 -0500)]
scons: Add --without-tcmalloc build option
Disabling tcmalloc is required for valgrind's memcheck to work properly;
this option makes it easier to create such a build.
Akash Bagdia [Tue, 2 Sep 2014 10:26:32 +0000 (11:26 +0100)]
arm: Don't speculatively access most miscregisters.
Speculative exeuction can cause panics in detailed execution mode that
shouldn't happen.
Curtis Dunham [Tue, 12 Aug 2014 22:35:28 +0000 (17:35 -0500)]
scons: Generate a single debug flag C++ file
Reduces target count/compiler invocations by ~180.
Curtis Dunham [Thu, 16 Oct 2014 09:49:33 +0000 (05:49 -0400)]
scons: create dummy target to have SWIG generate C++ classes
scons build/<arch>/swig
Andrew Bardsley [Thu, 16 Oct 2014 09:49:32 +0000 (05:49 -0400)]
config: Add a --without-python option to build process
Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.
This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.
This adds a few registration interfaces to things which cross
between Python and C++. Namely: stats dumping and SimObject resolving
Andreas Hansson [Thu, 16 Oct 2014 09:49:31 +0000 (05:49 -0400)]
stats: Small bump of trailing stats
Somehow these seem to have been missed.
Nilay Vaish [Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)]
stats: updates due to changes to x86, stale configs.
Andrew Lukefahr [Sat, 11 Oct 2014 21:16:02 +0000 (16:16 -0500)]
cpu: Fix o3 SMT IQCount bug
Commmitted by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 11 Oct 2014 21:16:00 +0000 (16:16 -0500)]
util: adds a script for using DSENT
This patch adds a python script that processes the configuration and the
statistics file from a simulation run. Configuration and activity of network
routers and links obtained from this processing is fed to DSENT via its Python
interface. DSENT then computes the area and the power consumption of these
network components. The script outputs these quantities to the console.
Nilay Vaish [Sat, 11 Oct 2014 21:16:00 +0000 (16:16 -0500)]
ext: dsent: adds a Python interface, drops C++ one
This patch extensively modifies DSENT so that it can be accessed using Python.
To access the Python interface, DSENT needs to compiled as a shared library.
For this purpose a CMakeLists.txt file has been added. Some of the code that
is not required is being removed.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ext: add the source code for DSENT
This patch adds a tool called DSENT to the ext/ directory. DSENT
is a tool that models power and area for on-chip networks. The next
patch adds a script for using the tool.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: network: garnet: add statistics for different activities
This patch adds some statistics to garnet that record the activity
of certain structures in the on-chip network. These statistics, in a later
patch, will be used for computing the energy consumed by the on-chip network.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: network: garnet: remove functions for computing power
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: drop Orion network power model
Orion is being dropped from ruby. It would be replaced with DSENT
which has better models. Note that the power / energy numbers reported
after this patch has been applied are not for use.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: mesi: slight renaming
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function. This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
ruby: structures: coorect #ifndef macros in header files
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
ruby: moesi hammer: correct typo in master-slave assignment
Jiuyue Ma [Fri, 13 Jun 2014 08:48:47 +0000 (16:48 +0800)]
x86: add LongModeAddressSize function to cpuid
LongModeAddressSize was used by kernel 2.6.28.4 for physical address
validation, if not properly implemented, PCI resource allocation may
failed because of ioremap failed:
- linux-2.6.28.4/arch/x86/mm/ioremap.c:27-30
27 static inline int phys_addr_valid(unsigned long addr)
28 {
29 return addr < (1UL << boot_cpu_data.x86_phys_bits);
30 }
- linux-2.6.28.4/arch/x86/kernel/cpu/common.c:475-482
475 #ifdef CONFIG_X86_64
476 if (c->extended_cpuid_level >= 0x80000008) {
477 u32 eax = cpuid_eax(0x80000008);
478
479 c->x86_virt_bits = (eax >> 8) & 0xff;
480 c->x86_phys_bits = eax & 0xff;
481 }
482 #endif
- linux-2.6.28.4/arch/x86/mm/ioremap.c:209-214
209 if (!phys_addr_valid(phys_addr)) {
210 printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
211 (unsigned long long)phys_addr);
212 WARN_ON_ONCE(1);
213 return NULL;
214 }
This patch return 0x0000ffff for LongModeAddressSize, which guarantee phys_addr_valid never failed.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jiuyue Ma [Thu, 17 Jul 2014 04:05:41 +0000 (12:05 +0800)]
config, x86: Ensure that PCI devs get bridged to the memory bus
This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by
reserve anything between the end of memory and 3GB if memory is less
than 3GB. It also statically bridge these address range to the IO bus,
which guaranty access to pci address space will pass though bridge to
iobus.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jiuyue Ma [Thu, 17 Jul 2014 03:00:12 +0000 (11:00 +0800)]
config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable
This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for
X86 platform. Because PCI device get config space address using
Pc::calcPciConfigAddr() which requires "assert(bus==0)".
This fixes PCI interrupt routing and discovery on Linux.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andrew Lukefahr [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
sim: draining bug for fast-forwaring multiple cores
fix draining bug where multiple cores hit max_insts_any_thread simultaneously
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
base: addr range: slight change to validity check
The validity check is being changed from < to <= since the end of the range
is considered to be a part of it.
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
base: misc: Add missing header file.
Andreas Hansson [Thu, 9 Oct 2014 21:52:13 +0000 (17:52 -0400)]
stats: Add DRAM power statistics to reference output
Omar Naji [Tue, 29 Jul 2014 16:22:44 +0000 (17:22 +0100)]
mem: DRAMPower integration for on-line DRAM power stats
This patch takes the final step in integrating DRAMPower and adds the
appropriate calls in the DRAM controller to provide the command trace
and extract the power and energy stats. The debug printouts are still
left in place, but will eventually be removed.
At the moment the DRAM power calculation is always on when using the
DRAM controller model. The run-time impact of this addition is around
1.5% when looking at the total host seconds of the regressions. We
deem this a sensible trade-off to avoid the complication of adding an
enable/disable mechanism.
Omar Naji [Tue, 29 Jul 2014 16:29:36 +0000 (17:29 +0100)]
mem: Add DRAMPower wrapping class
This patch adds a class to wrap DRAMPower Library in gem5.
This class initiates an object of class MemorySpecification
of the DRAMPower Library, passes the parameters from DRAMCtrl.py
to this object and creates an object of drampower library using
the memory specification.
Omar Naji [Fri, 25 Jul 2014 09:05:59 +0000 (10:05 +0100)]
mem: Add missig timing and current parameters to DRAM configs
This patch adds missing timing and current parameters to the existing
DRAM configs. These missing timing and current parameters are required
by DRAMPower for the DRAM power calculations. The missing values are
datasheet values of the specified DRAMs, and the appropriate
references are added for the variuos configs.
Omar Naji [Thu, 9 Oct 2014 21:52:04 +0000 (17:52 -0400)]
mem: Remove DRAMSim2 DDR3 configuration
This patch prunes the DDR3 config that was initially created to match
the default config of DRAMSim2. The config is not complete as it is,
and to avoid having to maintain it, the easiest way forward is to
simply prune it. Going forward we are adding power number etc to the
other configurations.
Andreas Hansson [Thu, 9 Oct 2014 21:52:03 +0000 (17:52 -0400)]
ext: Add DRAMPower to enable on-line DRAM power modelling
This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit
8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the
simulator. We have chosen this specific version of DRAMPower as it
provides the necessary functionality, and future updates will be
coordinated with the DRAMPower development team. The files added only
include the bits needed to build the library, thus excluding all
memory specifications, traces, and the stand-alone DRAMPower
command-line tool.
A future patch includes the DRAMPower functionality in the DRAM
controller, to enable on-line DRAM power modelling, and avoid using
post-processing of traces.
Andreas Hansson [Thu, 9 Oct 2014 21:52:00 +0000 (17:52 -0400)]
config: Add Current as a parameter type
This patch adds the Python parameter type Current, which is used for
the DRAM power modelling (to start with). With this addition we avoid
implicit unit assumptions.
Mitch Hayenga [Thu, 9 Oct 2014 21:51:58 +0000 (17:51 -0400)]
cpu: Remove Ozone CPU from the source tree
The Ozone CPU is now very much out of date and completely
non-functional, with no one actively working on restoring it. It is a
source of confusion for new users who attempt to use it before
realizing its current state. RIP
Andreas Hansson [Thu, 9 Oct 2014 21:51:57 +0000 (17:51 -0400)]
scons: Warn for known gcc and swig incompatibilities
Andreas Hansson [Thu, 9 Oct 2014 21:51:56 +0000 (17:51 -0400)]
mem: Add packet sanity checks to cache and MSHRs
This patch adds a number of asserts to the cache, checking basic
assumptions about packets being requests or responses.
Andreas Hansson [Thu, 9 Oct 2014 21:51:52 +0000 (17:51 -0400)]
mem: Allow packet queue to move next send event forward
This patch changes the packet queue such that when scheduling a send,
the queue is allowed to move the event forward.
Andreas Hansson [Wed, 1 Oct 2014 12:05:54 +0000 (08:05 -0400)]
misc: Fix issues identified by static analysis
Another bunch of issues addressed.
Andreas Hansson [Wed, 1 Oct 2014 12:05:52 +0000 (08:05 -0400)]
arm: Use MiscRegIndex rather than int when flattening
Some additional type checking to avoid future issues.
Andreas Hansson [Wed, 1 Oct 2014 12:05:51 +0000 (08:05 -0400)]
arm: More UBSan cleanups after additional full-system runs
Some incorrect casting to IntRegIndex, and a few uninitialized members
in the i8254xGBe device.
Andreas Hansson [Sun, 28 Sep 2014 20:53:48 +0000 (16:53 -0400)]
stats: Update stats to reflect ARM fixes
As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.