mesa.git
5 years agoradeonsi: add config entry for Counter-Strike Global Offensive
Timothy Arceri [Mon, 6 May 2019 04:39:44 +0000 (14:39 +1000)]
radeonsi: add config entry for Counter-Strike Global Offensive

This fixes rendering issues with gun scopes which is rather
important.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100239

5 years agolima/gpir: fix float uniform alignment issue
Vasily Khoruzhick [Wed, 1 May 2019 02:53:01 +0000 (19:53 -0700)]
lima/gpir: fix float uniform alignment issue

If PIPE_CAP_PACKED_UNIFORMS is not set uniforms are vec4 aligned,
so lima_nir_lower_uniform_to_scalar should use first channel of vec4
for float uniforms.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agodraw: flush when setting stream-out targets
Erik Faye-Lund [Wed, 1 May 2019 13:37:45 +0000 (15:37 +0200)]
draw: flush when setting stream-out targets

We need to re-prepare the middle-end state to pick up changes to this
state to react correctly to pausing/resuming stream-out. So let's add a
flush here.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: ec8cbd79ac4 "draw/softpipe: EXT_transform_feedback support (v2)"
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: pass stream-out targets to draw-module early
Erik Faye-Lund [Mon, 6 May 2019 13:35:04 +0000 (15:35 +0200)]
llvmpipe: pass stream-out targets to draw-module early

We currently set this state in the draw-module twice on each draw, but
which trashes this state. So far that's not a problem, because we don't
really do much from that function.

But it turns out, we're going to have to do more; namely flush when the
state changes. This will incur a large performance penalty due to the
excessive setting.

Instead, let's rely on the CSO caching making sure that
llvmpipe_set_so_targets doesn't get called needlessly, and setup the
state directly there instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agodoc: Update GL_KHR_robustness in features.txt for r600
Uros Bizjak [Mon, 6 May 2019 20:21:14 +0000 (06:21 +1000)]
doc: Update GL_KHR_robustness in features.txt for r600

glxinfo for Cypress XT [Radeon HD 5870] lists GL_KHR_robustness
as supported extension.  This was the last missing extension
for GL 4.5, so Mark GL 4.5 as all DONE for r600.

Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agovirgl: do not use inline writes for subdata
Chia-I Wu [Fri, 3 May 2019 17:40:38 +0000 (10:40 -0700)]
virgl: do not use inline writes for subdata

Inline writes skip transfer map/unamp at the cost of an extra copy
on the data during execbuffer.  That is generally a win for small
transfers.  But the heuristic to use inline writes based on buffer
sizes rather than transfer sizes makes little sense.  More
importantly, inline writes miss optimizations that are done for
buffer transfers.

Let's just use transfers.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: rework queries
Chia-I Wu [Mon, 18 Mar 2019 22:56:35 +0000 (15:56 -0700)]
virgl: rework queries

virglrender has been changed such that

 - VIRGL_CCMD_GET_QUERY_RESULT is fenced
 - query buffers (PIPE_BIND_CUSTOM) are coherent

We can check if a query is ready using DRM_IOCTL_VIRTGPU_WAIT, and also
avoid a synchronized transfer to retrieve the query result.  When
running against an older virglrenderer, it falls back to the old
behavior automatically.

TF2 @ 640x480 for pts4.dem went from 17fps to 40fps on my testing
machine.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agovirgl: export resource_is_busy from winsys
Chia-I Wu [Tue, 19 Mar 2019 18:13:40 +0000 (11:13 -0700)]
virgl: export resource_is_busy from winsys

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agoradv: fix rowPitch for R32G32B32 formats on GFX9
Samuel Pitoiset [Mon, 6 May 2019 14:17:26 +0000 (16:17 +0200)]
radv: fix rowPitch for R32G32B32 formats on GFX9

The pitch is actually the number of components per row. We found
the problem when we implemented some meta operations for these
formats and the wrong pitch has been confirmed with a small test case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108325
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoiris: Enable PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
Kenneth Graunke [Wed, 1 May 2019 21:34:00 +0000 (14:34 -0700)]
iris: Enable PIPE_CAP_SURFACE_REINTERPRET_BLOCKS

This makes CompressedTexSubImage from a PBO source do proper GPU
rendering to upload instead of stalling to map the PBO source on
the CPU (then copying it on the CPU).

Thanks Bas Nieuwenhuizen for pointing out that Vulkan includes this
functionality, and to Jason Ekstrand for writing the code I adapted.
Vulkan only supports a single layer, however, and this code tries to
support multiple layers as long as it's miplevel 0.

Improves performance in Sid Meier's Civilization VI:

   Average frame time (ms):         -3.67423% +/- 1.46201% (n=5)
   99th percentile frame time (ms): -5.09910% +/- 3.87874% (n=5)

5 years agoradv: Use given stride for images imported from Android.
Bas Nieuwenhuizen [Mon, 6 May 2019 13:44:04 +0000 (15:44 +0200)]
radv: Use given stride for images imported from Android.

Handled similarly as radeonsi. I checked the offsets are actually used.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agolima/ppir: abort compilation in case of unsupported intrinsic
Erico Nunes [Sun, 5 May 2019 08:53:33 +0000 (10:53 +0200)]
lima/ppir: abort compilation in case of unsupported intrinsic

Currently ppir continues compilation when there is an unsupported
intrinsic, resulting in a shader that will surely not work as intended.

This is a problem during piglit runs as some tests don't compile
properly due to this but actually still get submitted to the gpu and
leave the system in an unstable state after executing, causing further
tests to fail.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agolima/ir: print names of unsupported intrinsics
Erico Nunes [Sun, 5 May 2019 08:51:43 +0000 (10:51 +0200)]
lima/ir: print names of unsupported intrinsics

While lima still doesn't support some kinds of intrinsics, it is more
helpful to display the name of the unsupported instr->intrinsic to make
debugging easier.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agomesa: Makefile.sources: Add nir_lower_fb_read.c to Makefile.sources list
John Stultz [Thu, 2 May 2019 20:36:11 +0000 (13:36 -0700)]
mesa: Makefile.sources: Add nir_lower_fb_read.c to Makefile.sources list

In commit a99c360a4630 (nir: add pass to lower fb reads), a new
file was added that needs to also be added to the
Makefile.sources list used by the Android and SCons build system.

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes: a99c360a463 ("nir: add pass to lower fb reads")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agomesa: Makefile.sources: Add ir3_nir_lower_load_barycentric_at_sample/offset to Makefi...
John Stultz [Fri, 3 May 2019 16:17:57 +0000 (09:17 -0700)]
mesa: Makefile.sources: Add ir3_nir_lower_load_barycentric_at_sample/offset to Makefile.sources

In commit 2f0b9d22495 ("freedreno/ir3: lower
load_barycentric_at_offset") a new file was added that needs to
also be added to the Makefile.sources list used by Android and
SCons build system.

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 2f0b9d22495 ("freedreno/ir3: lower load_barycentric_at_offset")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agomesa: android: freedreno: Fix build failure due to path change
John Stultz [Thu, 2 May 2019 16:25:57 +0000 (09:25 -0700)]
mesa: android: freedreno: Fix build failure due to path change

The ir3_nir_trig.py file was moved in a previous commit,
aa0fed10d3574 (freedreno: move ir3 to common location),
so update the Android.gen.mk file to match.

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes: aa0fed10d35 ("freedreno: move ir3 to common location")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agomesa: android: freedreno: build libfreedreno_{drm,ir3} static libs
Amit Pundir [Tue, 30 Apr 2019 07:36:19 +0000 (13:06 +0530)]
mesa: android: freedreno: build libfreedreno_{drm,ir3} static libs

Add libfreedreno_drm/ir3 to the build

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes: b4476138d5a ("freedreno: move drm to common location")
Fixes: aa0fed10d35 ("freedreno: move ir3 to common location")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
[jstultz: Tweaked to add extra ir3 files from master]
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agomesa: android: Remove unnecessary dependency tracking rules
Alistair Strachan [Wed, 19 Sep 2018 22:05:33 +0000 (15:05 -0700)]
mesa: android: Remove unnecessary dependency tracking rules

The current AOSP master build system breaks building mesa due to the
following error:

external/mesa3d/src/compiler/Android.glsl.gen.mk:94: error:
  writing to readonly directory: "external/mesa3d/src/compiler/glsl/ir.h"

This error is bogus -- nothing "writes" to ir.h -- but the rule is
unnecessary because the generated header that is a dependency of the
non-generated header should be added to LOCAL_GENERATED_SOURCES and this
will track if the dependency needs to be regenerated.

(This change fixes a similar problem affecting nir.h too.)

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Alistair Strachan <astrachan@google.com>
[jstultz: Forward ported and tweaked commit subject]
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agoradv: Implement cosited_even sampling.
Bas Nieuwenhuizen [Mon, 6 May 2019 00:15:55 +0000 (02:15 +0200)]
radv: Implement cosited_even sampling.

Apparently cosited_even was the required one instead of midpoint.

This adds slight offset of 0.5 pixels to the coordinates (+ we need
the image size to convert to normalized coords)

Fixes: 91702374d5d "radv: Add ycbcr lowering pass."
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoRestore erroneously removed .gitignore entry for "build" directory
Michel Dänzer [Fri, 3 May 2019 08:12:56 +0000 (10:12 +0200)]
Restore erroneously removed .gitignore entry for "build" directory

It was removed in "delete autotools .gitignore files", but the build
directory is created by scons.

[Skip CI]

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoradv: Disable subsampled formats.
Bas Nieuwenhuizen [Sun, 5 May 2019 23:42:21 +0000 (01:42 +0200)]
radv: Disable subsampled formats.

Broken on Polaris and since I discovered NV12 is not subsampled, but
a 2-plane format I decided I don't really care.

Work to do to re-enable:

1) Figure out which devices support it natively.
2) Write some software emulation for the others.

Fixes: 52c1adda21b "radv: Add ycbcr format features."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoutil/drirc: add workarounds for bugs in Doom 3: BFG
Timothy Arceri [Fri, 3 May 2019 03:59:05 +0000 (13:59 +1000)]
util/drirc: add workarounds for bugs in Doom 3: BFG

This makes the game playable on radeonsi.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110143

5 years agofreedreno: remove unused forward struct declaration
Rob Clark [Sat, 4 May 2019 20:59:20 +0000 (13:59 -0700)]
freedreno: remove unused forward struct declaration

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agopanfrost/midgard: iabs cannot run on mul
Alyssa Rosenzweig [Fri, 3 May 2019 03:27:18 +0000 (03:27 +0000)]
panfrost/midgard: iabs cannot run on mul

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Lower mixed csel (NIR)
Alyssa Rosenzweig [Fri, 3 May 2019 03:16:14 +0000 (03:16 +0000)]
panfrost/midgard: Lower mixed csel (NIR)

Basically, when the conditions of a csel diverge, we scalarize to avoid
going into weird code paths during emit. We could be doing better, but
this case can't occur organically from GLSL as far as I can, though it
does fix lowered atan2.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Fix RA when temp_count = 0
Alyssa Rosenzweig [Fri, 3 May 2019 02:50:16 +0000 (02:50 +0000)]
panfrost/midgard: Fix RA when temp_count = 0

A previous commit by Tomeu aborted RA early, which solves the memory
corruption issue, but then generates an incorrect compile. This fixes
that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Fix integer selection
Alyssa Rosenzweig [Fri, 3 May 2019 01:54:16 +0000 (01:54 +0000)]
panfrost/midgard: Fix integer selection

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Support RGB565 FBOs
Alyssa Rosenzweig [Thu, 2 May 2019 02:27:04 +0000 (02:27 +0000)]
panfrost: Support RGB565 FBOs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Handle dest_override generalized
Alyssa Rosenzweig [Wed, 1 May 2019 02:00:08 +0000 (02:00 +0000)]
panfrost/midgard/disasm: Handle dest_override generalized

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Stub out 64-bit
Alyssa Rosenzweig [Tue, 30 Apr 2019 23:19:41 +0000 (23:19 +0000)]
panfrost/midgard/disasm: Stub out 64-bit

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Print 8-bit sources
Alyssa Rosenzweig [Tue, 30 Apr 2019 19:16:22 +0000 (19:16 +0000)]
panfrost/midgard/disasm: Print 8-bit sources

This handles the usual case. 8-bit register access parallels 16-bit
access, but with one major caveat: in 8-bit mode, only half of the
register file is actually (directly) accessible as sources. In
particular, for each 16-bit integer register (hrN), we can only index a
*single* 8-bit integer (qrN), corresponding to the lower 8-bits. To get
the upper 8-bits, it is required to do an explicit shift. For example,
to add the bytes of a 16-bit integer hr0.x and get the result as an
8-bit qr0, you'd need to do something like:

   ilsr hr1.x, hr0.x, #8
   iadd qr0.x, qr0.x, qr1.x

This scheme diverges from 32-bit registers, in that both the upper and
lower halves of a 32-bit register are individually accessible as a pair
of half registers. For contrast, to add the lower and upper 16-bits of a
32-bit integer r0.x, you can just:

   iadd hr0.x, hr0.x, hr1.x

Since hr1.x = upper 16-bit of r0.x.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Support 8-bit destination
Alyssa Rosenzweig [Tue, 30 Apr 2019 19:05:49 +0000 (19:05 +0000)]
panfrost/midgard/disasm: Support 8-bit destination

Meanwhile, we're forced to disable dest_override, since it's not yet
clear how this interacts with other bitnesses (it'll likely need to be
overhauled in any case).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Rename ilzcnt8 -> iclz
Alyssa Rosenzweig [Tue, 30 Apr 2019 06:19:33 +0000 (06:19 +0000)]
panfrost/midgard: Rename ilzcnt8 -> iclz

Per OpenCL.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Fix crash on unknown op
Alyssa Rosenzweig [Tue, 30 Apr 2019 05:06:18 +0000 (05:06 +0000)]
panfrost/midgard: Fix crash on unknown op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Fill in .int mod
Alyssa Rosenzweig [Tue, 30 Apr 2019 04:59:28 +0000 (04:59 +0000)]
panfrost/midgard/disasm: Fill in .int mod

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Extend print_reg to 8-bit
Alyssa Rosenzweig [Tue, 30 Apr 2019 04:58:52 +0000 (04:58 +0000)]
panfrost/midgard/disasm: Extend print_reg to 8-bit

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard/disasm: Catch mask errors
Alyssa Rosenzweig [Tue, 30 Apr 2019 04:52:36 +0000 (04:52 +0000)]
panfrost/midgard/disasm: Catch mask errors

We silently ignored certain bits of the mask, which causes issues when
disassembly 8/64-bit ops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: reg_mode_full -> reg_mode_32, etc
Alyssa Rosenzweig [Tue, 30 Apr 2019 02:19:26 +0000 (02:19 +0000)]
panfrost/midgard: reg_mode_full -> reg_mode_32, etc

In preparation for 8-bit and 64-bit operands, let's not reinforce the
32-bit-centric biases in the ISA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agofreedreno/a6xx: deduplicate a few lines
Rob Clark [Sat, 4 May 2019 16:16:58 +0000 (09:16 -0700)]
freedreno/a6xx: deduplicate a few lines

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno: add ubwc_enabled helper
Rob Clark [Sat, 4 May 2019 16:02:54 +0000 (09:02 -0700)]
freedreno:  add ubwc_enabled helper

Since it is dependent on the tile mode (ie. disabled for smaller mipmap
levels), we should handle it a similar way to fd_resource_level_linear().
The code previously mostly did the right thing because the old helper
took the tile mode.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno: move UBWC color offset to fd_resource_offset()
Rob Clark [Sat, 4 May 2019 15:04:59 +0000 (08:04 -0700)]
freedreno: move UBWC color offset to fd_resource_offset()

Best to keep it encapsulated in the helper which returns layer/level
offset (and actually use that helper everywhere) rather than spreading
the logic around the code.

Also add a helper to find UBWC offset, to complete the encapsulation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/a6xx: buffer resources cannot be compressed
Rob Clark [Sat, 4 May 2019 14:56:12 +0000 (07:56 -0700)]
freedreno/a6xx: buffer resources cannot be compressed

Small cleanup.  They are just an array of data and only ever linear/
uncompressed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno: mark imported resources as valid
Rob Clark [Sat, 4 May 2019 12:06:50 +0000 (05:06 -0700)]
freedreno: mark imported resources as valid

If someone is importing a buffer, we can't really know the state of it's
contents, so assume it is valid.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/a6xx: UBWC support for images
Rob Clark [Fri, 3 May 2019 20:39:45 +0000 (13:39 -0700)]
freedreno/a6xx: UBWC support for images

There are still some fallbacks we'll need to handle before we can enable
UBWC by default.  I think we may need to fallback to uncompressed if
image atomic operations are used.  And we still need to sort out how to
handle image and sampler views of compressed resources if the image/
sampler view is using a format that does not support compression.  (I
think the latter should hopefully be uncommon outside of deqp/piglit.)

But at least this gets us to the point where supertuxkart works properly
with UBWC enabled ;-)

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/a6xx: UBWC fixes
Rob Clark [Fri, 3 May 2019 20:10:22 +0000 (13:10 -0700)]
freedreno/a6xx: UBWC fixes

A few fixes that get UBWC working for the games/benchmarks where I
noticed problems before (in particular and manhattan, and stk (modulo
image support for UBWC when compute shaders are used for post-process
effects):

  + fix the size of the UBWC meta buffer (ie, the offset to color
    pixel data) that is returned by ->fill_ubwc_buffer_sizes()
  + correct size/layout for 8 and 16 byte per pixel formats
  + limit the supported formats.. Note all formats that can be
    tiled can be compressed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno: update generated headers
Rob Clark [Fri, 3 May 2019 17:23:00 +0000 (10:23 -0700)]
freedreno: update generated headers

Corrects tex state ubwc pitch/size

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/a6xx: OUT_RELOC vs OUT_RELOCW fixes
Rob Clark [Fri, 3 May 2019 13:22:08 +0000 (06:22 -0700)]
freedreno/a6xx: OUT_RELOC vs OUT_RELOCW fixes

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/ir3: remove assert
Rob Clark [Fri, 3 May 2019 16:33:34 +0000 (09:33 -0700)]
freedreno/ir3: remove assert

Fixes dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 and .20

ca3eb5db665cbcc2de5a5d3158e3dc68f86e5822 went from silently truncating
the constant state, which was also the wrong thing to do, to an assert.
Which then showed up in a couple of dEQPs.  Actually there is nothing
wrong with larger constant file so just drop the assert.

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agospirv/cl: support vload/vstore
Karol Herbst [Thu, 25 Oct 2018 22:42:52 +0000 (00:42 +0200)]
spirv/cl: support vload/vstore

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir: Add nir_op_vec helper
Karol Herbst [Wed, 20 Mar 2019 17:11:20 +0000 (18:11 +0100)]
nir: Add nir_op_vec helper

with that we can simplify code where nir vectors are created

v2: merge both lines in nir_vec

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir: Add a nir_builder_alu variant which takes an array of components
Karol Herbst [Wed, 20 Mar 2019 17:09:20 +0000 (18:09 +0100)]
nir: Add a nir_builder_alu variant which takes an array of components

v2: rename to nir_build_alu_src_arr

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agovtn: handle bitcast with pointer src/dest
Karol Herbst [Sat, 9 Mar 2019 19:32:52 +0000 (20:32 +0100)]
vtn: handle bitcast with pointer src/dest

v2: use vtn_push_ssa and vtn_ssa_value

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agomesa: Leave aliasing of vertex and generic0 attribute to the dlist code.
Mathias Fröhlich [Mon, 29 Apr 2019 05:23:58 +0000 (07:23 +0200)]
mesa: Leave aliasing of vertex and generic0 attribute to the dlist code.

Now that dlist compilation again knows if it is inside glBegin/glEnd,
we can leave the decision if aliasing should occur to the vertex attribute
setter functions instead of doing that at glArrayElement time.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Correct the is_vertex_position decision for dlists.
Mathias Fröhlich [Mon, 29 Apr 2019 05:23:58 +0000 (07:23 +0200)]
mesa: Correct the is_vertex_position decision for dlists.

We have to use _mesa_inside_dlist_begin_end instead of
_mesa_inside_begin_end to see if we are inside a glBegin/glEnd block in
case of display lists.
So split the is_vertex_position function used in vertex attribute processing
into a imm and dlist variant and use the appropriate _mesa_inside_begin_end
variant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Set CurrentSavePrimitive in vbo_save_NotifyBegin.
Mathias Fröhlich [Mon, 29 Apr 2019 05:23:58 +0000 (07:23 +0200)]
mesa: Set CurrentSavePrimitive in vbo_save_NotifyBegin.

That seems to be lost somewhere. Is needed for correct outside begin/end
detection in display list compilation. And is needed for correct aliasing
in dlists restablished in the next changes.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Remove the _glapi_table argument from _mesa_array_element.
Mathias Fröhlich [Wed, 3 Apr 2019 11:28:57 +0000 (13:28 +0200)]
mesa: Remove the _glapi_table argument from _mesa_array_element.

The value is now unused.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Constify static const array in api_arrayelt.c
Mathias Fröhlich [Wed, 3 Apr 2019 11:28:19 +0000 (13:28 +0200)]
mesa: Constify static const array in api_arrayelt.c

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Remove the now unused _NEW_ARRAY state change flag.
Mathias Fröhlich [Wed, 3 Apr 2019 11:25:22 +0000 (13:25 +0200)]
mesa: Remove the now unused _NEW_ARRAY state change flag.

Is no longer used, so we have less occasions where NewState is non zero.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Rip out now unused gl_context::aelt_context.
Mathias Fröhlich [Fri, 3 May 2019 04:53:21 +0000 (06:53 +0200)]
mesa: Rip out now unused gl_context::aelt_context.

Now this part of gl_context state is unused and can be removed.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Implement _mesa_array_element by walking enabled arrays.
Mathias Fröhlich [Wed, 3 Apr 2019 11:06:33 +0000 (13:06 +0200)]
mesa: Implement _mesa_array_element by walking enabled arrays.

In glArrayElement, use the bitmask trick to just walk the enabled
vao arrays. This should be about equivalent in execution time to
walk the prepare aelt_context list. Finally this will allow us to
reduce the _mesa_update_state calls in a few patches.

v2: Add comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Use glVertexAttrib*NV functions for fixed function attribs.
Mathias Fröhlich [Wed, 3 Apr 2019 10:47:36 +0000 (12:47 +0200)]
mesa: Use glVertexAttrib*NV functions for fixed function attribs.

In the glArrayElement implementation, use glVertexAttrib*NV type
functions for fixed function attributes. We do the same in display
execution when the list is replayed using immediate mode attribute
functions. Using a single set of function pointers enables to
use a unified loop to walk the vertex array attributes.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agomesa: Factor out index function that will have multiple use.
Mathias Fröhlich [Wed, 3 Apr 2019 10:33:37 +0000 (12:33 +0200)]
mesa: Factor out index function that will have multiple use.

For access to glArrayElement methods factor out a function to
get the table lookup index for normalized/integer/double access.
The function will be used in the next patch at least twice.

v2: Use vertex_format_to_index instead of NORM_IDX.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
5 years agonir: Add a SSA type gathering pass
Jason Ekstrand [Sat, 5 Jan 2019 15:13:44 +0000 (09:13 -0600)]
nir: Add a SSA type gathering pass

This new pass (which isn't even compile-tested) attempts to determine
the ALU type of all the SSA values in a function impl.  It takes a
greedy approach and assigns intness or floatness to everything it thinks
can possibly contain an int or a float.  Some values will be labled as
both int and float and some will be labled as neither and it is up to
the caller to decide what to do with this information.  However, for a
"nice" shader where the original source contained no bit-casts and no
implicit bit-casts were introduced by optimizations, there shouldn't be
any overlap in the two sets save for the odd CSEd zero constant.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agoiris: Delete bucketing allocators
Kenneth Graunke [Fri, 26 Apr 2019 01:30:57 +0000 (18:30 -0700)]
iris: Delete bucketing allocators

These add a lot of complexity, and I currently can't measure any
performance benefit from having them.  In the past, I seem to recall
seeing a benefit in drawoverhead scores, but currently it looks like
dropping them is either a wash or 1-2% faster.

Drop them to simplify allocations.

5 years agoiris: Force VMA alignment to be a multiple of the page size.
Kenneth Graunke [Sat, 27 Apr 2019 01:53:57 +0000 (18:53 -0700)]
iris: Force VMA alignment to be a multiple of the page size.

This should happen regardless, but let's be paranoid.

5 years agoiris: leave the top 4Gb of the high heap VMA unused
Kenneth Graunke [Fri, 3 May 2019 18:58:57 +0000 (11:58 -0700)]
iris: leave the top 4Gb of the high heap VMA unused

This ports commit 9e7b0988d6e98690eb8902e477b51713a6ef9cae from anv
to iris.  Thanks to Lionel for noticing that it was missing!

5 years agoiris: Fix 4GB memory zone heap sizes.
Kenneth Graunke [Sat, 27 Apr 2019 00:12:24 +0000 (17:12 -0700)]
iris: Fix 4GB memory zone heap sizes.

The STATE_BASE_ADDRESS "Size" fields can only hold 0xfffff in pages,
and 0xfffff * 4096 = 4294963200, which is 1 page shy of 4GB.

So we can't use the top page.

5 years agost/va: check resource_get_info nullity in vlVaDeriveImage
Julien Isorce [Thu, 2 May 2019 22:36:04 +0000 (15:36 -0700)]
st/va: check resource_get_info nullity in vlVaDeriveImage

This pipe_screen function is not implemented by all backends.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110443
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
5 years agoanv,i965: Stop warning about incomplete gen11 support
Jason Ekstrand [Fri, 3 May 2019 03:00:02 +0000 (22:00 -0500)]
anv,i965: Stop warning about incomplete gen11 support

Both drivers are feature-complete and should be running more-or-less at
perf at this point.  Drop the warning.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
5 years agonir/algebraic: Don't emit empty initializers for MSVC
Connor Abbott [Thu, 2 May 2019 20:22:01 +0000 (22:22 +0200)]
nir/algebraic: Don't emit empty initializers for MSVC

Just don't emit the transform array at all if there are no transforms

v2:
- Don't use len(array) > 0 (Dylan)
- Keep using ARRAY_SIZE to make the generated C code easier to read
(Jason).

5 years agoiris: Resolve textures used by the program, not merely bound textures
Kenneth Graunke [Thu, 2 May 2019 22:42:10 +0000 (15:42 -0700)]
iris: Resolve textures used by the program, not merely bound textures

st/mesa's PBO upload path binds a vertex shader that doesn't use any
textures, but leaves the existing sampler views bound in place.  This
was tricking us into thinking the PBO destination might be bound for
texturing in some cases.  In Civilization VI, this fixes a false self-
dependency issue that was preventing CCS_E compression on upload.
Fixing this slightly improves frame times.

5 years agomeson: Don't build glsl cache_test when shader cache is disabled
Dylan Baker [Tue, 22 May 2018 22:24:16 +0000 (15:24 -0700)]
meson: Don't build glsl cache_test when shader cache is disabled

v2: - Use new with_shader_cache variable instead of
      host_machine.system() == 'windows'

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agotests/vma: fix build with MSVC
Dylan Baker [Mon, 11 Jun 2018 22:11:07 +0000 (15:11 -0700)]
tests/vma: fix build with MSVC

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglsl/tests: define ssize_t on windows
Dylan Baker [Tue, 22 May 2018 22:32:22 +0000 (15:32 -0700)]
glsl/tests: define ssize_t on windows

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoutil/tests: Use define instead of VLA
Dylan Baker [Tue, 22 May 2018 22:00:35 +0000 (15:00 -0700)]
util/tests: Use define instead of VLA

To allow the this test to be built with MSVC, which doesn't support
VLAs.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomeson: make nm binary optional
Dylan Baker [Thu, 17 May 2018 20:44:30 +0000 (13:44 -0700)]
meson: make nm binary optional

This makes nm not required, but used if found. In general I imagine that
this means that on windows nm wont be found, and on other platforms it
will.

v2: - fix gbm and egl symbols check tests to only be run if nm is found
    - reword commit message to reflect the code change

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomeson: Make shader-cache a trillean instead of boolean
Dylan Baker [Wed, 18 Apr 2018 20:20:28 +0000 (13:20 -0700)]
meson: Make shader-cache a trillean instead of boolean

So that it can be implicitly disabled on windows, where it doesn't
compile.

v2: - Use an auto-option rather than automagic.
    - fix shader_cache check (== -> !=)
v4: - Use new with_shader_cache instead of get_option('shader-cache')
      elsewhere in the meson build

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomeson: switch gles1 and gles2 to auto options
Dylan Baker [Fri, 19 Oct 2018 16:47:41 +0000 (09:47 -0700)]
meson: switch gles1 and gles2 to auto options

This allows them to default to false on windows, but default to true
elsewhere. As a side effect turning off shared-glapi now automatically
turns off gles. Shared glapi remains a boolean defaulting to true.

v5: - new in this version

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglsl: fix general_ir_test with mingw
Dylan Baker [Wed, 18 Apr 2018 17:44:44 +0000 (10:44 -0700)]
glsl: fix general_ir_test with mingw

Somewhere down in the depths of the mingw headers 'interface' is
defined, change it to iface like a similar patch did.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomeson: always define libglapi
Dylan Baker [Wed, 18 Apr 2018 20:09:07 +0000 (13:09 -0700)]
meson: always define libglapi

This allows the identifier to be used even if shared-glapi isn't build,
which simplifies a bunch of things.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomeson: Fix missing glproto dependency for gallium-glx
Chuck Atkins [Fri, 3 May 2019 16:06:22 +0000 (12:06 -0400)]
meson: Fix missing glproto dependency for gallium-glx

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Cc: mesa-stable <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
5 years agoradv: apply the indexing workaround for atomic buffer operations on GFX9
Samuel Pitoiset [Fri, 3 May 2019 09:45:34 +0000 (11:45 +0200)]
radv: apply the indexing workaround for atomic buffer operations on GFX9

Because the new raw/struct intrinsics are buggy with LLVM 8
(they weren't marked as source of divergence), we fallback to the
old instrinsics for atomic buffer operations only. This means we need
to apply the indexing workaround for GFX9. The load/store
operations still use the new LLVM 8 intrinsics.

The fact that we need another workaround is painful but we should
be able to clean up that a bit once LLVM 7 support will be dropped.

This fixes a GPU hang with AC Odyssey and some rendering problems
with Nioh.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110573
Fixes: 31164cf5f70 ("ac/nir: only use the new raw/struct image atomic intrinsics with LLVM 9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoget_reviewer.pl: improve portability
Alyssa Ross [Fri, 19 Apr 2019 18:14:37 +0000 (18:14 +0000)]
get_reviewer.pl: improve portability

Not all package managers / users will install perl into /usr/bin,
but /usr/bin/env /should/ always be present.

Using /usr/bin/env means that we can't give the -w argument to Perl,
so I added `use warnings' in the script.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoanv: fix crash when application does not provide push constants
Lionel Landwerlin [Thu, 2 May 2019 14:08:42 +0000 (15:08 +0100)]
anv: fix crash when application does not provide push constants

Found while running Talos Principle.

As far as I can tell running a draw call with a pipeline having push
constants without the application having called vkCmdPushConstants
gives undefined push constant values.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
5 years agoradv: fix radv_get_aspect_format() for D+S formats
Samuel Pitoiset [Thu, 2 May 2019 16:07:11 +0000 (18:07 +0200)]
radv: fix radv_get_aspect_format() for D+S formats

This restores the previous behaviour before YCBCR landed. For D+S
formats, it returns the depth format.

This fixes an assertion with Thrones of Britannia.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110540
Fixes: 66507cc6563 ("radv: Add single plane image views & meta operations")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agointel/fs: Assert when brw_fs_nir sees a nir_deref_instr
Caio Marcelo de Oliveira Filho [Wed, 1 May 2019 23:31:14 +0000 (16:31 -0700)]
intel/fs: Assert when brw_fs_nir sees a nir_deref_instr

Since 09f1de97a76 "anv,i965: Lower away image derefs in the driver"
the backend compiler is not expected to handle any derefs, so let's
assert on it.

This helps identifying problems when a deref is not lowered and
"leaks" into the backend compiler.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agor600: implement resource_get_info
Julien Isorce [Thu, 2 May 2019 22:57:04 +0000 (15:57 -0700)]
r600: implement resource_get_info

Factoring code with resource_get_handle.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110443
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Dave Airlie airlied@redhat.com
5 years agoutil/bitset: fix bitset range mask calculations.
Dave Airlie [Mon, 29 Apr 2019 03:17:41 +0000 (13:17 +1000)]
util/bitset: fix bitset range mask calculations.

The MASK macro is used in the RANGE macro, and it should
return the pre-bitset word mask for the (b) value.

i.e.
BITSET_MASK(0) should be undefined since it's meaningless.
BITSET_MASK(31) should give 0x7fffffff
BITSET_MASK(32) should give 0xffffffff
BITSET_MASK(33) should give 0x00000001
BITSET_MASK(64) should give 0xffffffff

However then BITSET_RANGE ends up broken for cases where
it's (b) value is the 0,32,64 value as in that case the lower
mask would be 0 not 0xffffffff.

This fixes the unit tests that I've added, and my code that
uses bitsets.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: bb38cadb1c5f2 "More GLSL code"
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoutil/tests: add basic unit tests for bitset
Dave Airlie [Mon, 29 Apr 2019 02:24:58 +0000 (12:24 +1000)]
util/tests: add basic unit tests for bitset

The last test here currently fails as there is a bug in bitset.h

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir: fix lower vars to ssa for larger vector sizes.
Dave Airlie [Fri, 3 May 2019 03:23:45 +0000 (13:23 +1000)]
nir: fix lower vars to ssa for larger vector sizes.

This has a couple of hardcoded vec4 limits in it, change them
to the proper sizing to avoid future issues.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agospirv: fix SpvOpBitSize return value.
Dave Airlie [Fri, 3 May 2019 02:53:56 +0000 (12:53 +1000)]
spirv: fix SpvOpBitSize return value.

The spir-v spec says this returns a bool.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoiris: Disable dual source blending when shader doesn't handle it
Kenneth Graunke [Fri, 3 May 2019 04:14:49 +0000 (21:14 -0700)]
iris: Disable dual source blending when shader doesn't handle it

This is a port of Danylo's eca4a6548d07bbbb02a7768edb397bad7b72cfc2
which fixed the hang on i965.  It fixes GPU hangs in his new Piglit
test, arb_blend_func_extended-dual-src-blending-discard-without-src1.

I avoided my own review feedback here, and decided to simply adjust
3DSTATE_PS_BLEND rather than BLEND_STATE_ENTRY[0].  It has never been
clear to me which the hardware uses in every case.  However, whacking
the enable in 3DSTATE_PS_BLEND seems to be sufficient to fix the hang,
and that packet is already dynamic, so it's easy to handle.  I'd rather
avoid making BLEND_STATE_ENTRY[0] dynamic unless I have to.

5 years agoanv: Stop including POS in FS input limits
Jason Ekstrand [Mon, 29 Apr 2019 05:46:10 +0000 (00:46 -0500)]
anv: Stop including POS in FS input limits

It is an input but it comes in as part of the shader payload and doesn't
count towards the limits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agonir: fix nir tex print harder
Rob Clark [Thu, 2 May 2019 21:48:41 +0000 (14:48 -0700)]
nir: fix nir tex print harder

Fixes: 691d5a825a6 nir: rework tex instruction printing
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agodocs: fixup mistake in contents
Erik Faye-Lund [Thu, 2 May 2019 18:24:28 +0000 (20:24 +0200)]
docs: fixup mistake in contents

During a rebase, it seems I accidentally broke the contents-menu,
leading to a duplicate link to freedesktop.org. This was obviously not
intended. Let's fix this.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 7eee13c4679 ("docs: use dl/dd instead of blockquote for
       freedesktop link")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agolima/ppir: support nir_op_ftrunc
Erico Nunes [Tue, 23 Apr 2019 17:36:34 +0000 (19:36 +0200)]
lima/ppir: support nir_op_ftrunc

Support nir_op_ftrunc by turning it into a mov with a round to integer
output modifier.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agogitlab-ci: merge meson-glvnd into meson-swr
Eric Engestrom [Tue, 16 Apr 2019 16:06:53 +0000 (18:06 +0200)]
gitlab-ci: merge meson-glvnd into meson-swr

There's no need to have a whole build just for that flag, we can add it
to any build.

v2: Add a note about why we put glvnd where we did (by anholt).

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v2)
Acked-by: Dylan Baker <dylan@pnwbakers.com>
5 years agogitlab-ci: simplify meson job names
Eric Engestrom [Tue, 16 Apr 2019 16:06:30 +0000 (18:06 +0200)]
gitlab-ci: simplify meson job names

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
5 years agogitlab-ci: meson-gallium-radeonsi was a subset of meson-gallium-clover-llvm
Eric Engestrom [Tue, 16 Apr 2019 16:06:12 +0000 (18:06 +0200)]
gitlab-ci: meson-gallium-radeonsi was a subset of meson-gallium-clover-llvm

Let's just drop it.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
5 years agogitlab-ci: merge several meson jobs
Eric Engestrom [Fri, 8 Mar 2019 16:33:07 +0000 (16:33 +0000)]
gitlab-ci: merge several meson jobs

Merge the following into `meson-main`/`meson-loader-classic-dri`/
`meson-gallium-swr`:
- meson-vulkan
- meson-gallium-drivers-other
- meson-gallium-st-other

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
[ Michel Dänzer ]
* Rebase and fix up commit log.
* Don't set VULKAN_DRIVERS in meson-loader-classic-dri.
* Remove extraneous whitespace.
* Squash in follow-up fixes.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
[ anholt]
* Add a note why nine and swrast landed where they did.
* Switch from s/meson-vulkan/meson-main/ to
  s/meson-loader-classic-dri/meson-main/ which I think was the original
  intent

Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com> (anholt changes)
Acked-by: Dylan Baker <dylan@pnwbakers.com>