bugzilla-daemon [Fri, 29 May 2020 13:56:59 +0000 (13:56 +0000)]
[libre-riscv-dev] [Bug 263] LD/ST batching needed
Luke Kenneth Casson Leighton [Fri, 29 May 2020 14:14:45 +0000 (15:14 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 29may2020
bugzilla-daemon [Fri, 29 May 2020 13:56:59 +0000 (13:56 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Yehowshua [Fri, 29 May 2020 13:51:16 +0000 (09:51 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 29may2020
bugzilla-daemon [Fri, 29 May 2020 13:49:04 +0000 (13:49 +0000)]
[libre-riscv-dev] [Bug 357] New: create simplified (testing) version of Function Unit pipeline for test purposes
bugzilla-daemon [Fri, 29 May 2020 13:42:00 +0000 (13:42 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:04:33 +0000 (13:04 +0100)]
[libre-riscv-dev] daily kan-ban update 29may2020
Luke Kenneth Casson Leighton [Fri, 29 May 2020 10:30:49 +0000 (11:30 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Luke Kenneth Casson Leighton [Fri, 29 May 2020 02:45:50 +0000 (03:45 +0100)]
Re: [libre-riscv-dev] Rough Architectural Sketch
Yehowshua [Fri, 29 May 2020 01:58:59 +0000 (21:58 -0400)]
[libre-riscv-dev] Rough Architectural Sketch
bugzilla-daemon [Thu, 28 May 2020 23:57:33 +0000 (23:57 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Thu, 28 May 2020 23:53:01 +0000 (16:53 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Luke Kenneth Casson Leighton [Thu, 28 May 2020 23:47:37 +0000 (00:47 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
bugzilla-daemon [Thu, 28 May 2020 23:41:42 +0000 (23:41 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Thu, 28 May 2020 23:32:17 +0000 (16:32 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
bugzilla-daemon [Thu, 28 May 2020 23:18:18 +0000 (23:18 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Alain D D Williams [Thu, 28 May 2020 23:15:49 +0000 (00:15 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Luke Kenneth Casson Leighton [Thu, 28 May 2020 23:13:02 +0000 (00:13 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Yehowshua [Thu, 28 May 2020 23:09:33 +0000 (19:09 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Luke Kenneth Casson Leighton [Thu, 28 May 2020 23:06:04 +0000 (00:06 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Alain D D Williams [Thu, 28 May 2020 23:02:43 +0000 (00:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Luke Kenneth Casson Leighton [Thu, 28 May 2020 21:59:46 +0000 (22:59 +0100)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Alain D D Williams [Thu, 28 May 2020 21:51:05 +0000 (22:51 +0100)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Luke Kenneth Casson Leighton [Thu, 28 May 2020 21:04:29 +0000 (22:04 +0100)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Jacob Lifshay [Thu, 28 May 2020 20:51:34 +0000 (13:51 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
Yehowshua [Thu, 28 May 2020 20:37:25 +0000 (16:37 -0400)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Luke Kenneth Casson Leighton [Thu, 28 May 2020 20:35:53 +0000 (21:35 +0100)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Alain D D Williams [Thu, 28 May 2020 20:35:34 +0000 (21:35 +0100)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
bugzilla-daemon [Thu, 28 May 2020 20:34:10 +0000 (20:34 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Yehowshua [Thu, 28 May 2020 20:32:24 +0000 (16:32 -0400)]
Re: [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
Luke Kenneth Casson Leighton [Thu, 28 May 2020 20:28:52 +0000 (21:28 +0100)]
[libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time
bugzilla-daemon [Thu, 28 May 2020 20:27:22 +0000 (20:27 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Luke Kenneth Casson Leighton [Thu, 28 May 2020 20:03:17 +0000 (21:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 28may2020
bugzilla-daemon [Thu, 28 May 2020 20:00:00 +0000 (20:00 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 19:50:04 +0000 (19:50 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Thu, 28 May 2020 19:33:16 +0000 (12:33 -0700)]
[libre-riscv-dev] daily kan-ban update 28may2020
bugzilla-daemon [Thu, 28 May 2020 16:41:48 +0000 (16:41 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 16:20:15 +0000 (16:20 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Thu, 28 May 2020 15:41:52 +0000 (15:41 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Thu, 28 May 2020 15:39:06 +0000 (15:39 +0000)]
[libre-riscv-dev] [Bug 347] add setb (to CR pipeline?)
bugzilla-daemon [Thu, 28 May 2020 14:18:37 +0000 (14:18 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 13:26:22 +0000 (13:26 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Thu, 28 May 2020 13:07:30 +0000 (13:07 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Thu, 28 May 2020 12:38:44 +0000 (12:38 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Thu, 28 May 2020 12:35:44 +0000 (12:35 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
lkcl . [Thu, 28 May 2020 12:02:00 +0000 (13:02 +0100)]
[libre-riscv-dev] Fwd: power-gem5
bugzilla-daemon [Thu, 28 May 2020 10:44:25 +0000 (10:44 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Thu, 28 May 2020 10:44:25 +0000 (10:44 +0000)]
[libre-riscv-dev] [Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type
bugzilla-daemon [Thu, 28 May 2020 10:44:25 +0000 (10:44 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Thu, 28 May 2020 10:44:25 +0000 (10:44 +0000)]
[libre-riscv-dev] [Bug 356] fu POWER9 pipeline unit tests need to test RA=0
bugzilla-daemon [Thu, 28 May 2020 10:43:29 +0000 (10:43 +0000)]
[libre-riscv-dev] [Bug 356] New: fu POWER9 pipeline unit tests need to test RA=0
bugzilla-daemon [Thu, 28 May 2020 10:18:30 +0000 (10:18 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 10:03:53 +0000 (10:03 +0000)]
[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
bugzilla-daemon [Thu, 28 May 2020 06:51:35 +0000 (06:51 +0000)]
[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
bugzilla-daemon [Thu, 28 May 2020 02:59:21 +0000 (02:59 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 01:50:21 +0000 (01:50 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 01:33:08 +0000 (01:33 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Thu, 28 May 2020 01:18:42 +0000 (01:18 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 22:21:25 +0000 (22:21 +0000)]
[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline
Luke Kenneth Casson Leighton [Wed, 27 May 2020 22:09:31 +0000 (23:09 +0100)]
Re: [libre-riscv-dev] Power ISA v3.1 bug - parityw
Paul Mackerras [Wed, 27 May 2020 21:49:19 +0000 (07:49 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
bugzilla-daemon [Wed, 27 May 2020 21:42:32 +0000 (21:42 +0000)]
[libre-riscv-dev] [Bug 355] game theory "state" packet engine needed
bugzilla-daemon [Wed, 27 May 2020 21:04:35 +0000 (21:04 +0000)]
[libre-riscv-dev] [Bug 355] New: game theory "state" packet engine needed
bugzilla-daemon [Wed, 27 May 2020 19:43:34 +0000 (19:43 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 19:25:25 +0000 (19:25 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:56:53 +0000 (18:56 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:48:12 +0000 (18:48 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Luke Kenneth Casson Leighton [Wed, 27 May 2020 18:42:10 +0000 (19:42 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 18:40:38 +0000 (18:40 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:38:26 +0000 (18:38 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:33:52 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:24:09 +0000 (18:24 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:08:15 +0000 (18:08 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 17:58:34 +0000 (17:58 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Wed, 27 May 2020 17:56:04 +0000 (17:56 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 17:46:10 +0000 (17:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 17:42:40 +0000 (17:42 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 17:40:44 +0000 (17:40 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
Tobias Platen [Wed, 27 May 2020 17:29:39 +0000 (19:29 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 17:26:36 +0000 (17:26 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 16:45:13 +0000 (16:45 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Wed, 27 May 2020 16:35:04 +0000 (09:35 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 16:06:19 +0000 (16:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 14:57:34 +0000 (14:57 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Wed, 27 May 2020 14:49:42 +0000 (14:49 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:48:07 +0000 (14:48 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:21:21 +0000 (14:21 +0000)]
[libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed
bugzilla-daemon [Wed, 27 May 2020 14:43:44 +0000 (14:43 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:27:54 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:21:21 +0000 (14:21 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:09:09 +0000 (14:09 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:09:09 +0000 (14:09 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 27 May 2020 14:06:22 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Wed, 27 May 2020 14:01:40 +0000 (14:01 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Wed, 27 May 2020 13:34:21 +0000 (13:34 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
Luke Kenneth Casson Leighton [Wed, 27 May 2020 13:12:34 +0000 (14:12 +0100)]
[libre-riscv-dev] POWER9 formal correctness proofs collaboration
Luke Kenneth Casson Leighton [Wed, 27 May 2020 12:25:06 +0000 (13:25 +0100)]
[libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 11:14:46 +0000 (11:14 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 11:10:54 +0000 (11:10 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 27 May 2020 04:12:44 +0000 (04:12 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
projects / libre-riscv-dev.git / log