Gabe Black [Mon, 10 Oct 2011 07:31:51 +0000 (00:31 -0700)]
SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
Gabe Black [Mon, 10 Oct 2011 06:48:27 +0000 (23:48 -0700)]
[mq]: sefssparcregfile.patch
Gabe Black [Sun, 9 Oct 2011 11:44:02 +0000 (04:44 -0700)]
Interrupts: Make the IO APIC go get the local APICs.
This is so they don't have to declare themselves to the IO APIC and don't have
to have a pointer to the platform object.
Gabe Black [Sun, 9 Oct 2011 07:15:50 +0000 (00:15 -0700)]
SE/FS: Build the Interrupt objects in SE mode.
Gabe Black [Sun, 9 Oct 2011 06:24:34 +0000 (23:24 -0700)]
Configs: Use connectAllPorts to connect ports for simple-timing-ruby.
Gabe Black [Sun, 9 Oct 2011 06:24:32 +0000 (23:24 -0700)]
Ports: Print the port name when a port is used but not attached to anything.
Gabe Black [Tue, 4 Oct 2011 09:26:03 +0000 (02:26 -0700)]
SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
Gabe Black [Fri, 30 Sep 2011 07:29:07 +0000 (00:29 -0700)]
SE/FS: Remove System::platform and Platform::intrFrequency.
In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.
This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.
After this change, a platform will need to have a system, but a system won't
have to have a platform.
Gabe Black [Fri, 30 Sep 2011 07:28:40 +0000 (00:28 -0700)]
X86: Remove FULL_SYSTEM from the x86 faults.
Gabe Black [Fri, 30 Sep 2011 07:28:33 +0000 (00:28 -0700)]
SE/FS: Build the devices in SE mode.
Gabe Black [Fri, 30 Sep 2011 07:27:16 +0000 (00:27 -0700)]
SE/FS: Use the new FullSystem constant where possible.
Gabe Black [Tue, 27 Sep 2011 07:25:26 +0000 (00:25 -0700)]
O3: Tidy up some DPRINTFs in the LSQ.
Gabe Black [Tue, 27 Sep 2011 07:24:43 +0000 (00:24 -0700)]
Faults: Replace calls to genMachineCheckFault with M5PanicFault.
Gabe Black [Tue, 27 Sep 2011 07:17:09 +0000 (00:17 -0700)]
Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
Gabe Black [Tue, 27 Sep 2011 07:16:33 +0000 (00:16 -0700)]
Faults: Make the generic faults more consistent between SE and FS.
All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
Gabe Black [Tue, 27 Sep 2011 06:48:54 +0000 (23:48 -0700)]
ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.
Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
Nilay Vaish [Mon, 26 Sep 2011 17:18:32 +0000 (12:18 -0500)]
LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
Gabe Black [Mon, 26 Sep 2011 09:09:04 +0000 (02:09 -0700)]
SE/FS: Define a const bool FullSystem which will equal FULL_SYSTEM.
This constant will have the same value as FULL_SYSTEM but will not be usable
by the preprocessor. It can be substituted into places where FULL_SYSTEM is
used in a C++ context and will make it easier to find which parts of the
simulator still use FULL_SYSTEM with the preprocessor using grep.
Gabe Black [Sun, 25 Sep 2011 00:03:18 +0000 (17:03 -0700)]
SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
Gabe Black [Sat, 24 Sep 2011 23:59:11 +0000 (16:59 -0700)]
SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
Steve Reinhardt [Sat, 24 Sep 2011 15:12:26 +0000 (08:12 -0700)]
style.py: don't die on empty files
Gabe Black [Fri, 23 Sep 2011 09:42:22 +0000 (02:42 -0700)]
X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
Steve Reinhardt [Fri, 23 Sep 2011 01:59:55 +0000 (18:59 -0700)]
event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.
Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
Steve Reinhardt [Fri, 23 Sep 2011 01:59:54 +0000 (18:59 -0700)]
pseudo_inst: clean up workbegin/workend functions
Use exitSimLoop() function instead of explicitly scheduling
on mainEventQueue (which won't work once we go to multiple
event queues). Also introduced a local params variable to
shorten a lot of expressions.
Steve Reinhardt [Fri, 23 Sep 2011 01:58:14 +0000 (18:58 -0700)]
params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability.
Properly compare IpAddress objects (by value and not object identity).
Also fix up derived param classes (IpNetmask and IpWithPort)
similarly.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS, faults: Update how the PC is set.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Use inheritance to consolidate class definitions.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Get rid of the unused "count" field in FaultVals.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Consolidate the two AddressErrorFault variants.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Add constructors to the fault classes.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
SPARC: Remove #if FULL_SYSTEMs from the ISA description.
Gabe Black [Mon, 19 Sep 2011 13:14:02 +0000 (06:14 -0700)]
MIPS: Get rid of #if style config checks in the ISA description.
Gabe Black [Mon, 19 Sep 2011 13:09:15 +0000 (06:09 -0700)]
MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
Gabe Black [Mon, 19 Sep 2011 12:53:54 +0000 (05:53 -0700)]
MIPS: Get rid of the unused (and partially defined) CacheError fault.
Gabe Black [Mon, 19 Sep 2011 12:19:45 +0000 (05:19 -0700)]
Endianness: Make it easier to check the compiled in guest endianness.
It was technically possible but clumsy to determine what endianness a guest
was configured with using the state in byteswap.hh. This change makes that
information available more directly.
Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
Gabe Black [Mon, 19 Sep 2011 10:40:30 +0000 (03:40 -0700)]
Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
Gabe Black [Mon, 19 Sep 2011 10:39:58 +0000 (03:39 -0700)]
PseudoInst: Make all the pseudo insts available in SE and FS.
Gabe Black [Mon, 19 Sep 2011 09:53:37 +0000 (02:53 -0700)]
X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
Gabe Black [Mon, 19 Sep 2011 09:46:48 +0000 (02:46 -0700)]
Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
Gabe Black [Mon, 19 Sep 2011 09:40:19 +0000 (02:40 -0700)]
PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
Gabe Black [Mon, 19 Sep 2011 06:26:39 +0000 (23:26 -0700)]
Pseudoinst: Add an initParam pseudo inst function.
Ali Saidi [Sat, 17 Sep 2011 16:34:03 +0000 (12:34 -0400)]
MIPS: Fix regressions tests
Ali Saidi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
IGbE: Clean up debug printing and proprly account for copied bytes.
Some DPRINTFs were printing uninitalized values because the DPRINTFs were
always being printed even when the features they were printing weren't
being used. This change moves the DPRINTFs into the appropriate if blocks
and initializes the state variables correctly.
There also is a case where the offset into the packet could be calculated
incorrectly during a DMA that is fixed.
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
ARM: update TLB to set request packet ASID field
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
Mem: Allow ASID to be set after request is created.
Chander Sudanthi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
ARM: Implement numcpus bits in L2CTLR register.
Ali Saidi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
Prakash Ramrakhyani [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
gem5ops: Implement Java JNI for gem5Ops
These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;
public class HelloWorld {
public static void main(String[] args) {
gem5Op gem5 = new gem5Op();
System.out.println("Rpns0:" + gem5.rpns());
System.out.println("Rpns1:" + gem5.rpns());
}
static {
System.loadLibrary("gem5OpJni");
}
}
When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java
and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
Ali Saidi [Tue, 13 Sep 2011 16:58:09 +0000 (12:58 -0400)]
O3: Update stats for new ordering fix.
Ali Saidi [Tue, 13 Sep 2011 16:58:08 +0000 (12:58 -0400)]
LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).
This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.
The performance improvement on SPEC benchmarks can be substantial (2-10%).
Deyuan Guo [Sat, 10 Sep 2011 10:45:25 +0000 (03:45 -0700)]
MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.
Testing:
Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
Gabe Black [Sat, 10 Sep 2011 09:31:15 +0000 (02:31 -0700)]
PseudoInst: Add compiler guards to pseudo_inst.hh.
Gabe Black [Fri, 9 Sep 2011 09:40:11 +0000 (02:40 -0700)]
StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
Gabe Black [Fri, 9 Sep 2011 09:30:01 +0000 (02:30 -0700)]
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
Gabe Black [Fri, 9 Sep 2011 08:35:05 +0000 (01:35 -0700)]
MIPS: Update MIPS stats for cleaned up operand checks.
Gabe Black [Fri, 9 Sep 2011 08:01:43 +0000 (01:01 -0700)]
Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
Gabe Black [Thu, 8 Sep 2011 10:21:14 +0000 (03:21 -0700)]
ISA parser: Don't look for operands in strings.
Gabe Black [Thu, 8 Sep 2011 10:20:05 +0000 (03:20 -0700)]
ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
Gabe Black [Tue, 6 Sep 2011 01:36:26 +0000 (18:36 -0700)]
X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
Gabe Black [Mon, 5 Sep 2011 09:48:57 +0000 (02:48 -0700)]
X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
Lisa Hsu [Sat, 3 Sep 2011 00:04:00 +0000 (17:04 -0700)]
TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why. Add a little warn() to explain it a bit. Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
Lisa Hsu [Thu, 1 Sep 2011 22:25:54 +0000 (15:25 -0700)]
Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
Lisa Hsu [Thu, 1 Sep 2011 18:41:44 +0000 (11:41 -0700)]
Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.
Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
Nilay Vaish [Mon, 29 Aug 2011 11:34:40 +0000 (06:34 -0500)]
SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
Nilay Vaish [Mon, 29 Aug 2011 10:10:23 +0000 (05:10 -0500)]
Ruby: Remove some unused code
Nilay Vaish [Fri, 26 Aug 2011 17:27:58 +0000 (12:27 -0500)]
Ruby: Eliminate modulo op for computing set size.
Ali Saidi [Fri, 19 Aug 2011 20:08:09 +0000 (15:08 -0500)]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
Mem: Put prefetcher notify call before packet is deleted.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Add VExpress_E support with PCIe to gem5
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Add support for Versatile Express boards
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Make GIC function that should only be called by GIC protected.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
StoreSet: Update stats for store-set clearing
Ali Saidi [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
ARM: Add support for DIV/SDIV instructions.
Ali Saidi [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
This patch improves performance by as much as 10% on some spec benchmarks.
Geoffrey Blake [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
Ali Saidi [Fri, 19 Aug 2011 20:08:06 +0000 (15:08 -0500)]
O3: Update stats for LSQ changes.
Mrinmoy Ghosh [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
LSQ: Add some better dprintfs for storeset predictor.
Mrinmoy Ghosh [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
the barrier was squashed instead of committed. This made all load insts
dependent on a non-existent barrier in-flight.
Thomas Grass [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
Stats: Add a sparse histogram stat object.
Giacomo Gabrielli [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
O3: Squash the violator and younger instructions instead not all insts.
Change the way instructions are squashed on memory ordering violations
to squash the violator and younger instructions, not all instructions
that are younger than the instruction they violated (no reason to throw
away valid work).
Geoffrey Blake [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
Prakash Ramrakhani [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Add per-processor interrupt support to GIC.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Fix a memory leak with the table walker.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
Prefetcher: Fix some memory leaks with the prefetcher.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: quiet what can be a very noise CLCD controller.
Gabe Black [Tue, 16 Aug 2011 09:47:15 +0000 (02:47 -0700)]
InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.
Gabe Black [Tue, 16 Aug 2011 09:46:57 +0000 (02:46 -0700)]
O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.
Nilay Vaish [Mon, 15 Aug 2011 17:56:47 +0000 (12:56 -0500)]
Ruby: Initialize some variables.
Gabe Black [Mon, 15 Aug 2011 01:34:17 +0000 (18:34 -0700)]
X86: Add an X86_FS o3 regression.