mesa.git
5 years agonir/xfb: Properly align 64-bit values
Jason Ekstrand [Tue, 12 Feb 2019 18:49:08 +0000 (12:49 -0600)]
nir/xfb: Properly align 64-bit values

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agocompiler/types: Add a contains_64bit helper
Jason Ekstrand [Tue, 12 Feb 2019 19:03:34 +0000 (13:03 -0600)]
compiler/types: Add a contains_64bit helper

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agofreedreno/a6xx: samplerBuffer fixes
Rob Clark [Wed, 20 Feb 2019 22:33:23 +0000 (17:33 -0500)]
freedreno/a6xx: samplerBuffer fixes

Use the 'UNK31' bit (which should probably be called 'BUFFER') for
samplerBuffer case, which increases the size of supported buffer
texture beyond 2^15 elements.

Also need to fix the 2nd coord injected to handle the tex instructions
that take integer coords.

Fixes dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
and similar

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3/a6xx: use ldib for ssbo reads
Rob Clark [Wed, 20 Feb 2019 15:31:15 +0000 (10:31 -0500)]
freedreno/ir3/a6xx: use ldib for ssbo reads

... instead of isam.  It seems like when using isam, plus atomics, we
can have the problem of old data being in the texture cache.  Plus this
way we don't have to load a component at a time.

Note that blob still seems to use isam in some cases.  I suppose it might
be preferable in the case of loading a single component, when atomics
are not in the picture (or that the ssbo does not need to otherwise be
coherent).

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: sync instr/disasm and add ldib encoding
Rob Clark [Wed, 20 Feb 2019 15:21:18 +0000 (10:21 -0500)]
freedreno/ir3: sync instr/disasm and add ldib encoding

Resync disasm and instr header from envytools, and add ldib encoding.
This replaces an opcode from a3xx which was never seen in practice,
since that seemed easier than dealing with the same opc # meaning a
different thing on a6xx.  (Not really sure if 'sti' was actually a
real thing, I think it was only seen in fuzzing.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3/a6xx: fix load_ssbo barrier type.
Rob Clark [Tue, 19 Feb 2019 19:44:10 +0000 (14:44 -0500)]
freedreno/ir3/a6xx: fix load_ssbo barrier type.

Silly copy/pasta bug, since load_image is actually the same instruction
but different barrier class.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: rename put_dst()
Rob Clark [Tue, 19 Feb 2019 18:32:25 +0000 (13:32 -0500)]
freedreno/ir3: rename put_dst()

This was overlooked when it moved to ir3_context.c and ceased to be
static..

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: fix crash w/ masked non-SSA dst
Rob Clark [Tue, 19 Feb 2019 18:25:02 +0000 (13:25 -0500)]
freedreno: fix crash w/ masked non-SSA dst

Fixes
dEQP-GLES3.functional.shaders.indexing.varying_array.vec3_dynamic_write_dynamic_loop_read
regression.

Fixes: c1a27ba9baf freedreno/ir3: HIGH reg w/a for a6xx
Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: 3d and cube image fixes
Rob Clark [Tue, 19 Feb 2019 13:51:30 +0000 (08:51 -0500)]
freedreno/a6xx: 3d and cube image fixes

Fixes dEQP-GLES31.functional.image_load_store.{3d,cube}.store.*
and a bunch more

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: fix crash in compile fail case
Rob Clark [Mon, 18 Feb 2019 18:54:26 +0000 (13:54 -0500)]
freedreno/ir3: fix crash in compile fail case

The variant will be NULL if RA failed.  Which isn't ideal, but at least
lets not segfault and bring down the rest of the dEQP run with us.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: fix legalize for vecN inputs
Rob Clark [Mon, 18 Feb 2019 18:15:54 +0000 (13:15 -0500)]
freedreno/ir3: fix legalize for vecN inputs

The wrmask is handled in regmask_get()/regmask_set(), but it wasn't
being propagated from SSA src to dst.  So for example, an SSBO read
value that is passed in as src2.y component to atomic op, wasn't
getting the (sy) flag set.  Causing lots of fail.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agoradv: Disable depth clamping even without EXT_depth_range_unrestricted.
Bas Nieuwenhuizen [Sat, 26 Jan 2019 02:18:05 +0000 (03:18 +0100)]
radv: Disable depth clamping even without EXT_depth_range_unrestricted.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: Implement VK_EXT_depth_clip_enable.
Bas Nieuwenhuizen [Sat, 26 Jan 2019 01:28:08 +0000 (02:28 +0100)]
radv: Implement VK_EXT_depth_clip_enable.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agonir: remove non-ssa support from nir_copy_prop()
Timothy Arceri [Wed, 20 Feb 2019 04:03:42 +0000 (15:03 +1100)]
nir: remove non-ssa support from nir_copy_prop()

Even in a very basic shader this reduces the time spent in
nir_copy_prop() by ~17%.

No shader-db changes for radeonsi NIR or i965.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: Handle clip+cull distances more generally as compact arrays.
Bas Nieuwenhuizen [Sat, 16 Feb 2019 01:24:14 +0000 (02:24 +0100)]
radv: Handle clip+cull distances more generally as compact arrays.

Needed for https://gitlab.freedesktop.org/mesa/mesa/merge_requests/248 .

That MR keeps the clip and cull arrays split.

So we have to handle
 - compact arrays with location_frac != 0
 - VARYING_SLOT_CLIP_DIST1

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agokmsro: Add the rest of the current set of tinydrm drivers.
Eric Anholt [Mon, 28 Jan 2019 17:51:41 +0000 (09:51 -0800)]
kmsro: Add the rest of the current set of tinydrm drivers.

While I haven't tested them all, given that they're all using the same
allocation paths and modifiers in the kernel they should be fine to use in
the same way.

v2: Rebase on other kmsro changes.
v3: Skip repeated '[with_gallium_kmsro,' in the meson build.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agoi965: re-emit index buffer state on a reset option change.
Andrii Simiklit [Fri, 25 Jan 2019 13:03:07 +0000 (15:03 +0200)]
i965: re-emit index buffer state on a reset option change.

Seems like we forget to update the index buffer (ib) status and
IndexedDrawCutIndexEnable or CutIndexEnable flag is left unchanged it
leads to ignoring of glEnable/glDisable functions for GL_PRIMITIVE_RESTART
in some cases. The index buffer (ib) status should be re-emmited after the
reset option change to avoid some unexpected behavior.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109451
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
5 years agonir: Don't forget if-uses in new nir_opt_dead_cf liveness check
Kenneth Graunke [Wed, 20 Feb 2019 07:17:28 +0000 (23:17 -0800)]
nir: Don't forget if-uses in new nir_opt_dead_cf liveness check

Commit 08bfd710a25c14df5f690cce9604617536d7c560. (nir/dead_cf: Stop
relying on liveness analysis) introduced a new check that iterated
through a SSA def's uses, to see if it's used.  But it only checked
normal uses, and not uses which are part of an 'if' condition.  This
led to it thinking more nodes were dead than possible.

Fixes Piglit's variable-indexing/tcs-output-array-float-index-wr test
(and related tests) with the out-of-tree Iris driver.

Fixes: 08bfd710a25 nir/dead_cf: Stop relying on liveness analysis
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agofreedreno/a6xx: Support MSAA resolve blits on blitter
Kristian H. Kristensen [Fri, 15 Feb 2019 07:37:01 +0000 (23:37 -0800)]
freedreno/a6xx: Support MSAA resolve blits on blitter

This gets stencil and depth resolves working properly.

Fixes:

  dEQP-GLES3.functional.fbo.msaa.2_samples.depth32f_stencil8
  dEQP-GLES3.functional.fbo.msaa.2_samples.depth24_stencil8
  dEQP-GLES3.functional.fbo.msaa.4_samples.depth32f_stencil8
  dEQP-GLES3.functional.fbo.msaa.4_samples.depth24_stencil8
  dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_color
  dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_color

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Copy stencil as R8_UINT
Kristian H. Kristensen [Fri, 15 Feb 2019 07:34:09 +0000 (23:34 -0800)]
freedreno/a6xx: Copy stencil as R8_UINT

Blitter does support it after all. Previous attempt to use R8_UINT
failed because we overwrote the a6xx format in emit_blit_texture(),
but some of the later setup still looked at the gallium format.

If we overwrite it in the pipe_blit_info before we even call into
emit_blit_texture() it works properly.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno: Update headers
Kristian H. Kristensen [Fri, 15 Feb 2019 07:33:16 +0000 (23:33 -0800)]
freedreno: Update headers

Add support for multisampled sources for the blitter.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agoanv: use anv_shader_bin_write_to_blob()'s return value
Eric Engestrom [Wed, 20 Feb 2019 11:09:46 +0000 (11:09 +0000)]
anv: use anv_shader_bin_write_to_blob()'s return value

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: drop unused imports
Eric Engestrom [Wed, 20 Feb 2019 10:34:41 +0000 (10:34 +0000)]
anv: drop unused imports

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: make sure the extensions stay sorted
Eric Engestrom [Wed, 20 Feb 2019 10:34:24 +0000 (10:34 +0000)]
anv: make sure the extensions stay sorted

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: sort vendors extensions after KHR and EXT
Eric Engestrom [Wed, 20 Feb 2019 10:33:51 +0000 (10:33 +0000)]
anv: sort vendors extensions after KHR and EXT

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: sort extensions alphabetically
Eric Engestrom [Wed, 20 Feb 2019 10:33:26 +0000 (10:33 +0000)]
anv: sort extensions alphabetically

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: anv: refactor error handling in anv_shader_bin_write_to_blob()
Tapani Pälli [Thu, 14 Feb 2019 08:12:49 +0000 (10:12 +0200)]
anv: anv: refactor error handling in anv_shader_bin_write_to_blob()

v2: blob manages error state internally, just return
    true if errors did not occur (Jason)

CID: 1442546
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agowayland/egl: Ensure EGL surface is resized on DRI update_buffers()
Carlos Garnacho [Tue, 20 Nov 2018 17:06:38 +0000 (18:06 +0100)]
wayland/egl: Ensure EGL surface is resized on DRI update_buffers()

Fullscreening and unfullscreening a totem window while playing a video
sometimes results in the video subsurface not changing size along. This
is also reproducible with epiphany.

If a surface gets resized while we have an active back buffer for it, the
resized dimensions won't get neither immediately applied on the resize
callback, nor correctly synchronized on update_buffers(), as the
(now stale) surface size and currently attached buffer size still do match.

There's actually 2 things to synchronize here, first the surface query
size might not be updated yet to the wl_egl_window's (i.e. resize_callback
happened while there is a back buffer), and second the wayland buffers
would need dropping if new surface size differs with the currently attached
buffer. These are done in separate steps now.

https://bugzilla.redhat.com/show_bug.cgi?id=1650929
https://bugs.freedesktop.org/show_bug.cgi?id=109594

Fixes: a9fb331ea7d ("wayland/egl: update surface size on window resize")
Signed-off-by: Carlos Garnacho <carlosg@gnome.org>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Bastien Nocera <hadess@hadess.net>
Tested-by: Denys Kostin <denys.kostin@globallogic.com>
5 years agoanv: implement VK_EXT_depth_clip_enable
Lionel Landwerlin [Mon, 14 Jan 2019 18:06:33 +0000 (18:06 +0000)]
anv: implement VK_EXT_depth_clip_enable

A new extension allowing the user to explictly specify the clipping
behavior.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agovulkan: Update the XML and headers to 1.1.101
Lionel Landwerlin [Mon, 14 Jan 2019 16:19:53 +0000 (10:19 -0600)]
vulkan: Update the XML and headers to 1.1.101

5 years agoisl: remove the cache line size alignment requirement
Samuel Iglesias Gonsálvez [Fri, 15 Feb 2019 08:07:29 +0000 (09:07 +0100)]
isl: remove the cache line size alignment requirement

The cacheline size was a requirement for using the BLT engine, which
we don't use anymore except for a few things on old HW, so we drop it.

Fixes CTS's CL#3500 test:

dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: Clean up a bunch of compiler warnings.
Bas Nieuwenhuizen [Wed, 20 Feb 2019 00:02:51 +0000 (01:02 +0100)]
radv: Clean up a bunch of compiler warnings.

Random unused vars.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradv: Sync ETC2 whitelisted devices.
Bas Nieuwenhuizen [Wed, 20 Feb 2019 01:19:42 +0000 (02:19 +0100)]
radv: Sync ETC2 whitelisted devices.

Fixes: 4bb6c49375e "radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9."
Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agost/nir: use NIR for asm programs
Timothy Arceri [Wed, 9 May 2018 04:06:43 +0000 (14:06 +1000)]
st/nir: use NIR for asm programs

This uses prog_to_nir to translate ARB assembly programs to NIR.

Co-authored by Tim Arceri, Dave Airlie, and Ken Graunke:

 - [Tim Arceri]: original patch
 - [Dave Airlie]: fix crashes with parameter names
 - [Ken Graunke]:
   - Rebase on SCALAR_ISA cap, lower wpos_ytransform too.
   - Rebase on streamout fixes.
   - Lower system values for fragcoord support.
   - Don't try to use prog_to_nir for ATI_fragment_shader programs.
   - Create TGSI for fixed-function or ARB vertex shaders even if the
     driver prefers NIR, so we can create draw module shaders for
     feedback/select emulation, which rely on TGSI.

Tested on:
- iris (Intel Skylake/Kabylake): Piglit & GL CTS - Ken Graunke
- radeonsi (AMD Vega 64): Piglit - Ken Graunke
- vc4/v3d - Piglit - Eric Anholt
- freedreno - dEQP - Kristian Høgsberg

Fixes lit_degenerate_case on vc4 and v3d, and vp-address-01,
vp-arl-constant-array-huge-offset-neg, and vp-arl-neg-array on v3d.
No Piglit regressions on radeonsi; no dEQP regressions on freedreno.

Acked-by: Eric Anholt <eric@anholt.net>
Tested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agost/mesa: Copy VP TGSI tokens if they exist, even for NIR shaders.
Kenneth Graunke [Fri, 15 Feb 2019 08:00:39 +0000 (00:00 -0800)]
st/mesa: Copy VP TGSI tokens if they exist, even for NIR shaders.

Even if the driver wants to use NIR shaders, we may need to have TGSI
tokens for creating draw module vertex shaders for the feedback/select
render modes.

So...if the st_vertex_program has any TGSI...copy it to the variant.

Acked-by: Eric Anholt <eric@anholt.net>
Tested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi: Go back to using llvm.pow intrinsic for nir_op_fpow
Kenneth Graunke [Fri, 15 Feb 2019 19:00:39 +0000 (11:00 -0800)]
radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpow

ARB_vertex_program and ARB_fragment_program define 0^0 = 1 (while GLSL
leaves it undefined).  Performing fpow lowering in NIR would break this
behavior, preventing us from using prog_to_nir.

According to llvm/lib/Target/AMDGPU/SIInstructions.td, POW_common
expands to <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>,
which presumably does a zero-wins multiply.

Lowering in NIR results in a non-legacy multiply, where:

   pow(0, 0) = 2^(log2(0) * 0)
             = 2^(-INF * 0)
             = 2^(-NaN)
             = -NaN

which isn't the desired result.

This reverts:
- commit d6b75392067712908bdc372f1007e085439bf9f5
  (ac/nir: remove emission of nir_op_fpow)
- commit 22430224fec31591432d4a3e65c6f457ba1c1653
  (radeonsi/nir: enable lowering of fpow)

and prevents a regression in gl-1.0-spot-light with AMD_DEBUG=nir
after enabling prog_to_nir in st/mesa later in this series.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi/nir: set shader_buffers_declared properly
Timothy Arceri [Tue, 12 Feb 2019 00:30:56 +0000 (11:30 +1100)]
radeonsi/nir: set shader_buffers_declared properly

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: set colors_read properly
Timothy Arceri [Mon, 11 Feb 2019 23:36:35 +0000 (10:36 +1100)]
radeonsi/nir: set colors_read properly

shader-db results for VEGA64:

Totals from affected shaders:
SGPRS: 1976 -> 1976 (0.00 %)
VGPRS: 1240 -> 1144 (-7.74 %)
Spilled SGPRs: 145 -> 145 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 34632 -> 34604 (-0.08 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 261 -> 285 (9.20 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: set input_usage_mask properly
Timothy Arceri [Tue, 19 Feb 2019 23:33:11 +0000 (10:33 +1100)]
radeonsi/nir: set input_usage_mask properly

shader-db results for VEGA64:

Totals from affected shaders:
SGPRS: 791528 -> 792616 (0.14 %)
VGPRS: 421624 -> 410784 (-2.57 %)
Spilled SGPRs: 1639 -> 1674 (2.14 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 16103516 -> 16063696 (-0.25 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 136307 -> 137830 (1.12 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: Use uniform location when calculating const_file_max.
Timur Kristóf [Tue, 19 Feb 2019 13:19:59 +0000 (14:19 +0100)]
radeonsi/nir: Use uniform location when calculating const_file_max.

The nine state tracker can produce NIR uniform variables
whose location is explicitly set. radeonsi did not take that
into account when calculating const_file_max, resulting in
rendering glitches. This patch fixes that.

Signed-Off-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agodrirc: Add sddm-greeter to adaptive_sync blacklist.
Mario Kleiner [Tue, 19 Feb 2019 03:00:09 +0000 (04:00 +0100)]
drirc: Add sddm-greeter to adaptive_sync blacklist.

This is the sddm login screen.

Fixes: a9c36dbf9c56 ("drirc: Initial blacklist for adaptive sync")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
5 years agodriconf: add Civ6Sub executable for Civilization 6
Marek Olšák [Tue, 19 Feb 2019 22:29:52 +0000 (17:29 -0500)]
driconf: add Civ6Sub executable for Civilization 6

I'm getting Civ6Sub instead of Civ6.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi: always enable NIR for Civilization 6 to fix corruption
Marek Olšák [Tue, 19 Feb 2019 22:21:20 +0000 (17:21 -0500)]
radeonsi: always enable NIR for Civilization 6 to fix corruption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi: add driconf option radeonsi_enable_nir
Marek Olšák [Tue, 19 Feb 2019 22:20:01 +0000 (17:20 -0500)]
radeonsi: add driconf option radeonsi_enable_nir

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agomesa: Align doubles to a 64-bit starting boundary, even if packing.
Kenneth Graunke [Wed, 16 Jan 2019 06:35:02 +0000 (22:35 -0800)]
mesa: Align doubles to a 64-bit starting boundary, even if packing.

In the new Intel Iris driver, I am using Tim's new packed uniform
storage system.  It works great, with one caveat: our scalar compiler
backend assumes that uniform offsets will be aligned to the underlying
data type.  For example, doubles must be 64-bit aligned, floats 32-bit,
half-floats 16-bit, and so on.  It does not need any other padding.

Currently, _mesa_add_parameter aligns everything to 32-bit offsets,
creating doubles that have an unaligned offset.  This patch alters
that code to align doubles to 64-bit offsets.

This may be slightly less optimal for drivers which can support full
packing, and allow reads from unaligned offsets at no penalty.  We could
make this extra alignment optional.  However, it only comes into play
when intermixing double and single precision uniforms.  Doubles are
already not too common, and intermixed values (floats then doubles)
is probably even less common.  At most, we burn a single 32-bit slot
to the alignment, which is not that expensive.  So, it doesn't seem
worthwhile to add the extra complexity.

Eventually, we'll likely want to update this code to allow half-float
values to be packed tighter than 32-bit offsets.  At that point, we'll
probably want to revisit what drivers ultimately want, and add options.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agocompiler: Make is_64bit(GL_*) helper more broadly available
Kenneth Graunke [Wed, 16 Jan 2019 08:03:39 +0000 (00:03 -0800)]
compiler: Make is_64bit(GL_*) helper more broadly available

I'd like to use this in the prog_parameter.c code, so I need to move it
into C, make it non-static, and so on.  This probably isn't the ideal
place for it, but I couldn't think of a better one.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agogitlab-ci: automatically run the CI on pushes to `ci/*` branches
Eric Engestrom [Tue, 19 Feb 2019 13:09:11 +0000 (13:09 +0000)]
gitlab-ci: automatically run the CI on pushes to `ci/*` branches

Last commit limited the CI to master and MRs, but to avoid having to
manually trigger CI runs, let's add a 3rd, automatic way: by pushing to
a branch named `ci/*` (or `ci-*` or just `ci`) (which you can delete
afterwards, the pipeline results will remain).

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agogitlab-ci: limit the automatic CI to master and MRs
Eric Engestrom [Mon, 18 Feb 2019 19:01:28 +0000 (19:01 +0000)]
gitlab-ci: limit the automatic CI to master and MRs

Runs on random other branches (stables RCs, personal forks) can still be
triggered manually via the web interface, or an app using the API.

This should massively help with the current voracious state of our CI.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agotegra/autotools: add missing libdrm cflags
Eric Engestrom [Tue, 19 Feb 2019 11:18:07 +0000 (11:18 +0000)]
tegra/autotools: add missing libdrm cflags

Fixes: f1374805a86d0d506557 "drm-uapi: use local files, not system libdrm"
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109647
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agotegra/meson: add missing dep_libdrm
Eric Engestrom [Tue, 19 Feb 2019 10:57:58 +0000 (10:57 +0000)]
tegra/meson: add missing dep_libdrm

Fixes: f1374805a86d0d506557 "drm-uapi: use local files, not system libdrm"
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109645
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoac/nir: implement half-float nir_op_ldexp
Rhys Perry [Thu, 6 Dec 2018 14:36:56 +0000 (14:36 +0000)]
ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement half-float nir_op_frsq
Rhys Perry [Thu, 6 Dec 2018 14:35:23 +0000 (14:35 +0000)]
ac/nir: implement half-float nir_op_frsq

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement half-float nir_op_frcp
Rhys Perry [Thu, 6 Dec 2018 14:33:21 +0000 (14:33 +0000)]
ac/nir: implement half-float nir_op_frcp

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_fdiv support 16-bit floats
Rhys Perry [Thu, 6 Dec 2018 14:22:17 +0000 (14:22 +0000)]
ac/nir: make ac_build_fdiv support 16-bit floats

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_isign work on all bit sizes
Rhys Perry [Thu, 6 Dec 2018 14:27:01 +0000 (14:27 +0000)]
ac/nir: make ac_build_isign work on all bit sizes

v2: don't use ac_get_zero(), ac_get_one() and ac_int_of_size()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_clamp work on all bit sizes
Rhys Perry [Thu, 6 Dec 2018 14:23:31 +0000 (14:23 +0000)]
ac/nir: make ac_build_clamp work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef()
v3: rename "intr" to "name"

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: fix 64-bit nir_op_f2f16_rtz
Rhys Perry [Thu, 6 Dec 2018 15:00:21 +0000 (15:00 +0000)]
ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement 8-bit nir_load_const_instr
Rhys Perry [Thu, 6 Dec 2018 14:41:11 +0000 (14:41 +0000)]
ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: ensure export arguments are always float
Rhys Perry [Thu, 6 Dec 2018 12:11:00 +0000 (12:11 +0000)]
radv: ensure export arguments are always float

So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.

This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
tests

Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: bitcast 16-bit outputs to integers
Rhys Perry [Thu, 6 Dec 2018 12:10:41 +0000 (12:10 +0000)]
radv: bitcast 16-bit outputs to integers

16-bit outputs are stored as 16-bit floats in the outputs array, so they
have to be bitcast.

Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agogitlab-ci: use ccache to speed up builds
Eric Engestrom [Tue, 12 Feb 2019 16:59:27 +0000 (16:59 +0000)]
gitlab-ci: use ccache to speed up builds

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agov3d: Move i2b and f2b support into emit_comparison.
Eric Anholt [Tue, 19 Feb 2019 02:15:59 +0000 (18:15 -0800)]
v3d: Move i2b and f2b support into emit_comparison.

This lets us save a resolve to NIR true/false for ifs and discard_if.  No
change in shader-db.

5 years agov3d: Emit a simpler negate for the iabs implementation.
Eric Anholt [Tue, 19 Feb 2019 02:13:09 +0000 (18:13 -0800)]
v3d: Emit a simpler negate for the iabs implementation.

One program affected in my shader-db.

instructions in affected programs: 110 -> 108 (-1.82%)

5 years agov3d: Delay emitting ldvpm on V3D 4.x until it's actually used.
Eric Anholt [Fri, 15 Feb 2019 05:11:20 +0000 (21:11 -0800)]
v3d: Delay emitting ldvpm on V3D 4.x until it's actually used.

For V3D 3.x, we emitted the ldvpms all at the top so that we didn't need
to do VPM setup when the load_inputs are out of order.  For V3D 4.x, we
can reduce register pressure by delaying our loads until they're actually
needed.  This also avoids a bunch of silly MOVs in the pre-opt VIR dump.

total instructions in shared programs: 6421415 -> 6419933 (-0.02%)
total uniforms in shared programs: 2393139 -> 2393140 (<.01%)
total threads in shared programs: 153864 -> 153906 (0.03%)

5 years agov3d: Stop tracking num_inputs for VPM loads.
Eric Anholt [Fri, 15 Feb 2019 05:01:05 +0000 (21:01 -0800)]
v3d: Stop tracking num_inputs for VPM loads.

It's unused in the VS (since we need vattr_sizes[] anyway), so move it to
FS prog data.

5 years agov3d: Add a function to describe what the c->execute.file check means.
Eric Anholt [Thu, 14 Feb 2019 17:34:33 +0000 (09:34 -0800)]
v3d: Add a function to describe what the c->execute.file check means.

This is what pointed out that we were misusing the check for last_thrsw in
the previous commit.

5 years agov3d: Fix the check for "is the last thrsw inside control flow"
Eric Anholt [Thu, 14 Feb 2019 17:42:38 +0000 (09:42 -0800)]
v3d: Fix the check for "is the last thrsw inside control flow"

The execute.file check used to be good enough, until I stopped setting up
the execute mask for uniform ifs.

No known tests fixed, noticed while doing a refactor.

Fixes: 080506057310 ("v3d: Handle dynamically uniform IF statements with uniform control flow.")
5 years agov3d: Fix f2b32 behavior.
Eric Anholt [Wed, 13 Feb 2019 20:21:01 +0000 (12:21 -0800)]
v3d: Fix f2b32 behavior.

Now that we don't have the vir_PF() magic, it's obvious that we were doing
the wrong thing for f2b32 by allowing -0.0 to produce true instead of
false.

5 years agov3d: Kill off vir_PF(), which is hard to use right.
Eric Anholt [Wed, 13 Feb 2019 20:09:02 +0000 (12:09 -0800)]
v3d: Kill off vir_PF(), which is hard to use right.

You were allowed to pass in any old temp so that you could hopefully fold
the PF up into the def of the temp.  If we couldn't find one, it
implicitly generated a MOV(nop, reg).  However, that PF could have
different behavior depending on whether the def being folded into was a
float or int opcode, which the caller doesn't necessarily control.

Due to the fragility of the function, just switch all callers over to
vir_set_pf().  This also encourages the callers to use a _dest call for
the inst they're putting the PF on, eliminating a bunch of temps in the
pre-optimization VIR.

shader-db says the change is in the noise:

total instructions in shared programs: 6226247 -> 6227184 (0.02%)
instructions in affected programs: 851068 -> 852005 (0.11%)

5 years agov3d: Do bool-to-cond for discard_if as well.
Eric Anholt [Wed, 13 Feb 2019 21:42:41 +0000 (13:42 -0800)]
v3d: Do bool-to-cond for discard_if as well.

Turns this minimal conditional discard (glsl-fs-discard-01.shader_test):

0x3de0b086c5fe9000 fcmp.pushn  -, r1, r5; mov  r2, 0
0x3dec3086bbfc001f nop                  ; mov.ifa  r2, -1
0x3c047186bbe80000 nop                  ; mov.pushz  -, r2
0x3dea3186ba837000 setmsf.ifna  -, 0    ; nop

into:

0x3c00b186c582a000 fcmp.pushn  -, r2, r5; nop
0x3de83186ba837000 setmsf.ifa  -, 0     ; nop

total instructions in shared programs: 6229820 -> 6226247 (-0.06%)

5 years agov3d: Refactor bcsel and if condition handling.
Eric Anholt [Wed, 13 Feb 2019 20:39:08 +0000 (12:39 -0800)]
v3d: Refactor bcsel and if condition handling.

Both were doing the same thing to try to get a condition to predicate on.
Noticed when I wanted to do this for discard_if as well.

No change in shader-db.

5 years agov3d: Add a helper function for getting a nop register.
Eric Anholt [Wed, 13 Feb 2019 19:59:10 +0000 (11:59 -0800)]
v3d: Add a helper function for getting a nop register.

Just a little refactor to explain what's going on with QFILE_NULL.

5 years agov3d: Drop our hand-lowered nir_op_ffract.
Eric Anholt [Wed, 13 Feb 2019 19:22:07 +0000 (11:22 -0800)]
v3d: Drop our hand-lowered nir_op_ffract.

The NIR lowering works fine, though it causes some slight noise due to
what looks like choices about propagating constants up multiply chains
changing.

total instructions in shared programs: 6229671 -> 6229820 (<.01%)
total uniforms in shared programs: 2312171 -> 2312324 (<.01%)

5 years agov3d: Drop a perf note about merging unpack_half_*, which has been implemented.
Eric Anholt [Wed, 6 Feb 2019 21:19:06 +0000 (13:19 -0800)]
v3d: Drop a perf note about merging unpack_half_*, which has been implemented.

This is handled with copy-propagation now.

5 years agov3d: Fix incorrect flagging of ldtmu as writing r4 on v3d 4.x.
Eric Anholt [Tue, 5 Feb 2019 21:14:12 +0000 (13:14 -0800)]
v3d: Fix incorrect flagging of ldtmu as writing r4 on v3d 4.x.

Fixes some stalls in 3DMMES's main vertex shader.

total instructions in shared programs: 6280751 -> 6211270 (-1.11%)
instructions in affected programs: 2935050 -> 2865569 (-2.37%)

5 years agov3d: Use the early_fragment_tests flag for the shader's disable-EZ field.
Eric Anholt [Tue, 12 Feb 2019 22:39:40 +0000 (14:39 -0800)]
v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.

Apparently we need disable-EZ flagged, not just "does Z writes".

Fixes
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
on 7278, even though it passed in simulation.

Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 051a41d3d56e ("v3d: Add support for the early_fragment_tests flag.")
5 years agov3d: Sync indirect draws on the last rendering.
Eric Anholt [Fri, 8 Feb 2019 18:41:25 +0000 (10:41 -0800)]
v3d: Sync indirect draws on the last rendering.

Fixes intermittent fails in
dEQP-GLES31.functional.draw_indirect.compute_interop.separate.drawelements_compute_cmd_and_data_and_indices
and others (particularly when run as part of a CTS run)

5 years agov3d: Clear the GMP on initialization of the simulator.
Eric Anholt [Thu, 31 Jan 2019 00:22:02 +0000 (16:22 -0800)]
v3d: Clear the GMP on initialization of the simulator.

Otherwise, we might have pages accessible that shouldn't be and miss out
on errors.  This is unlikely for most tests since v3d_hw_get_mem() is big
enough that it'll be a freshly zeroed mmap, but if screens are destroyed
and recreated then we'd be reusing the old v3d_hw_get_mem() contents.

5 years agodocs: update calendar, add news item and link release notes for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:38:14 +0000 (18:38 +0000)]
docs: update calendar, add news item and link release notes for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
5 years agodocs: add sha256 checksums for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:33:16 +0000 (18:33 +0000)]
docs: add sha256 checksums for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit bfb5bdaa97272537567cdf1e6caf1c7db9f28aba)

5 years agodocs: add release notes for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:23:55 +0000 (18:23 +0000)]
docs: add release notes for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b26488deadc3a8221d558a323dbe81dcf09115ab)

5 years agoi965: always enable EXT_float_blend
Ilia Mirkin [Wed, 13 Feb 2019 03:35:47 +0000 (22:35 -0500)]
i965: always enable EXT_float_blend

From the table in isl_format.c, it appears that all generations
support blending on 32-bit float surfaces.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agost/mesa: enable GL_EXT_float_blend when possible
Ilia Mirkin [Wed, 13 Feb 2019 03:34:25 +0000 (22:34 -0500)]
st/mesa: enable GL_EXT_float_blend when possible

If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip
EXT_float_blend on (which will affect ES3 contexts).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agomesa: add explicit enable for EXT_float_blend, and error condition
Ilia Mirkin [Wed, 13 Feb 2019 02:32:27 +0000 (21:32 -0500)]
mesa: add explicit enable for EXT_float_blend, and error condition

If EXT_float_blend is not supported, error out on blending of FP32
attachments in an ES2 context.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: fix writing the alpha channel of MRT0 when alpha coverage is enabled
Samuel Pitoiset [Mon, 18 Feb 2019 16:42:10 +0000 (17:42 +0100)]
radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled

This version is better and safer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agofreedreno/ir3: handle quirky atomic dst for a6xx
Rob Clark [Mon, 18 Feb 2019 16:15:52 +0000 (11:15 -0500)]
freedreno/ir3: handle quirky atomic dst for a6xx

The new encoding returns a value via the 2nd src.  The legalize pass
needs to be aware of this to set the correct needs_sy flag, otherwise we
can, in cases where the atomic dst is not used, overwrite the register
that hardware will asynchronously load result into without (sy) flag, so
it gets clobbered by the atomic result.

This fixes a whole lot of rando ssbo+atomic fails, like
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.highp_vec4.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: fix helper_invocation (sampler mask/id)
Rob Clark [Mon, 18 Feb 2019 15:34:06 +0000 (10:34 -0500)]
freedreno/a6xx: fix helper_invocation (sampler mask/id)

Since gl_HelperInvocation is lowered to:

  !((1 << sample_id) & sample_mask_in))

Not setting these enable bits was causing it be broken.  (And probably a
bunch of other stuff too.)

Fixes dEQP-GLES31.functional.shaders.helper_invocation.*

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agoradv: remove unused variable in gather_push_constant_info()
Samuel Pitoiset [Mon, 18 Feb 2019 12:30:16 +0000 (13:30 +0100)]
radv: remove unused variable in gather_push_constant_info()

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoi965: scale factor changes should trigger recompile
Lionel Landwerlin [Fri, 15 Feb 2019 13:47:48 +0000 (13:47 +0000)]
i965: scale factor changes should trigger recompile

Found by inspection.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3da858a6b990c5 ("intel/compiler: add scale_factors to sampler_prog_key_data")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
5 years agoradv: write the alpha channel of MRT0 when alpha coverage is enabled
Samuel Pitoiset [Fri, 15 Feb 2019 17:02:52 +0000 (18:02 +0100)]
radv: write the alpha channel of MRT0 when alpha coverage is enabled

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: use new LLVM 8 intrinsic when loading 16-bit values
Samuel Pitoiset [Thu, 14 Feb 2019 13:42:30 +0000 (14:42 +0100)]
ac: use new LLVM 8 intrinsic when loading 16-bit values

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add ac_build_llvm8_tbuffer_load() helper
Samuel Pitoiset [Thu, 14 Feb 2019 13:42:29 +0000 (14:42 +0100)]
ac: add ac_build_llvm8_tbuffer_load() helper

It uses the new LLVM intrinsics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agomesa: return NULL if we exceed MaxColorAttachments in get_fb_attachment
Tapani Pälli [Thu, 14 Feb 2019 07:02:31 +0000 (09:02 +0200)]
mesa: return NULL if we exceed MaxColorAttachments in get_fb_attachment

This fixes invalid access to Attachment array which would occur if caller
would exceed MaxColorAttachments. In practice this should not ever happen
because DiscardFramebufferEXT specifies only GL_COLOR_ATTACHMENT0 to be
valid and InvalidateFramebuffer will error out before but this should
make coverity happy.

v2: const, remove _EXT (Ian)

CID: 1442559
Fixes: 0c42b5f3cb9 "mesa: wire up InvalidateFramebuffer"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agopanfrost: Fix clipping region
Alyssa Rosenzweig [Sat, 16 Feb 2019 01:04:07 +0000 (01:04 +0000)]
panfrost: Fix clipping region

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Preserve w sign in perspective division
Alyssa Rosenzweig [Fri, 15 Feb 2019 06:38:23 +0000 (06:38 +0000)]
panfrost: Preserve w sign in perspective division

This fixes issues where polygons that should be culled (due to negative
w, for instance) may not be.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Cleanup mali_viewport (clipping) code
Alyssa Rosenzweig [Fri, 15 Feb 2019 06:45:07 +0000 (06:45 +0000)]
panfrost: Cleanup mali_viewport (clipping) code

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Swap order of tiled texture (de)alloc
Alyssa Rosenzweig [Fri, 15 Feb 2019 00:28:46 +0000 (00:28 +0000)]
panfrost: Swap order of tiled texture (de)alloc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Free imported BOs
Alyssa Rosenzweig [Fri, 15 Feb 2019 00:15:14 +0000 (00:15 +0000)]
panfrost: Free imported BOs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Fix various leaks unmapping resources
Alyssa Rosenzweig [Thu, 14 Feb 2019 06:17:19 +0000 (06:17 +0000)]
panfrost: Fix various leaks unmapping resources

v2: Don't check for NULL before free()

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agonir: Don't reassociate add/mul chains containing only constants
Kenneth Graunke [Fri, 15 Feb 2019 22:52:20 +0000 (14:52 -0800)]
nir: Don't reassociate add/mul chains containing only constants

The idea here is to reassociate a * (b * c) into (a * c) * b, when
b is a non-constant value, but a and c are constants, allowing them
to be combined.

But nothing was enforcing that 'b' must be non-constant, which meant
that running opt_algebraic in a loop would never terminate if the IR
contained non-folded constant expressions like 256 * 0.5 * 2.  Normally,
we call constant folding in such a loop too, but IMO it's better for
nir_opt_algebraic to be robust and not rely on that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109581
Fixes: 32e266a9a58 i965: Compile fp64 funcs only if we do not have 64-bit hardware support
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>