bugzilla-daemon [Sat, 9 May 2020 13:13:41 +0000 (13:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:08:52 +0000 (14:08 +0100)]
[libre-riscv-dev] insights about the selection of the design and architecture
Luke Kenneth Casson Leighton [Sat, 9 May 2020 11:33:05 +0000 (12:33 +0100)]
[libre-riscv-dev] daily kan-ban update 09may2020
Luke Kenneth Casson Leighton [Sat, 9 May 2020 10:02:13 +0000 (11:02 +0100)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Luke Kenneth Casson Leighton [Sat, 9 May 2020 09:59:13 +0000 (10:59 +0100)]
[libre-riscv-dev] pinmux to generate interfaces (with no pinmux)
Staf Verhaegen [Sat, 9 May 2020 09:12:40 +0000 (11:12 +0200)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Luke Kenneth Casson Leighton [Sat, 9 May 2020 08:25:32 +0000 (09:25 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Luke Kenneth Casson Leighton [Sat, 9 May 2020 07:51:48 +0000 (08:51 +0100)]
Re: [libre-riscv-dev] spinlocks considered harmful
Yehowshua [Sat, 9 May 2020 00:31:29 +0000 (20:31 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Jacob Lifshay [Fri, 8 May 2020 23:21:48 +0000 (16:21 -0700)]
Re: [libre-riscv-dev] LD/ST CompUnit "working"
Jacob Lifshay [Fri, 8 May 2020 23:20:27 +0000 (16:20 -0700)]
[libre-riscv-dev] spinlocks considered harmful
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:18:32 +0000 (00:18 +0100)]
[libre-riscv-dev] LD/ST CompUnit "working"
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:11:26 +0000 (00:11 +0100)]
Re: [libre-riscv-dev] note on memory operation requirements for linux
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:09:50 +0000 (00:09 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
bugzilla-daemon [Fri, 8 May 2020 23:08:27 +0000 (23:08 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:48:49 +0000 (23:48 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:45:26 +0000 (23:45 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:41:03 +0000 (23:41 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Jacob Lifshay [Fri, 8 May 2020 22:34:03 +0000 (15:34 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:23:18 +0000 (23:23 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:19:00 +0000 (23:19 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Jacob Lifshay [Fri, 8 May 2020 21:39:11 +0000 (14:39 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:47:24 +0000 (21:47 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Michael Nolan [Fri, 8 May 2020 20:47:18 +0000 (16:47 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Alain D D Williams [Fri, 8 May 2020 20:38:17 +0000 (21:38 +0100)]
[libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:35:17 +0000 (21:35 +0100)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 20:27:28 +0000 (16:27 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Jacob Lifshay [Fri, 8 May 2020 19:15:25 +0000 (12:15 -0700)]
[libre-riscv-dev] note on memory operation requirements for linux
Staf Verhaegen [Fri, 8 May 2020 19:08:50 +0000 (21:08 +0200)]
Re: [libre-riscv-dev] minimum viable ASIC
bugzilla-daemon [Fri, 8 May 2020 18:38:56 +0000 (18:38 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Staf Verhaegen [Fri, 8 May 2020 17:25:04 +0000 (19:25 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Staf Verhaegen [Fri, 8 May 2020 17:23:35 +0000 (19:23 +0200)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
bugzilla-daemon [Fri, 8 May 2020 17:10:44 +0000 (17:10 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 17:04:07 +0000 (17:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 16:55:52 +0000 (17:55 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
bugzilla-daemon [Fri, 8 May 2020 16:54:32 +0000 (16:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 16:48:11 +0000 (16:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Cole Poirier [Fri, 8 May 2020 16:01:57 +0000 (09:01 -0700)]
Re: [libre-riscv-dev] HDL_Workflow clarification
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:59:20 +0000 (16:59 +0100)]
Re: [libre-riscv-dev] HDL_Workflow clarification
Cole Poirier [Fri, 8 May 2020 15:42:33 +0000 (08:42 -0700)]
[libre-riscv-dev] HDL_Workflow clarification
bugzilla-daemon [Fri, 8 May 2020 15:40:50 +0000 (15:40 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:35:47 +0000 (15:35 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:32:54 +0000 (15:32 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:29:35 +0000 (15:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:29:05 +0000 (15:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:28:42 +0000 (15:28 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:28:21 +0000 (15:28 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:27:34 +0000 (16:27 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
whygee [Fri, 8 May 2020 15:27:06 +0000 (17:27 +0200)]
[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:25:55 +0000 (16:25 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Michael Nolan [Fri, 8 May 2020 15:21:57 +0000 (11:21 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
bugzilla-daemon [Fri, 8 May 2020 15:17:20 +0000 (15:17 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 15:17:00 +0000 (15:17 +0000)]
[libre-riscv-dev] [Bug 305] New: Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:16:12 +0000 (16:16 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:10:19 +0000 (16:10 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:03:55 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Yehowshua [Fri, 8 May 2020 15:00:30 +0000 (11:00 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Luke Kenneth Casson Leighton [Fri, 8 May 2020 14:59:01 +0000 (15:59 +0100)]
Re: [libre-riscv-dev] minimum viable ASIC
bugzilla-daemon [Fri, 8 May 2020 14:37:52 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Fri, 8 May 2020 14:36:36 +0000 (14:36 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
Yehowshua [Fri, 8 May 2020 14:20:48 +0000 (10:20 -0400)]
[libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Michael N [Fri, 8 May 2020 14:03:17 +0000 (10:03 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Yehowshua [Fri, 8 May 2020 13:51:59 +0000 (09:51 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Michael Nolan [Fri, 8 May 2020 13:28:02 +0000 (09:28 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Yehowshua [Fri, 8 May 2020 12:59:44 +0000 (08:59 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 12:59:07 +0000 (08:59 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 12:50:12 +0000 (08:50 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 12:49:04 +0000 (08:49 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Luke Kenneth Casson Leighton [Fri, 8 May 2020 12:46:49 +0000 (13:46 +0100)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 12:43:58 +0000 (08:43 -0400)]
Re: [libre-riscv-dev] minimum viable ASIC
Luke Kenneth Casson Leighton [Fri, 8 May 2020 11:18:30 +0000 (12:18 +0100)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
bugzilla-daemon [Fri, 8 May 2020 11:15:06 +0000 (11:15 +0000)]
[libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC
Staf Verhaegen [Fri, 8 May 2020 11:10:52 +0000 (13:10 +0200)]
Re: [libre-riscv-dev] minimum viable ASIC
Staf Verhaegen [Fri, 8 May 2020 11:02:35 +0000 (13:02 +0200)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Luke Kenneth Casson Leighton [Fri, 8 May 2020 10:59:07 +0000 (11:59 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 10:56:32 +0000 (11:56 +0100)]
[libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 10:46:20 +0000 (11:46 +0100)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Luke Kenneth Casson Leighton [Fri, 8 May 2020 10:42:57 +0000 (11:42 +0100)]
Re: [libre-riscv-dev] minimum viable ASIC
Staf Verhaegen [Fri, 8 May 2020 10:29:45 +0000 (12:29 +0200)]
Re: [libre-riscv-dev] minimum viable ASIC
Luke Kenneth Casson Leighton [Fri, 8 May 2020 09:50:52 +0000 (10:50 +0100)]
[libre-riscv-dev] minimum viable ASIC
Luke Kenneth Casson Leighton [Fri, 8 May 2020 09:08:02 +0000 (10:08 +0100)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Yehowshua [Fri, 8 May 2020 08:51:09 +0000 (04:51 -0400)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Staf Verhaegen [Fri, 8 May 2020 08:41:02 +0000 (10:41 +0200)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Luke Kenneth Casson Leighton [Fri, 8 May 2020 02:36:03 +0000 (03:36 +0100)]
Re: [libre-riscv-dev] nMigen Hierachical Issues
Luke Kenneth Casson Leighton [Fri, 8 May 2020 02:26:11 +0000 (03:26 +0100)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Yehowshua [Fri, 8 May 2020 02:19:57 +0000 (22:19 -0400)]
[libre-riscv-dev] nMigen Hierachical Issues
Luke Kenneth Casson Leighton [Fri, 8 May 2020 00:40:17 +0000 (01:40 +0100)]
Re: [libre-riscv-dev] MMU + TLB idea
Michael Nolan [Thu, 7 May 2020 23:39:08 +0000 (19:39 -0400)]
[libre-riscv-dev] MMU + TLB idea
Yehowshua [Thu, 7 May 2020 23:28:18 +0000 (19:28 -0400)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Jacob Lifshay [Thu, 7 May 2020 23:23:52 +0000 (16:23 -0700)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Luke Kenneth Casson Leighton [Thu, 7 May 2020 19:02:30 +0000 (20:02 +0100)]
Re: [libre-riscv-dev] 4 Simulators?
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:55:05 +0000 (19:55 +0100)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:53:55 +0000 (19:53 +0100)]
Re: [libre-riscv-dev] 4 Simulators?
Tobias Platen [Thu, 7 May 2020 18:54:11 +0000 (20:54 +0200)]
Re: [libre-riscv-dev] 4 Simulators?
Tobias Platen [Thu, 7 May 2020 18:48:51 +0000 (20:48 +0200)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
Jacob Lifshay [Thu, 7 May 2020 18:46:54 +0000 (11:46 -0700)]
Re: [libre-riscv-dev] 4 Simulators?
Yehowshua [Thu, 7 May 2020 18:41:49 +0000 (14:41 -0400)]
Re: [libre-riscv-dev] 4 Simulators?
Jacob Lifshay [Thu, 7 May 2020 18:40:39 +0000 (11:40 -0700)]
Re: [libre-riscv-dev] 4 Simulators?
Yehowshua [Thu, 7 May 2020 18:30:07 +0000 (14:30 -0400)]
Re: [libre-riscv-dev] 4 Simulators?
Michael Nolan [Thu, 7 May 2020 18:25:14 +0000 (14:25 -0400)]
Re: [libre-riscv-dev] daily kan-ban 07may2020 update
projects / libre-riscv-dev.git / log