Mitch Hayenga [Wed, 3 Sep 2014 11:42:52 +0000 (07:42 -0400)]
arm: Make memory ops work on 64bit/128-bit quantities
Multiple instructions assume only 32-bit load operations are available,
this patch increases load sizes to 64-bit or 128-bit for many load pair and
load multiple instructions.
Curtis Dunham [Fri, 27 Jun 2014 17:29:00 +0000 (12:29 -0500)]
mem: write streaming support via WriteInvalidate promotion
Support full-block writes directly rather than requiring RMW:
* a cache line is allocated in the cache upon receipt of a
WriteInvalidateReq, not the WriteInvalidateResp.
* only top-level caches allocate the line; the others just pass
the request along and invalidate as necessary.
* to close a timing window between the *Req and the *Resp, a new
metadata bit tracks whether another cache has read a copy of
the new line before the writeback to memory.
Andreas Hansson [Wed, 3 Sep 2014 11:42:50 +0000 (07:42 -0400)]
mem: Fix a bug in the cache port flow control
This patch fixes a bug in the cache port where the retry flag was
reset too early, allowing new requests to arrive before the retry was
actually sent, but with the event already scheduled. This caused a
deadlock in the interactions with the O3 LSQ.
The patche fixes the underlying issue by shifting the resetting of the
flag to be done by the event that also calls sendRetry(). The patch
also tidies up the flow control in recvTimingReq and ensures that we
also check if we already have a retry outstanding.
Curtis Dunham [Tue, 13 May 2014 17:20:49 +0000 (12:20 -0500)]
cpu, mem: Make software prefetches non-blocking
Previously, they were treated so much like loads that they could stall
at the head of the ROB. Now they are always treated like L1 hits.
If they actually miss, a new request is created at the L1 and tracked
from the MSHRs there if necessary (i.e. if it didn't coalesce with
an existing outstanding load).
Curtis Dunham [Tue, 13 May 2014 17:20:48 +0000 (12:20 -0500)]
mem: Refactor assignment of Packet types
Put the packet type swizzling (that is currently done in a lot of places)
into a refineCommand() member function.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:46 +0000 (07:42 -0400)]
x86: Flag instructions that call suspend as IsQuiesce
The o3 cpu relies upon instructions that suspend a thread context being
flagged as "IsQuiesce". If they are not, unpredictable behavior can occur.
This patch fixes that for the x86 ISA.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:45 +0000 (07:42 -0400)]
cpu: Fix o3 drain bug
For X86, the o3 CPU would get stuck with the commit stage not being
drained if an interrupt arrived while drain was pending. isDrained()
makes sure that pcState.microPC() == 0, thus ensuring that we are at
an instruction boundary. However, when we take an interrupt we
execute:
pcState.upc(romMicroPC(entry));
pcState.nupc(romMicroPC(entry) + 1);
tc->pcState(pcState);
As a result, the MicroPC is no longer zero. This patch ensures the drain is
delayed until no interrupts are present. Once draining, non-synchronous
interrupts are deffered until after the switch.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:44 +0000 (07:42 -0400)]
arm: Fix v8 neon latency issue for loads/stores
Neon memory ops that operate on multiple registers currently have very poor
performance because of interleave/deinterleave micro-ops.
This patch marks the deinterleave/interleave micro-ops as "No_OpClass" such
that they take minumum cycles to execute and are never resource constrained.
Additionaly the micro-ops over-read registers. Although one form may need
to read up to 20 sources, not all do. This adds in new forms so false
dependencies are not modeled. Instructions read their minimum number of
sources.
Curtis Dunham [Tue, 29 Apr 2014 21:05:02 +0000 (16:05 -0500)]
arm: use condition code registers for ARM ISA
Analogous to
ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Andrew Bardsley [Wed, 3 Sep 2014 11:42:43 +0000 (07:42 -0400)]
arm: ISA X31 destination register fix
This patch substituted the zero register for X31 used as a
destination register. This prevents false dependencies based on
X31.
Andreas Hansson [Wed, 3 Sep 2014 11:42:41 +0000 (07:42 -0400)]
tests: Use O3_ARM_v7a config for full-system ARM regressions
This patch changes the CPU configuration used for the full-system ARM
regressions to increase the test coverage. Note that it is only the
core configuration, and not the caches etc.
Dam Sunwoo [Wed, 3 Sep 2014 11:42:41 +0000 (07:42 -0400)]
cpu: fix bimodal predictor to use correct global history reg
A small bug in the bimodal predictor caused significant degradation in
performance on some benchmarks. This was caused by using the wrong
globalHistoryReg during the update phase. This patches fixes the bug
and brings the performance to normal level.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:40 +0000 (07:42 -0400)]
arm: Mark v7 cbz instructions as direct branches
v7 cbz/cbnz instructions were improperly marked as indirect branches.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:39 +0000 (07:42 -0400)]
cpu: Fix cache blocked load behavior in o3 cpu
This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.
Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width). This patch also corrects that.
Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:38 +0000 (07:42 -0400)]
cpu: Fix o3 quiesce fetch bug
O3 is supposed to stop fetching instructions once a quiesce is encountered.
However due to a bug, it would continue fetching instructions from the current
fetch buffer. This is because of a break statment that only broke out of the
first of 2 nested loops. It should have broken out of both.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:37 +0000 (07:42 -0400)]
cpu: Fix SMT scheduling issue with the O3 cpu
The o3 cpu could attempt to schedule inactive threads under round-robin SMT
mode.
This is because it maintained an independent priority list of threads from the
active thread list. This priority list could be come stale once threads were
inactive, leading to the cpu trying to fetch/commit from inactive threads.
Additionally the fetch queue is now forcibly flushed of instrctuctions
from the de-scheduled thread.
Relevant output:
24557000: system.cpu: [tid:1]: Calling deactivate thread.
24557000: system.cpu: [tid:1]: Removing from active threads list
24557500: system.cpu:
FullO3CPU: Ticking main, FullO3CPU.
24557500: system.cpu.fetch: Running stage.
24557500: system.cpu.fetch: Attempting to fetch from [tid:1]
Mitch Hayenga [Wed, 3 Sep 2014 11:42:36 +0000 (07:42 -0400)]
cpu: Fix incorrect speculative branch predictor behavior
When a branch mispredicted gem5 would squash all history after and including
the mispredicted branch. However, the mispredicted branch is still speculative
and its history is required to rollback state if another, older, branch
mispredicts. This leads to things like RAS corruption.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:35 +0000 (07:42 -0400)]
cpu: Add a fetch queue to the o3 cpu
This patch adds a fetch queue that sits between fetch and decode to the
o3 cpu. This effectively decouples fetch from decode stalls allowing it
to be more aggressive, running futher ahead in the instruction stream.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:34 +0000 (07:42 -0400)]
cpu: Fix o3 front-end pipeline interlock behavior
The o3 pipeline interlock/stall logic is incorrect. o3 unnecessicarily stalled
fetch and decode due to later stages in the pipeline. In general, a stage
should usually only consider if it is stalled by the adjacent, downstream stage.
Forcing stalls due to later stages creates and results in bubbles in the
pipeline. Additionally, o3 stalled the entire frontend (fetch, decode, rename)
on a branch mispredict while the ROB is being serially walked to update the
RAT (robSquashing). Only should have stalled at rename.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:33 +0000 (07:42 -0400)]
cpu: Change writeback modeling for outstanding instructions
As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().
Mitch Hayenga [Wed, 3 Sep 2014 11:42:32 +0000 (07:42 -0400)]
arch: Properly guess OpClass from optional StaticInst flags
isa_parser.py guesses the OpClass if none were given based upon the StaticInst
flags. The existing code does not take into account optionally set flags.
This code hoists the setting of optional flags so OpClass is properly assigned.
Geoffrey Blake [Wed, 3 Sep 2014 11:42:31 +0000 (07:42 -0400)]
cache: Fix handling of LL/SC requests under contention
If a set of LL/SC requests contend on the same cache block we
can get into a situation where CPUs will deadlock if they expect
a failed SC to supply them data. This case happens where 3 or
more cores are contending for a cache block using LL/SC and the system
is configured where 2 cores are connected to a local bus and the
third is connected to a remote bus. If a core on the local bus
sends an SCUpgrade and the core on the remote bus sends and SCUpgrade
they will race to see who will win the SC access. In the meantime
if the other core appends a read to one of the SCUpgrades it will expect
to be supplied data by that SCUpgrade transaction. If it happens that
the SCUpgrade that was picked to supply the data is failed, it will
drop the appended request for data and never respond, leaving the requesting
core to deadlock. This patch makes all SC's behave as normal stores to
prevent this case but still makes sure to check whether it can perform
the update.
Curtis Dunham [Tue, 27 May 2014 16:00:56 +0000 (11:00 -0500)]
arm: support 16kb vm granules
Andreas Hansson [Wed, 3 Sep 2014 11:42:29 +0000 (07:42 -0400)]
mem: Add utility script to plot DRAM efficiency sweep
This patch adds basic functionality to quickly visualise the output
from the DRAM efficiency script. There are some unfortunate hacks
needed to communicate the needed information from one script to the
other, and we fall back on (ab)using the simout to do this.
As part of this patch we also trim the efficiency sweep to stop at 512
bytes as this should be sufficient for all forseeable DRAMs.
Andreas Hansson [Wed, 3 Sep 2014 11:42:28 +0000 (07:42 -0400)]
mem: Packet queue clean up
No change in functionality, just a bit of tidying up.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:27 +0000 (07:42 -0400)]
dev: Avoid invalid sized reads in PL390 with DPRINTF enabled
The first DPRINTF() in PL390::writeDistributor always read a uint32_t, though a
packet may have only been 1 or 2 bytes. This caused an assertion in
packet->get().
Andrew Bardsley [Wed, 3 Sep 2014 11:42:25 +0000 (07:42 -0400)]
sim: Fix checkpoint restore for Ticked
This patch makes restoring the 'lastStopped' value for Ticked-containing
objects (including MinorCPU) optional so that Ticked-containing objects
can be restored from non-Ticked-containing objects (such as AtomicSimpleCPU).
Andreas Sandberg [Wed, 3 Sep 2014 11:42:22 +0000 (07:42 -0400)]
arch, cpu: Factor out the ExecContext into a proper base class
We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.
The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.
Andreas Hansson [Wed, 3 Sep 2014 11:42:21 +0000 (07:42 -0400)]
arch: Cleanup unused ISA traits constants
This patch prunes unused values, and also unifies how the values are
defined (not using an enum for ALPHA), aligning the use of int vs Addr
etc.
The patch also removes the duplication of PageBytes/PageShift and
VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical
values and the latter has been removed.
Mitch Hayenga [Wed, 3 Sep 2014 11:42:20 +0000 (07:42 -0400)]
config: Change parsing of Addr so hex values work from scripts
When passed from a configuration script with a hexadecimal value (like
"0x80000000"), gem5 would error out. This is because it would call
"toMemorySize" which requires the argument to end with a size specifier (like
1MB, etc).
This modification makes it so raw hex values can be passed through Addr
parameters from the configuration scripts.
Andreas Hansson [Wed, 3 Sep 2014 11:42:19 +0000 (07:42 -0400)]
arm: Fix ExtMachInst hash operator underlying type
This patch fixes the hash operator used for ARM ExtMachInst, which
incorrectly was still using uint32_t. Instead of changing it to
uint64_t it is not using the underlying data type of the BitUnion.
Nilay Vaish [Mon, 1 Sep 2014 21:55:52 +0000 (16:55 -0500)]
stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
Nilay Vaish [Mon, 1 Sep 2014 21:55:50 +0000 (16:55 -0500)]
ruby: remove typedef of Index as int64
The Index type defined as typedef int64 does not really provide any help
since in most places we use primitive types instead of Index. Also, the name
Index is very generic that it does not merit being used as a typename.
Nilay Vaish [Mon, 1 Sep 2014 21:55:49 +0000 (16:55 -0500)]
x86: set op class of two fp instructions
This patch sets op class of two fp instructions: movfp and pop x87 stack
as IntAluOp since these instructions do not make use of the fp alu.
Nilay Vaish [Mon, 1 Sep 2014 21:55:48 +0000 (16:55 -0500)]
ruby: PerfectSwitch: moves code to a per vnet helper function
This patch moves code from the wakeup() function to a operateVnet().
The aim is to improve the readiblity of the code.
Nilay Vaish [Mon, 1 Sep 2014 21:55:47 +0000 (16:55 -0500)]
ruby: message buffers: significant changes
This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.
This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.
The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
Nilay Vaish [Mon, 1 Sep 2014 21:55:46 +0000 (16:55 -0500)]
build opts: add MI_example to NULL ISA
A later changeset changes the file src/python/swig/pyobject.cc to include
a header file that includes a header file generated at build time depending
on the PROTOCOL in use. Since NULL ISA was not specifying any protocol,
this resulted in compilation problems. Hence, the changeset.
Nilay Vaish [Mon, 1 Sep 2014 21:55:46 +0000 (16:55 -0500)]
mem: change the namespace Message to ProtoMessage
The namespace Message conflicts with the Message data type used extensively
in Ruby. Since Ruby is being moved to the same Master/Slave ports based
configuration style as the rest of gem5, this conflict needs to be resolved.
Hence, the namespace is being renamed to ProtoMessage.
Nilay Vaish [Mon, 1 Sep 2014 21:55:45 +0000 (16:55 -0500)]
ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a
state machine are specified in SLICC. The first change is that the data
member declarations will need to be separated by a semi-colon instead of a
comma. Secondly, the default value to be assigned would now use SLICC's
assignment operator i.e. ':='.
Nilay Vaish [Mon, 1 Sep 2014 21:55:44 +0000 (16:55 -0500)]
ruby: slicc: improve the grammar
This patch changes the grammar for SLICC so as to remove some of the
redundant / duplicate rules. In particular rules for object/variable
declaration and class member declaration have been unified. Similarly, the
rules for a general function and a class method have been unified.
One more change is in the priority of two rules. The first rule is on
declaring a function with all the params typed and named. The second rule is
on declaring a function with all the params only typed. Earlier the second
rule had a higher priority. Now the first rule has a higher priority.
Nilay Vaish [Mon, 1 Sep 2014 21:55:44 +0000 (16:55 -0500)]
ruby: mesi three level: slight naming changes.
Nilay Vaish [Mon, 1 Sep 2014 21:55:43 +0000 (16:55 -0500)]
ruby: slicc: donot prefix machine name to variables
This changeset does away with prefixing of member variables of state machines
with the identity of the machine itself.
Nilay Vaish [Mon, 1 Sep 2014 21:55:42 +0000 (16:55 -0500)]
ruby: remove unused toString() from AbstractController
Nilay Vaish [Mon, 1 Sep 2014 21:55:42 +0000 (16:55 -0500)]
ruby: network: move getNumNodes() to base class
All the implementations were doing the same things.
Nilay Vaish [Mon, 1 Sep 2014 21:55:41 +0000 (16:55 -0500)]
ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.
Nilay Vaish [Mon, 1 Sep 2014 21:55:40 +0000 (16:55 -0500)]
ruby: move files from ruby/system to ruby/structures
The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.
The directory ruby/systems has the glue code that holds these structures
together.
--HG--
rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh
rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc
rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh
rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc
rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh
rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh
rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc
rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh
rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py
rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc
rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh
rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc
rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh
rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py
rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh
rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc
rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh
rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py
rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc
rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh
rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh
rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh
rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc
rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh
rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh
rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc
rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh
rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py
rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc
rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh
rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh
rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc
rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh
rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc
rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh
rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py
rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc
rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
ruby: Fixes clock domains in configuration files
This patch fixes scripts related to ruby by adding the ruby clock domain.
Now the L1 controllers and the Sequencer shares the cpu clock domain,
while the rest of the components use the ruby clock domain.
Before this patch, running simulations with the cpu clock set at 2GHz or
1GHz will output the same time results and could distort power measurements.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Alexandru [Thu, 28 Aug 2014 15:11:44 +0000 (10:11 -0500)]
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
Alexandru [Tue, 1 Apr 2014 17:18:12 +0000 (12:18 -0500)]
mem: adding a multi-level page table class
This patch defines a multi-level page table class that stores the page table in
system memory, consistent with ISA specifications. In this way, cpu models that
use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page
table.
Nilay Vaish [Tue, 26 Aug 2014 19:41:23 +0000 (14:41 -0500)]
Added tag stable_2014_08_26 for changeset
cb2e6950956d
Andreas Hansson [Tue, 26 Aug 2014 14:14:38 +0000 (10:14 -0400)]
mem: Fix DRAMSim2 cycle check when restoring from checkpoint
This patch ensures the cycle check is still valid even restoring from
a checkpoint. In this case the DRAMSim2 cycle count is relative to the
startTick rather than 0.
Andreas Hansson [Tue, 26 Aug 2014 14:14:32 +0000 (10:14 -0400)]
base: Add const to intmath and be more flexible with typing
This patch ensures the functions can be used on const variables.
Andreas Sandberg [Tue, 26 Aug 2014 14:14:30 +0000 (10:14 -0400)]
style: Add support for a style ignore list and ignore ext/
There are some directories within the repository where we don't want
to enforce our coding style. Specifically, we don't want the style
hooks to warn whenever we update external code in the ext/ directory.
Andreas Sandberg [Tue, 26 Aug 2014 14:14:07 +0000 (10:14 -0400)]
style: Fixup strange semantics in hg m5style
The 'hg m5style' command had some rather strange semantics. When
called without arguments, it applied the style checker to all added
files and modified regions of modified files. However, when providing
a list of files, it used that list as an ignore list instead of
specifically checking those files.
This patch makes the m5style command behave more like other Mercurial
commands where the arguments are used to specify which files to work
on instead of which files to ignore.
Andreas Sandberg [Tue, 26 Aug 2014 14:13:45 +0000 (10:13 -0400)]
base: Replace the internal varargs stuff with C++11 constructs
We currently use our own home-baked support for type-safe variadic
functions. This is confusing and somewhat limited (e.g., cprintf only
supports a limited number of arguments). This changeset converts all
uses of our internal varargs support to use C++11 variadic macros.
Andreas Sandberg [Tue, 26 Aug 2014 14:13:33 +0000 (10:13 -0400)]
base: Add compiler macros for C++11 final/override
Add the macros M5_ATTR_FINAL and M5_ATTR_OVERRIDE which are defined to
final and override respectively if supported by the compiler. This is
done to allow a smooth transition to gcc >= 4.7.
Mitch Hayenga [Tue, 26 Aug 2014 14:13:31 +0000 (10:13 -0400)]
mips: Fix RLIMIT_RSS naming
MIPS defined RLIMIT_RSS in a way that could cause a naming conflict with
RLIMIT_RSS from the host system. Broke clang+MacOS build.
Andreas Sandberg [Tue, 26 Aug 2014 14:13:28 +0000 (10:13 -0400)]
base: Add a static assert to check bit union ranges
If a bit field in a bit union specified as Bitfield<LSB, MSB> instead
of Bitfield<MSB, LSB> the code silently fails and the field is read as
zero. This changeset introduces a static assert that tests, at compile
time, that the bit order is correct.
Andreas Sandberg [Tue, 26 Aug 2014 14:13:23 +0000 (10:13 -0400)]
sparc: Fixup bit ordering in the PSTATE bit union
The order of the MSB and LSB bit of the mm field in the PSTATE union
is wrong. Any access to this field will currently be ignored and reads
will always return zero. This patch fixes the ordering so it is <MSB,
LSB> instead of <LSB, MSB>.
Andreas Hansson [Tue, 26 Aug 2014 14:13:03 +0000 (10:13 -0400)]
mem: Update DRAM controller comments
Update comments and add a reference for more information.
Andreas Hansson [Tue, 26 Aug 2014 14:12:45 +0000 (10:12 -0400)]
mem: Fix address interleaving bug in DRAM controller
This patch fixes a bug in the DRAM controller address decoding. In
cases where the DRAM burst size (e.g. 32 bytes in a rank with a single
LPDDR3 x32) was smaller than the channel interleaving size
(e.g. systems with a 64-byte cache line) one address bit effectively
got used as a channel bit when it should have been a low-order column
bit.
This patch adds a notion of "columns per stripe", and more clearly
deals with the low-order column bits and high-order column bits. The
patch also relaxes the granularity check such that it is possible to
use interleaving granularities other than the cache line size.
The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as
it is only used in the debug build for now.
Curtis Dunham [Wed, 5 Feb 2014 22:17:41 +0000 (16:17 -0600)]
sim: bump checkpoint version for multiple event queues
This patch adds a fix for older checkpoints before support for
multiple event queues were added in changeset
2cce74fe359e. The change
in checkpoint version should really hav ebeen part of the
aforementioned changeset.
Andreas Hansson [Tue, 26 Aug 2014 14:12:04 +0000 (10:12 -0400)]
misc: README direct to website for dependencies
This patch updates the README to direct the user to the appropriate
sections on the gem5.org website rather than duplicating information.
Dam Sunwoo [Wed, 13 Aug 2014 10:57:36 +0000 (06:57 -0400)]
arm: change MISCREG_L2ERRSR to warn not fail
Some newer binaries compiled for Versatile Express TC2 contain access
to implementation specific L2MERRSR registers. This causes an infinite
loop of undefined exceptions. This patch changes the behavior to "warn
not fail" to keep the workloads going.
Dam Sunwoo [Wed, 13 Aug 2014 10:57:35 +0000 (06:57 -0400)]
sim: remove kernel mapping check for baremetal workloads
Baremetal workloads are specified using the "kernel" parameter, but
don't always have the correct address mappings. This patch adds a
boolean flag to the system and bypasses the kernel addr mapping checks
when running in baremetal mode.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:31 +0000 (06:57 -0400)]
scons: Build the branch predictor for all CPUs
The branch predictor is normally only built when a CPU that uses a
branch predictor is built. The list of CPUs is currently incomplete as
the simple CPUs support branch predictors (for warming, branch stats,
etc). In practice, all CPU models now use branch predictors, so this
changeset removes the CPU model check and replaces it with a check for
the NULL ISA.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:30 +0000 (06:57 -0400)]
mips: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used. This changeset removes such members from the
MIPS-specific classes to silence the warning.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:29 +0000 (06:57 -0400)]
power: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used. This changeset removes such members from the
POWER-specific ProcessInfo struct to silence the warning.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:28 +0000 (06:57 -0400)]
scons: Silence clang 3.4 warnings on Ubuntu 12.04
This changeset fixes three types of warnings that occur in clang 3.4
on Ubuntu 12.04:
* Certain versions of libstdc++ (primarily 4.8) use struct and class
interchangeably. This triggers a warning in clang.
* Swig has a tendency to generate code with the register class which
was deprecated in C++11. This triggers a deprecation warning in
clang.
* Swig sometimes generates Python wrapper code which returns
uninitialized values. It's unclear if this is actually a problem
(the cases might be limited to failure paths). We'll silence these
warnings for now since there is little we can do about the
generated code.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:27 +0000 (06:57 -0400)]
base: Remove unused M5_PRAGMA_NORETURN
The M5_PRAGMA_NORETURN macro was only used in for
__exit_message. Since the macro only holds a stub definition and all
functions with noreturn semantics use the M5_ATTR_NORETURN, this
macros is completely redundant.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:26 +0000 (06:57 -0400)]
cpu: Don't forward declare RefCountingPtr
RefCountingPtr is sometimes forward declared to avoid having to
include refcnt.hh. This does not work since we typically return
instances of RefCountingPtr rather than references to instances. The
only reason this currently works is that we include refcnt.hh in
cprintf.hh, which "leaks" the header to most other source files. This
changeset replaces such forward declarations with an include of
refcnt.hh.
Andreas Sandberg [Wed, 13 Aug 2014 10:57:25 +0000 (06:57 -0400)]
util: Fix state leakage in the SortIncludes style verifier
There are cases where the state of a SortIncludes object gets messed
up and leaks between invocations/files. This typically happens when a
file ends with an include block (dump_block() gets called at the end
of __call__). In this case, the state of the class is not reset
between files. This bug manifests itself as ghost includes that leak
between files when applying the style hooks.
This changeset adds a reset at the beginning of the __call__ method
which ensures that the class is always in a clean state when
processing a new file.
Mitch Hayenga [Wed, 13 Aug 2014 10:57:24 +0000 (06:57 -0400)]
mem: Properly set cache block status fields on writebacks
When a cacheline is written back to a lower-level cache,
tags->insertBlock() sets various status parameters. However these
status bits were cleared immediately after calling. This patch makes
it so that these status fields are not cleared by moving them outside
of the tags->insertBlock() call.
Andreas Hansson [Wed, 13 Aug 2014 10:57:21 +0000 (06:57 -0400)]
cpu: Modernise the branch predictor (STL and C++11)
This patch does some minor house keeping of the branch predictor by
adopting STL containers, and shifting some iterator to use range-based
for loops.
The predictor history is also changed from a list to a deque as we
never to insertion/deletion other than at the front and back.
Curtis Dunham [Tue, 11 Mar 2014 14:50:02 +0000 (09:50 -0500)]
arm: remove dead code fplib mul64x64
Mitch Hayenga [Wed, 13 Aug 2014 10:57:19 +0000 (06:57 -0400)]
ext: clang fix for flexible array members
Changes how flexible array members are defined so clang does not error
out during compilation.
Radhika Jagtap [Sun, 10 Aug 2014 09:39:40 +0000 (05:39 -0400)]
config: Fix cache latency param in mem test
This patch fixes the cache latency in mem test which is split into two params,
hit and response latency as per BaseCache.
Radhika Jagtap [Sun, 10 Aug 2014 09:39:20 +0000 (05:39 -0400)]
util: Move packet trace file read to protolib
This patch moves the code for opening an input protobuf packet trace into
a function defined in the protobuf library. This is because the code is
commonly used in decode scripts and is independent of the src protobuf
message.
Geoffrey Blake [Sun, 10 Aug 2014 09:39:16 +0000 (05:39 -0400)]
config: Add SubSystem container for simobjects
This patch adds the SubSystem container for grouping
simobjects together in logical subsystems to facilitate
building a larger system from constituent parts. The container
is simply a non-abstract empty simobject to hold the components
that will be connected as its children. In simulation the
object does not participate, its only use is during configuration
of the system.
Geoffrey Blake [Sun, 10 Aug 2014 09:39:13 +0000 (05:39 -0400)]
config: Add hooks to enable new config sys
This patch adds helper functions to SimObject.py, params.py and
simulate.py to enable the new configuration system. Functions like
enumerateParams() in SimObject lets the config system auto-generate
command line options for simobjects to be modified on the command
line.
Params in params.py have __call__() added
to their definition to allow the argparse module to use them
as a type to check command input is in the proper format.
Andreas Hansson [Sun, 10 Aug 2014 09:39:04 +0000 (05:39 -0400)]
cpu: Ensure the traffic generator suppresses non-memory packets
This patch adds a check to ensure that packets which are not going to
a memory range are suppressed in the traffic generator. Thus, if a
trace is collected in full-system, the packets destined for devices
are not played back.
Andreas Hansson [Sun, 10 Aug 2014 09:38:59 +0000 (05:38 -0400)]
base: Remove unused files
A bit of pruning
Andreas Hansson [Sun, 10 Aug 2014 09:38:56 +0000 (05:38 -0400)]
scons: Warn for incompatible gcc and binutils
It seems gcc >4.8 does not get along well with binutils <= 2.22, and
to help users this patch adds a warning with an indication for how to
fix the issue. It might even be worth adding a Exit(-1) and stop the
build.
Anthony Gutierrez [Mon, 28 Jul 2014 16:23:23 +0000 (12:23 -0400)]
mem: refactor LRU cache tags and add random replacement tags
this patch implements a new tags class that uses a random replacement policy.
these tags prefer to evict invalid blocks first, if none are available a
replacement candidate is chosen at random.
this patch factors out the common code in the LRU class and creates a new
abstract class: the BaseSetAssoc class. any set associative tag class must
implement the functionality related to the actual replacement policy in the
following methods:
accessBlock()
findVictim()
insertBlock()
invalidate()
Anthony Gutierrez [Mon, 28 Jul 2014 16:22:00 +0000 (12:22 -0400)]
arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.
Andreas Hansson [Mon, 28 Jul 2014 05:48:21 +0000 (01:48 -0400)]
stats: Bump stats for the regressions using the minor CPU
Updating the stats to match the current behaviour.
Andrew Bardsley [Wed, 23 Jul 2014 21:09:05 +0000 (16:09 -0500)]
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
Andrew Bardsley [Wed, 23 Jul 2014 21:09:04 +0000 (16:09 -0500)]
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Minor is faster than the o3 model. Sample results:
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Steve Reinhardt [Sun, 20 Jul 2014 02:04:58 +0000 (19:04 -0700)]
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall
warning means the count of register accesses has changed on
a few runs. Oddly only Alpha Tru64 seems to have any ignored
syscalls in the regression tests.
Steve Reinhardt [Sat, 19 Jul 2014 09:06:22 +0000 (02:06 -0700)]
syscall emulation: fix fast build issue
Surprisingly gcc will complain about unused variables even
inside an 'if (false)' block.
I thought I had tested this previously, but apparently not.
Binh Pham [Sat, 19 Jul 2014 05:05:51 +0000 (22:05 -0700)]
x86: make PioBus return BadAddress errors
Stop setting the use_default_range flag in PioBus in order to
have random bad addresses result in a BadAddress response and
not a gem5 fatal error. This is necessary in Ruby as Ruby is
connected directly to PioBus, so misspeculated addresses will
be sent there directly. For the classic memory system, this
change has no effect, as bad addresses are caught by the
memory bus before being sent to the PioBus.
This work was done while Binh was an intern at AMD Research.
Steve Reinhardt [Sat, 19 Jul 2014 05:05:51 +0000 (22:05 -0700)]
sim: remove unused MemoryModeStrings array
The System object has a static MemoryModeStrings array
that's (1) unused and (2) redundant, since there's an
auto-generated version in the Enums namespace. No
point in leaving it in.
Steve Reinhardt [Sat, 19 Jul 2014 05:05:51 +0000 (22:05 -0700)]
kern: get rid of unused linux syscall files
Steve Reinhardt [Sat, 19 Jul 2014 05:05:51 +0000 (22:05 -0700)]
syscall emulation: fix DPRINTF arg ordering bug
When we switched getSyscallArg() from explicit arg indices to
the implicit method, some DPRINTF arguments were left as calls
to getSyscallArg(), even though C/C++ doesn't guarantee
anything about the order of invocation of these calls. As a
result, the args could be printed out in arbitrary orders.
Interestingly, this bug has been around since 2009:
http://repo.gem5.org/gem5/rev/
4842482e1bd1
Anthony Gutierrez [Wed, 9 Jul 2014 13:28:15 +0000 (09:28 -0400)]
base: fix operator== for comparing EthAddr objects
this operator uses memcmp() to detect if two EthAddr object have the same
address, however memcmp() will return 0 if all bytes are equal. operator==
returns the return value of memcmp() to indicate whether or not two
address are equal. this is incorrect as it will always give the opposite of
the intended behavior. this patch fixes that problem.
Anthony Gutierrez [Wed, 2 Jul 2014 17:19:13 +0000 (13:19 -0400)]
base: fix some bugs in EthAddr
per the IEEE 802 spec:
1) fixed broadcast() to ensure that all bytes are equal to 0xff.
2) fixed unicast() to ensure that bit 0 of the first byte is equal to 0
3) fixed multicast() to ensure that bit 0 of the first byte is equal to 1, and
that it is not a broadcast.
also the constructors in EthAddr are fixed so that all bytes of data are
initialized.
Radhika Jagtap [Tue, 1 Jul 2014 15:58:22 +0000 (11:58 -0400)]
util: Add DVFS perfLevel to checkpoint upgrade script
This patch updates the checkpoint upgrader script. It adds the _perfLevel
variable in the clock domain and voltage domain simObjects used for DVFS.
Stephan Diestelhorst [Mon, 30 Jun 2014 17:56:06 +0000 (13:56 -0400)]
power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
Andreas Hansson [Mon, 30 Jun 2014 17:56:04 +0000 (13:56 -0400)]
mem: DRAMPower trace formatting script
This patch adds a first version of a script that processes the debug
output and generates a command trace for DRAMPower. This is work in
progress and is intended as a snapshot of ongoing work at this point.
The longer term plan is to link in DRAMPower as a library and have one
instance of the model per rank, and instantiate it based on a struct
passed from gem5. Each command will then be a call to the model and no
parsing of traces will be necessary.
Andreas Hansson [Mon, 30 Jun 2014 17:56:03 +0000 (13:56 -0400)]
mem: DRAMPower trace output
This patch adds a DRAMPower flag to enable off-line DRAM power
analysis using the DRAMPower tool. A new DRAMPower flag is added
and a follow-on patch adds a Python script to post-process the output
and order it based on time stamps.
The long-term goal is to link DRAMPower as a library and provide the
commands through function calls to the model rather than first
printing and then parsing the commands. At the moment it is also up to
the user to ensure that the same DRAM configuration is used by the
gem5 controller model and DRAMPower.