Eddie Hung [Fri, 14 Jun 2019 19:43:20 +0000 (12:43 -0700)]
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung [Fri, 14 Jun 2019 19:40:51 +0000 (12:40 -0700)]
Cover __APPLE__ too for little to big endian
Eddie Hung [Fri, 14 Jun 2019 19:29:46 +0000 (12:29 -0700)]
Update abc9 -D doc
Eddie Hung [Fri, 14 Jun 2019 19:28:01 +0000 (12:28 -0700)]
Enable "abc9 -D <num>" for timing-driven synthesis
Eddie Hung [Fri, 14 Jun 2019 19:25:06 +0000 (12:25 -0700)]
Further cleanup based on @daveshah1
Eddie Hung [Fri, 14 Jun 2019 19:00:02 +0000 (12:00 -0700)]
Resolve comments from @daveshah1
Eddie Hung [Fri, 14 Jun 2019 18:38:22 +0000 (11:38 -0700)]
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Eddie Hung [Fri, 14 Jun 2019 18:33:10 +0000 (11:33 -0700)]
Update delays based on SymbiFlow/prjxray-db
Eddie Hung [Fri, 14 Jun 2019 17:51:11 +0000 (10:51 -0700)]
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung [Fri, 14 Jun 2019 17:42:30 +0000 (10:42 -0700)]
Comment out dist RAM boxing on ECP5 for now
Eddie Hung [Fri, 14 Jun 2019 17:37:52 +0000 (10:37 -0700)]
Remove WIP ABC9 flop support
Eddie Hung [Fri, 14 Jun 2019 17:33:27 +0000 (10:33 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 14 Jun 2019 17:32:46 +0000 (10:32 -0700)]
Make doc consistent
Eddie Hung [Fri, 14 Jun 2019 17:29:27 +0000 (10:29 -0700)]
Cleanup
Eddie Hung [Fri, 14 Jun 2019 17:29:16 +0000 (10:29 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Fri, 14 Jun 2019 17:28:30 +0000 (10:28 -0700)]
Merge pull request #1097 from YosysHQ/dave/xaig_ecp5
Add ECP5 ABC9 support (to xaig branch)
Eddie Hung [Fri, 14 Jun 2019 17:27:30 +0000 (10:27 -0700)]
Cleanup
Eddie Hung [Fri, 14 Jun 2019 17:13:17 +0000 (10:13 -0700)]
Cleanup/optimise toposort in write_xaiger
Eddie Hung [Fri, 14 Jun 2019 17:11:34 +0000 (10:11 -0700)]
Remove extra semicolon
Eddie Hung [Fri, 14 Jun 2019 17:11:13 +0000 (10:11 -0700)]
Add TODO to parse_xaiger
David Shah [Fri, 14 Jun 2019 11:02:12 +0000 (12:02 +0100)]
ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Fri, 14 Jun 2019 00:02:58 +0000 (17:02 -0700)]
Optimise some more
Eddie Hung [Thu, 13 Jun 2019 23:28:11 +0000 (16:28 -0700)]
Move ConstEvalAig to aigerparse.cc
Eddie Hung [Thu, 13 Jun 2019 21:27:07 +0000 (14:27 -0700)]
Fix name clash
Eddie Hung [Thu, 13 Jun 2019 20:29:03 +0000 (13:29 -0700)]
More slimming
Eddie Hung [Thu, 13 Jun 2019 20:13:48 +0000 (13:13 -0700)]
Add ConstEvalAig specialised for AIGs
Eddie Hung [Thu, 13 Jun 2019 16:15:30 +0000 (09:15 -0700)]
Update CHANGELOG with "synth -abc9"
Eddie Hung [Thu, 13 Jun 2019 15:24:33 +0000 (08:24 -0700)]
Fix LP SB_LUT4 timing
Eddie Hung [Thu, 13 Jun 2019 15:22:22 +0000 (08:22 -0700)]
More accurate CHANGELOG
Serge Bazanski [Thu, 13 Jun 2019 10:14:37 +0000 (12:14 +0200)]
Merge pull request #829 from abdelrahmanhosny/master
Dockerfile for Yosys
Eddie Hung [Wed, 12 Jun 2019 23:54:12 +0000 (16:54 -0700)]
Update CHANGELOG
Eddie Hung [Wed, 12 Jun 2019 23:53:12 +0000 (16:53 -0700)]
Rip out all non FPGA stuff from abc9
Eddie Hung [Wed, 12 Jun 2019 23:52:09 +0000 (16:52 -0700)]
Fix spelling
Eddie Hung [Wed, 12 Jun 2019 23:51:37 +0000 (16:51 -0700)]
Revert "For 'stat' do not count modules with abc_box_id"
This reverts commit
b89bb744529fc8a5e4cd38522f86a797117f2abc.
Eddie Hung [Wed, 12 Jun 2019 23:33:05 +0000 (16:33 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit
2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to
eaee250a6e63e58dfef63fa30c4120db78223e24.
Eddie Hung [Sun, 28 Apr 2019 19:36:04 +0000 (12:36 -0700)]
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung [Wed, 12 Jun 2019 23:04:33 +0000 (16:04 -0700)]
Be more precise when connecting during ABC9 re-integration
Eddie Hung [Wed, 12 Jun 2019 22:55:02 +0000 (15:55 -0700)]
Remove unnecessary undriven_bits.insert
Eddie Hung [Wed, 12 Jun 2019 22:52:49 +0000 (15:52 -0700)]
Remove hacky wideports_split from abc9
Eddie Hung [Wed, 12 Jun 2019 22:47:39 +0000 (15:47 -0700)]
Fix compile errors when #if 1 for debug
Eddie Hung [Wed, 12 Jun 2019 22:45:46 +0000 (15:45 -0700)]
parse_xaiger to cope with inouts
Eddie Hung [Wed, 12 Jun 2019 22:44:30 +0000 (15:44 -0700)]
write_xaiger to preserve POs even if driven by constant
Eddie Hung [Wed, 12 Jun 2019 22:43:43 +0000 (15:43 -0700)]
Add a couple more tests
Eddie Hung [Wed, 12 Jun 2019 17:18:44 +0000 (10:18 -0700)]
Do not call abc9 if no outputs
Eddie Hung [Wed, 12 Jun 2019 17:00:57 +0000 (10:00 -0700)]
More write_xaiger cleanup
Eddie Hung [Wed, 12 Jun 2019 16:53:14 +0000 (09:53 -0700)]
Cleanup write_xaiger
Eddie Hung [Wed, 12 Jun 2019 16:40:51 +0000 (09:40 -0700)]
Consistency
Eddie Hung [Wed, 12 Jun 2019 16:34:41 +0000 (09:34 -0700)]
Reduce diff with master
Eddie Hung [Wed, 12 Jun 2019 16:29:30 +0000 (09:29 -0700)]
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
Eddie Hung [Wed, 12 Jun 2019 16:21:52 +0000 (09:21 -0700)]
Fix spacing
Eddie Hung [Wed, 12 Jun 2019 16:20:46 +0000 (09:20 -0700)]
Remove wide mux inference
Eddie Hung [Wed, 12 Jun 2019 16:14:27 +0000 (09:14 -0700)]
Merge branch 'xc7mux' into xaig
Eddie Hung [Wed, 12 Jun 2019 16:14:12 +0000 (09:14 -0700)]
Merge branch 'xc7mux' of github.com:YosysHQ/yosys into xc7mux
Eddie Hung [Wed, 12 Jun 2019 16:13:53 +0000 (09:13 -0700)]
Typo: wire delay is -W argument
Eddie Hung [Wed, 12 Jun 2019 16:05:02 +0000 (09:05 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit
a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing
changes made to
b77c5da76919f7f99f171a0a2775896fbc8debc2.
Eddie Hung [Wed, 12 Jun 2019 16:04:31 +0000 (09:04 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit
eaee250a6e63e58dfef63fa30c4120db78223e24, reversing
changes made to
935df3569b4677ac38041ff01a2f67185681f4e3.
Eddie Hung [Wed, 12 Jun 2019 16:01:15 +0000 (09:01 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit
2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to
eaee250a6e63e58dfef63fa30c4120db78223e24.
Eddie Hung [Wed, 12 Jun 2019 15:52:46 +0000 (08:52 -0700)]
Merge remote-tracking branch 'origin/xc7mux' into xaig
Eddie Hung [Wed, 12 Jun 2019 15:50:39 +0000 (08:50 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Wed, 12 Jun 2019 15:49:15 +0000 (08:49 -0700)]
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung [Wed, 12 Jun 2019 15:48:45 +0000 (08:48 -0700)]
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit
2dffa4685b830313204f5d04314a14ed6ecac8ec.
Eddie Hung [Wed, 12 Jun 2019 00:10:47 +0000 (17:10 -0700)]
Add "-W' wire delay arg to abc9, use from synth_xilinx
Eddie Hung [Tue, 11 Jun 2019 23:05:27 +0000 (16:05 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit
5174082208ef9bea22ad1ba62622947375b3e83b, reversing
changes made to
54379f9872ba3abdf5328994abcf5abfc7288c6b.
Eddie Hung [Tue, 11 Jun 2019 22:48:41 +0000 (15:48 -0700)]
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung [Tue, 11 Jun 2019 22:48:20 +0000 (15:48 -0700)]
Try way that doesn't involve creating a new wire
Eddie Hung [Tue, 11 Jun 2019 19:02:51 +0000 (12:02 -0700)]
Disable dist RAM boxes due to comb loop
Eddie Hung [Tue, 11 Jun 2019 19:02:31 +0000 (12:02 -0700)]
Remove #ifndef ABC
Eddie Hung [Mon, 10 Jun 2019 23:21:43 +0000 (16:21 -0700)]
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung [Mon, 10 Jun 2019 23:16:40 +0000 (16:16 -0700)]
If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung [Mon, 10 Jun 2019 23:16:26 +0000 (16:16 -0700)]
Add test
Eddie Hung [Mon, 10 Jun 2019 21:37:09 +0000 (14:37 -0700)]
Revert "Revert "Move ff_map back after ABC for shregmap""
This reverts commit
e473e7456545d702c011ee7872956f94a8522865.
Eddie Hung [Mon, 10 Jun 2019 21:34:43 +0000 (14:34 -0700)]
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
This reverts commit
94a5f4e60985fc1e3fea75eec85638fa29874bea.
Eddie Hung [Mon, 10 Jun 2019 21:34:16 +0000 (14:34 -0700)]
Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
This reverts commit
45d1bdf83ae6d51628e917b66f1b6043c8a3baee.
Eddie Hung [Mon, 10 Jun 2019 21:34:15 +0000 (14:34 -0700)]
Revert "Refactor to ShregmapTechXilinx7Static"
This reverts commit
e1e37db86073e545269ff440da77f57135e8b155.
Eddie Hung [Mon, 10 Jun 2019 21:34:14 +0000 (14:34 -0700)]
Revert "Add -tech xilinx_static"
This reverts commit
dfe9d95579ab98d7518d40e427af858243de4eb3.
Eddie Hung [Mon, 10 Jun 2019 21:34:14 +0000 (14:34 -0700)]
Revert "Continue support for ShregmapTechXilinx7Static"
This reverts commit
72eda94a66c8c4938a713c9ae49d560e6b33574f.
Eddie Hung [Mon, 10 Jun 2019 21:34:12 +0000 (14:34 -0700)]
Revert "shregmap -tech xilinx_static to handle INIT"
This reverts commit
935df3569b4677ac38041ff01a2f67185681f4e3.
Eddie Hung [Mon, 10 Jun 2019 18:02:54 +0000 (11:02 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Mon, 10 Jun 2019 17:27:55 +0000 (10:27 -0700)]
Add some more comments
David Shah [Mon, 10 Jun 2019 14:12:23 +0000 (15:12 +0100)]
Merge pull request #1082 from corecode/u4k
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Simon Schubert [Mon, 10 Jun 2019 09:49:08 +0000 (11:49 +0200)]
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Clifford Wolf [Sat, 8 Jun 2019 09:31:19 +0000 (11:31 +0200)]
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs
Allow muxcover costs to be changed
Eddie Hung [Sat, 8 Jun 2019 00:00:36 +0000 (17:00 -0700)]
Update CHANGELOG
Eddie Hung [Fri, 7 Jun 2019 23:58:57 +0000 (16:58 -0700)]
Comment out muxpack (currently broken)
Eddie Hung [Fri, 7 Jun 2019 23:57:32 +0000 (16:57 -0700)]
Fine tune aigerparse
Eddie Hung [Fri, 7 Jun 2019 23:15:19 +0000 (16:15 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Fri, 7 Jun 2019 22:44:57 +0000 (15:44 -0700)]
Fix spacing from spaces to tabs
Clifford Wolf [Fri, 7 Jun 2019 21:13:34 +0000 (23:13 +0200)]
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
Eddie Hung [Fri, 7 Jun 2019 20:12:48 +0000 (13:12 -0700)]
Add read_aiger to CHANGELOG
Eddie Hung [Fri, 7 Jun 2019 18:30:36 +0000 (11:30 -0700)]
Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung [Fri, 7 Jun 2019 18:28:25 +0000 (11:28 -0700)]
Remove unnecessary std::getline() for ASCII
Eddie Hung [Fri, 7 Jun 2019 18:28:05 +0000 (11:28 -0700)]
Test *.aag too, by using *.aig as reference
Eddie Hung [Fri, 7 Jun 2019 18:07:15 +0000 (11:07 -0700)]
Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung [Fri, 7 Jun 2019 18:06:57 +0000 (11:06 -0700)]
Use ABC to convert from AIGER to Verilog
Eddie Hung [Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)]
Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung [Fri, 7 Jun 2019 18:05:25 +0000 (11:05 -0700)]
Add symbols to AIGER test inputs for ABC
Eddie Hung [Fri, 7 Jun 2019 15:30:39 +0000 (08:30 -0700)]
Allow muxcover costs to be changed
Eddie Hung [Fri, 7 Jun 2019 15:30:39 +0000 (08:30 -0700)]
Allow muxcover costs to be changed
Clifford Wolf [Fri, 7 Jun 2019 11:39:46 +0000 (13:39 +0200)]
Merge pull request #1077 from YosysHQ/clifford/pr983
elaboration system tasks
Clifford Wolf [Fri, 7 Jun 2019 11:12:25 +0000 (13:12 +0200)]
Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>