Eric Engestrom [Sun, 2 Feb 2020 06:54:14 +0000 (06:54 +0000)]
VERSION: bump after 20.0 branch point
Closes: #2457
Vinson Lee [Fri, 31 Jan 2020 06:19:32 +0000 (22:19 -0800)]
lima: Fix build with GCC 10.
This patch fixes this build error with GCC 10.
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_context.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_resource.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_draw.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_bo.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_submit.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_util.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_texture.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
Fixes: d71cd245d744 ("lima: Rotate dump files after each finished pp frame")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Rob Clark [Mon, 27 Jan 2020 16:35:20 +0000 (08:35 -0800)]
freedreno/ir3: fix a dirty lie
Lies, damn lies, and leftover hacks!
We no longer hard-code these two, so fix the disasm to print the correct
values.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Mon, 27 Jan 2020 16:29:35 +0000 (08:29 -0800)]
freedreno/ir3: simplify split from collect
In some cases we need to split components out from what was already a
collect. That was making it hard to DCE unused components of the
collect. (Ie. unused components of fragcoord, etc)
So just detect this case and skip the chained collect+split.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Mon, 27 Jan 2020 16:26:04 +0000 (08:26 -0800)]
freedreno/ir3: create fragcoord instructions in input block
This was somehow working to create the instructions in a random block,
and use the value in other blocks, by dumb luck. But two-pass-RA's
better choice of register assignment causes a couple dEQPs to start
failing without this fix:
dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_1
dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Fri, 24 Jan 2020 00:45:29 +0000 (16:45 -0800)]
freedreno/ir3: remove unused tex arg harder
Just killing the SSA link isn't enough. It confuses RA, legalize,
and postsched to see a bogus unused reg.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Wed, 15 Jan 2020 22:52:43 +0000 (14:52 -0800)]
freedreno/ir3: add RA sanity check
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Sun, 12 Jan 2020 01:30:24 +0000 (17:30 -0800)]
freedreno/a6xx: fix lrz overflow
Running the complete deqp_gles2 seems to trigger an overflow in lrz
cmdstream. We skip the blit clear fast-path if there have been any
draws (so mid-batch clears of any attached buffer hit the 3d pipe).
Which means it is safe to simply discard any lrz clear rendering.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Tue, 22 Oct 2019 21:00:09 +0000 (14:00 -0700)]
freedreno/ir3: two pass register allocation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Sat, 18 Jan 2020 21:44:26 +0000 (13:44 -0800)]
freedreno/ir3: don't precolor unused inputs
This apparently can happen with gs/tess. And will cause problems with
two-pass-ra, so lets just skip them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Sat, 18 Jan 2020 19:03:38 +0000 (11:03 -0800)]
freedreno/ir3: add is_tex_or_prefetch()
Some of the aspects of tex prefetch are in common with normal tex
instructions, such as having a wrmask to control which components
are written. Add a helper for this.
This should result in actually using the prefetch wrmask to avoid
fetching unneeded components.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Wed, 15 Jan 2020 22:23:23 +0000 (14:23 -0800)]
freedreno/ir3: number instructions from one
ra_block_compute_live_ranges() treats zero as "not yet defined", so
probably best to not let this be a valid instruction #
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Fri, 13 Dec 2019 22:09:39 +0000 (14:09 -0800)]
freedreno/ir3: post-RA sched pass
After RA, we can schedule to increase parallelism (reduce nop's) without
worrying about increasing register pressure. This pass lets us cut down
the instruction count ~10%, and prioritize bary.f, kill, etc, which
would tend to increase register pressure if we tried to do that before
RA.
It should be more useful if RA round-robin'd register choices.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Thu, 23 Jan 2020 18:26:27 +0000 (10:26 -0800)]
freedreno/ir3: fix kill scheduling
kill (and other cat0/flow instructions) do not have a dst register.
Which was mostly harmless before, other than RA thinking it would need
a free register to write. (But nothing consumed it, so the value would
be immediately dead.) But this would cause more problems with postsched
which would see a bogus dependency.
Also, post-RA sched *does* need to see the dependency on the predicate
register.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Tue, 22 Oct 2019 23:05:41 +0000 (16:05 -0700)]
freedreno/ir3/ra: make use()/def() functions instead of macros
Originally these were nested functions, which worked nicely, giving us
the function of a local macro that was actual 'c' syntax (ie. not token
pasted macro). But these were converted to macros because clang doesn't
let us have nice gcc extensions.
Extract these back out into functions, before adding more things and
making the macros even more cumbersome.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Thu, 19 Dec 2019 21:58:32 +0000 (13:58 -0800)]
freedreno/ir3: a bit more optmsgs debug
Also dump where arrays are allocated. This was useful for debugging.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Fri, 10 Jan 2020 22:07:03 +0000 (14:07 -0800)]
freedreno/ir3: move atomic fixup after RA
A post-RA sched pass will move the extra mov's to the wrong place, so
rework the fixup so it can run after RA (and therefore after postsched)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Wed, 18 Dec 2019 22:04:36 +0000 (14:04 -0800)]
freedreno/ir3: move block-scheduling into legalize
We want to do this only once. If we have post-RA sched pass, then we
don't want to do it pre-RA. Since legalize is where we resolve the
branch/jumps, we might as well move this into legalize.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Wed, 18 Dec 2019 19:57:41 +0000 (11:57 -0800)]
freedreno/ir3: move nop padding to legalize
This way we can deal with it in one place, *after* all the blocks have
been scheduled. Which will simplify life for a post-RA sched pass.
This has the benefit of already taking into account nop's that legalize
has to insert for non-delay related reasons.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Wed, 18 Dec 2019 19:10:12 +0000 (11:10 -0800)]
freedreno/ir3: split out delay helpers
We're going to want these also for a post-RA sched pass. And also to
split nop stuffing out into it's own pass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Thu, 19 Dec 2019 17:48:39 +0000 (09:48 -0800)]
freedreno/ir3: fix crash when no non-input instructions
This scenario can come up with block-sched and nop-sched moved to after
RA. So lets fix it first to keep things bisectable.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Tue, 17 Dec 2019 19:57:14 +0000 (11:57 -0800)]
freedreno/ir3: cleanup after lower_locals_to_regs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Rob Clark [Tue, 17 Dec 2019 17:09:16 +0000 (09:09 -0800)]
freedreno/ir3: shuffle a few ir3_register fields
It makes life easier for postsched to always be able to rely on wrmask.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Anuj Phogat [Sat, 5 Jan 2019 00:06:04 +0000 (16:06 -0800)]
intel/gen12+: Set way_size_per_bank to 4
This patch fixes the way_size_per_bank for Gen12+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Anuj Phogat [Fri, 31 Jan 2020 17:31:29 +0000 (09:31 -0800)]
intel/gen12+: Reserve 4KB of URB space per bank for Compute Engine
This patch is required to fix 11K+ vulkan CTS failures we were
getting with way_size_per_bank of 4 (see next patch).
Thanks to Sagar Ghuge and Jordan Justen for all the hard work of
debugging and testing.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Szymon Andrzejuk [Mon, 13 Jan 2020 12:01:58 +0000 (13:01 +0100)]
virgl: Use align_free for align_malloc allocated buffer
Signed-off-by: Szymon Andrzejuk <s.andrzejuk@samsung.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Rob Clark [Fri, 31 Jan 2020 21:01:52 +0000 (13:01 -0800)]
freedreno/drm: readonly cmdstream
Noticed that we weren't consistently making cmdstream buffers
gpu-readonly. Fix that and drop the need to pass flags to
fd_bo_new_ring().
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3663>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3663>
Jason Ekstrand [Thu, 30 Jan 2020 17:34:51 +0000 (11:34 -0600)]
intel/fs: Write the address register with NoMask for MOV_INDIRECT
This fixes a hang in the following Vulkan CTS test on TGL-LP:
dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Jason Ekstrand [Thu, 30 Jan 2020 17:35:52 +0000 (11:35 -0600)]
intel/tools: Handle strides better when dumping buffers
The old code would only break at stride boundaries if the stride was
less than 32B; otherwise it would just break every 32B. This commit
makes it break at stride boundaries and 32B boundaries (starting from
the last stride). This makes reading large vertex buffers in aubinator
much nicer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Jason Ekstrand [Wed, 29 Jan 2020 22:20:23 +0000 (16:20 -0600)]
intel/disasm: SEND has two sources on Gen12+
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Jason Ekstrand [Wed, 29 Jan 2020 22:23:25 +0000 (16:23 -0600)]
intel/eu/validate: Don't validate regions of sends
Otherwise, the validator tries to read the type of src1 of a SEND/SENDS
which doesn't actually have a type field. This prevents validation
issues in the next commit.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Daniel Schürmann [Fri, 31 Jan 2020 09:41:39 +0000 (10:41 +0100)]
aco: fix image_atomic_cmp_swap
Fixes: 71440ba0f5512fe455be66ca48b253ecc37478a9 ('aco: reorder VMEM operands in ACO IR')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652>
Samuel Pitoiset [Fri, 31 Jan 2020 07:23:02 +0000 (08:23 +0100)]
aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
When some unused channels are skipped and that we expand vec3 loads
to vec4 loads, we have to adjust the fourth component.
While we are at it, add an assertion to make sure we don't use
MUBUF for vec3 loads on GFX6.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2450
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2442
Fixes: 6aecc316 ("aco: fix VS input loads with MUBUF on GFX6")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641>
Krzysztof Raszkowski [Thu, 30 Jan 2020 16:25:58 +0000 (17:25 +0100)]
gallium/swr: Fix gcc 4.8.5 compile error
Stop using C++14 feature so it can be compile on default centos7
gcc compiler.
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3640>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3640>
Vinson Lee [Fri, 31 Jan 2020 04:48:26 +0000 (20:48 -0800)]
swr: Fix build with GCC 10.
GCC 10 added _mm256_storeu2_m128i.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91341
This patch fixes this build error with GCC 10.
In file included from src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.cpp:39:
../src/gallium/drivers/swr/rasterizer/common/os.h:178:20: error: ‘void _mm256_storeu2_m128i(__m128i*, __m128i*, __m256i)’ redeclared inline without ‘gnu_inline’ attribute
178 | static INLINE void _mm256_storeu2_m128i(__m128i* hi, __m128i* lo, __m256i a)
| ^~~~~~~~~~~~~~~~~~~~
In file included from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:51,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32,
from ../src/gallium/drivers/swr/rasterizer/common/os.h:107,
from src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.cpp:39:
/usr/lib/gcc/x86_64-redhat-linux/10/include/avxintrin.h:1580:1: note: ‘void _mm256_storeu2_m128i(__m128i_u*, __m128i_u*, __m256i)’ previously defined here
1580 | _mm256_storeu2_m128i (__m128i_u *__PH, __m128i_u *__PL, __m256i __A)
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3650>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3650>
Krzysztof Raszkowski [Wed, 29 Jan 2020 15:46:04 +0000 (16:46 +0100)]
gallium/swr: fix gcc warnings
Few changes to make gcc happy.
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3629>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3629>
Erik Faye-Lund [Thu, 30 Jan 2020 15:50:59 +0000 (16:50 +0100)]
zink: implement support for derivative-control
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3645>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3645>
Erik Faye-Lund [Thu, 30 Jan 2020 19:35:04 +0000 (20:35 +0100)]
zink: implement load_instance_id
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3644>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3644>
Erik Faye-Lund [Thu, 30 Jan 2020 22:15:51 +0000 (23:15 +0100)]
zink: enable texture-buffer objects
This seems to work as-is, and just need enabling. There's a few piglit
failures, but those seems to be problems with the tests, where they
don't handle lacking GL3-support.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3647>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3647>
Zhang, Boyuan [Wed, 4 Dec 2019 14:16:29 +0000 (14:16 +0000)]
radeonsi: Add support for midstream bitrate change in encoder
BACKPORT: Remove |picture| argument from enc->begin in radeon_vcn_enc.c
Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3426>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3426>
Tomeu Vizoso [Mon, 6 Jan 2020 09:48:20 +0000 (10:48 +0100)]
panfrost: Use DBG macro to avoid noise in the console
It pollutes the output of programs that use Panfrost and can confuse its
callers, such as test runners.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Tomeu Vizoso [Fri, 3 Jan 2020 08:42:11 +0000 (09:42 +0100)]
pan/midgard: Handle nir_intrinsic_load_barycentric_centroid
To avoid hitting the assert in the default case, add a nop for this
intrinsic.
dEQP-GLES3.functional.transform_feedback.random.interleaved.lines.3
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Tomeu Vizoso [Thu, 19 Dec 2019 14:07:39 +0000 (15:07 +0100)]
panfrost: Add more info to some assertions
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Tomeu Vizoso [Thu, 19 Dec 2019 13:02:54 +0000 (14:02 +0100)]
panfrost: Print intended field when decoding
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Jason Ekstrand [Mon, 27 Jan 2020 19:13:20 +0000 (13:13 -0600)]
anv: Always fill out the AUX table even if CCS is disabled
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 20:41:50 +0000 (14:41 -0600)]
iris: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 20:14:03 +0000 (14:14 -0600)]
anv: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 20:13:28 +0000 (14:13 -0600)]
intel/blorp: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 20:10:40 +0000 (14:10 -0600)]
intel/common: Return the block size from get_urb_config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Thu, 16 Jan 2020 23:05:10 +0000 (17:05 -0600)]
anv: Emit URB setup earlier
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 19:38:52 +0000 (13:38 -0600)]
iris: Consolodate URB emit
Now that we don't have to carry a URB state emit function for BLORP we
can roll some stuff together and drop a genX helper.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 18:09:13 +0000 (12:09 -0600)]
intel/blorp: Always emit URB config on Gen7+
Previously, i965/iris tried to reuse the currently programmed URB config
if it was good enough for BLORP, rather than reprogramming it each time.
However, this will make some things harder on Gen12+ and we've not seen
any performance impact from emitting URB more frequently in ANV.
This makes the blorp <-> driver interface a bit simpler on Gen7+ because
now all the driver has to do is to provide the L3$ config rather than
trying to hand off URB re-config to blorp.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Thu, 16 Jan 2020 23:02:26 +0000 (17:02 -0600)]
intel: Take a gen_l3_config in gen_get_urb_config
Instead of making each driver pass in the same push constant size and do
it's own L3$ config URB size calculation, just make them pass in their
L3$ configuration.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 19:30:48 +0000 (13:30 -0600)]
i965: Re-emit l3 state before BLORP executes
If BLORP is the first thing to execute, we may not have set the L3$
config yet. That's not normally a problem but we're about to add code
to BLORP which will look at brw_context::l3::config and we'd like that
to be initialized. It's also just good practice.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 20:22:58 +0000 (14:22 -0600)]
iris: Use the URB size from the L3$ config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 17:37:31 +0000 (11:37 -0600)]
iris: Store the L3$ configs in the screen
We only calculate them based on device info and never change them so
this seems like a reasonable place to put them. We could also put them
in the context, but that's not accessible from iris_init_*_context.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 17:36:52 +0000 (11:36 -0600)]
iris: Set SLMEnable based on the L3$ config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Fri, 17 Jan 2020 17:23:14 +0000 (11:23 -0600)]
intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11
SML is no longer in the L3$ on Gen11+. It's not incredibly clear from
the docs but no Gen11 platforms are in the list of platforms on which
this bit exists. Also, we've been always setting it false on Gen11 in
ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects.
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Thu, 16 Jan 2020 23:59:43 +0000 (17:59 -0600)]
anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+
According to the BSpec, this should prevent hangs when using shaders
with large URB entries. A more precise fix can be done but it requires
re-arranging URB setup.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Jason Ekstrand [Thu, 16 Jan 2020 23:54:49 +0000 (17:54 -0600)]
genxml: Add a new 3DSTATE_SF field on gen12
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Dylan Baker [Thu, 30 Jan 2020 22:43:17 +0000 (14:43 -0800)]
docs/release-calendar: 20.0.0-rc1 has been released
Brian Ho [Fri, 24 Jan 2020 23:04:50 +0000 (18:04 -0500)]
turnip: Fix vkCmdCopyQueryPoolResults with available flag
Previously, calling vkCmdCopyQueryPoolResults with the
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT flag set the query result
field in the buffer to 0 if unavailable and the query result if
available. This was a misunderstanding of the Vulkan spec, and this
commit corrects the behavior to emitting a separate available
result in addition to the query result.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
Brian Ho [Fri, 24 Jan 2020 21:39:47 +0000 (16:39 -0500)]
turnip: Fix vkGetQueryPoolResults with available flag
Previously, calling vkGetQueryPoolResults with the
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT flag set the query result
field in *pData to 0 if unavailable and the query result if
available. This was a misunderstanding of the Vulkan spec, and this
commit corrects the behavior to eriting a separate available result
in addition to the query result.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
Brian Ho [Thu, 30 Jan 2020 16:02:29 +0000 (11:02 -0500)]
turnip: Free event->bo on vkDestroyEvent
Fixes a leak from freeing event but not event->bo.
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3639>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3639>
Kenneth Graunke [Wed, 29 Jan 2020 15:50:16 +0000 (07:50 -0800)]
loader: Fix leak of kernel driver name
This is strdup'd, it needs to be freed.
CID:
1458032
Fixes: f93bb2fb102 ("loader: Check if the kernel driver is i915 before loading iris")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3630>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3630>
Jan Zielinski [Thu, 30 Jan 2020 08:34:55 +0000 (09:34 +0100)]
docs: Update SWR tessellation support
Update features.txt to reflect ARB_tessellation_shader
support in SWR
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3636>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3636>
Kenneth Graunke [Wed, 29 Jan 2020 08:22:02 +0000 (00:22 -0800)]
i965: Use brw_batch_references in tex_busy check
If the batch references the buffer, we will have to flush the batch
immediately before mapping it, at which point it will be busy.
(This bug has existed for a long time...even going back to BLT-era...)
Fixes: 779923194c6 ("i965/tex_image: Use meta for instead of the blitter PBO TexImage and GetTexImage")
Fixes: d5d4ba9139a ("i965/tex_subimage: use meta instead of the blitter for PBO TexSubImage")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
Christian Gmeiner [Sat, 21 Dec 2019 19:54:29 +0000 (20:54 +0100)]
etnaviv: drm-shim: add GC400
These are the ETNAVIV_PARAM's returned from a GC400 found on a
STM32MP157C-DK2 Discovery Board running mainline kernel.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3195>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3195>
Qiang Yu [Wed, 15 Jan 2020 10:00:19 +0000 (18:00 +0800)]
lima: add noheap debug option
Disable using heap buffer when set.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
Qiang Yu [Wed, 1 Jan 2020 12:25:45 +0000 (20:25 +0800)]
lima: create heap buffer with new interface if available
Newly added heap buffer create interface can create a
large enough buffer whose backup memory can increase
dynamically as needed.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
Qiang Yu [Tue, 31 Dec 2019 06:55:35 +0000 (14:55 +0800)]
lima: sync lima_drm.h with kernel
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
Icenowy Zheng [Wed, 29 Jan 2020 12:45:22 +0000 (20:45 +0800)]
lima: fix lima_set_vertex_buffers()
When setting the vertex buffers, lima calls
util_set_vertex_buffers_mask() to reference and copy buffers. That
function
function adds dst with start_slot internally, so lima should not offset
the destination address again.
This is discovered when comparing with other drivers, and fixed by
removing the extra offset in lima_set_vertex_buffers().
This fixes draws that get translated in u_vbuf, because u_vbuf adds
extra vertex buffers when translating.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3620>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3620>
Jonathan Marek [Mon, 16 Dec 2019 15:56:54 +0000 (10:56 -0500)]
turnip: hook up cmdbuffer event set/wait
Gets some basic tests under "dEQP-VK.synchronization.*event*" passing
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3123>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3123>
Christian Gmeiner [Wed, 29 Jan 2020 22:06:35 +0000 (23:06 +0100)]
etnaviv: drop default state for PE_STENCIL_CONFIG_EXT2
It gets emitted when needed.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3631>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3631>
Daniel Schürmann [Wed, 29 Jan 2020 14:30:25 +0000 (15:30 +0100)]
docs: add new features for RADV/ACO.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>
Samuel Pitoiset [Wed, 29 Jan 2020 14:02:26 +0000 (15:02 +0100)]
radv: refactor physical device properties
Based on ANV. This removes a bunch of duplicated code for properties.
Fixes: 1b8d99e2885 ("radv: bump conformance version to 1.2.0.0")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
Rob Clark [Wed, 22 Jan 2020 00:15:28 +0000 (16:15 -0800)]
freedreno: remove flush-queue
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Tue, 21 Jan 2020 23:59:22 +0000 (15:59 -0800)]
freedreno: add gmem_lock
The gmem state is split out now, so it does not require synchronization.
But gmem rendering still accesses vsc state from the context.
TODO maybe there is a better way? For gen's that don't do vsc resizing,
this is probably easier.. but for a6xx there isn't really a great
position for more fine grained locking. Maybe it doesn't matter since
in practice the lock shouldn't be contended.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Tue, 21 Jan 2020 22:28:06 +0000 (14:28 -0800)]
freedreno: add gmem state cache
Which also has the benefit of getting rid of fd_context::gmem.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Tue, 21 Jan 2020 19:27:14 +0000 (11:27 -0800)]
freedreno: get GMEM state from batch
Prep work to reduce churn in next patch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:18:32 +0000 (11:18 -0800)]
freedreno/a2xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:17:43 +0000 (11:17 -0800)]
freedreno/a3xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:16:35 +0000 (11:16 -0800)]
freedreno/a4xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:14:41 +0000 (11:14 -0800)]
freedreno/a5xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:13:49 +0000 (11:13 -0800)]
freedreno/a6xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:10:38 +0000 (11:10 -0800)]
freedreno: constify fd_vsc_pipe
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Sat, 25 Jan 2020 19:04:58 +0000 (11:04 -0800)]
freedreno: constify fd_tile
In a following patch, when we cache the gmem state, we will want to
treat the gmem state as immuatable. So start converting things to
const to make this more clear.. fd_tile is a good place to start.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Tue, 21 Jan 2020 18:47:45 +0000 (10:47 -0800)]
freedreno: consolidate GMEM state
The tile and vsc_pipe arrays are really part of the GMEM configuration.
So pull these out of fd_context and into fd_gmem_stateobj.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Rob Clark [Tue, 21 Jan 2020 18:34:29 +0000 (10:34 -0800)]
freedreno: extract vsc pipe bo from GMEM state
Prep work for reorganizing GMEM state and extracting out of fd_context.
The vsc pipe bo was the one thing that doesn't change with GMEM/tile
config.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Alejandro Piñeiro [Wed, 29 Jan 2020 13:20:19 +0000 (14:20 +0100)]
turnip: remove unused descriptor state dirty
It was only used to be initialized to zero. Not even updated as
descriptor sets are bind.
As far as I understand, setting the bit TU_CMD_DIRTY_DESCRIPTOR_SET on
tu_cmd_state.dirty is used instead.
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>
Timur Kristóf [Wed, 29 Jan 2020 12:28:58 +0000 (13:28 +0100)]
aco: Fix the meaning of is_atomic.
Previously, is_atomic really meant "is not atomic", contrary to its name.
This commit fixes it to mean what one would think it means.
Fixes: 69bed1c9186c3e24ad54089218d58c5f7b83befe
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>
Kenneth Graunke [Tue, 14 Jan 2020 00:14:24 +0000 (16:14 -0800)]
iris: Support multiple chained batches.
There was never much point in artificially limiting chaining to two
batches - we can trivially support arbitrary length chains.
Currently, we should only ever have 1 or 2, but this may change.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Kenneth Graunke [Tue, 3 Sep 2019 15:03:13 +0000 (08:03 -0700)]
iris: Make iris_emit_default_l3_config pull devinfo from the batch
No need to pass it, we can just use batch->screen->devinfo.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Kenneth Graunke [Tue, 3 Sep 2019 14:19:32 +0000 (07:19 -0700)]
iris: Drop 'engine' from iris_batch.
For the moment, everything is I915_EXEC_RENDER, so this isn't necessary.
But even should that change, I don't think we want to handle multiple
engines in this manner.
Nowadays, we have batch->name (IRIS_BATCH_RENDER, IRIS_BATCH_COMPUTE,
possibly an IRIS_BATCH_BLIT for blorp batches someday), which describes
the functional usage of the batch. We can simply check that and select
an engine for that class of work (assuming there ever is more than one).
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Eric Anholt [Wed, 29 Jan 2020 00:00:45 +0000 (16:00 -0800)]
tu: Fix binning address setup after pack macros change.
This fixes a regression in "vkcube -m headless" rendering, but upsettingly
none of my CTS tests I've been using.
Fixes: 59f29fc845ce ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")
Caught-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
Brian Ho [Tue, 28 Jan 2020 22:18:27 +0000 (17:18 -0500)]
turnip: Enable occlusionQueryPrecise
This commit enables the occlusionQueryPrecise feature. No additonal
work is required as occlusion queries are already implemented to
track exact sample counts.
Also enables a number of extra tests on the Vulkan CTS.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>
Daniel Schürmann [Thu, 23 Jan 2020 18:12:55 +0000 (19:12 +0100)]
aco: simplify gathering of MIMG address components
This patch has a slight effect on pipelinedb:
Totals from affected shaders:
SGPRS: 23616 -> 21504 (-8.94 %)
VGPRS: 15088 -> 14444 (-4.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 662660 -> 664600 (0.29 %) bytes
LDS: 49 -> 49 (0.00 %) blocks
Max Waves: 3079 -> 3204 (4.06 %)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Daniel Schürmann [Thu, 23 Jan 2020 14:38:53 +0000 (15:38 +0100)]
aco: simplify adjust_sample_index_using_fmask() & get_image_coords()
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Daniel Schürmann [Tue, 21 Jan 2020 11:11:12 +0000 (12:11 +0100)]
aco: fix register allocation with multiple live-range splits
This patch fixes register allocation if multiple live-range splits
occur to the same variable within one instruction.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Daniel Schürmann [Thu, 16 Jan 2020 15:54:35 +0000 (16:54 +0100)]
aco: reorder VMEM operands in ACO IR
For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
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