yosys.git
10 years agoAdded Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf [Fri, 15 Aug 2014 00:08:02 +0000 (02:08 +0200)]
Added Frontend "+/" filename syntax for files from proc_share_dir

10 years agodocument "techmap -map %<design-name>"
Clifford Wolf [Fri, 15 Aug 2014 00:00:53 +0000 (02:00 +0200)]
document "techmap -map %<design-name>"

10 years agoFixed bug in "read_verilog -ignore_redef"
Clifford Wolf [Thu, 14 Aug 2014 23:53:22 +0000 (01:53 +0200)]
Fixed bug in "read_verilog -ignore_redef"

10 years agoAdded RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf [Thu, 14 Aug 2014 21:14:47 +0000 (23:14 +0200)]
Added RTLIL::SigSpec::to_sigbit_map()

10 years agoChanged the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf [Thu, 14 Aug 2014 21:02:07 +0000 (23:02 +0200)]
Changed the AST genWidthRTLIL subst interface to use a std::map

10 years agoAdded sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf [Thu, 14 Aug 2014 20:32:18 +0000 (22:32 +0200)]
Added sig.{replace,remove,extract} variants for std::{map,set} pattern

10 years agoFixed line numbers when using here-doc macros
Clifford Wolf [Thu, 14 Aug 2014 20:26:30 +0000 (22:26 +0200)]
Fixed line numbers when using here-doc macros

10 years agoFixed handling of task outputs
Clifford Wolf [Thu, 14 Aug 2014 20:26:10 +0000 (22:26 +0200)]
Fixed handling of task outputs

10 years agoSimplified $__arraymul techmap rule
Clifford Wolf [Thu, 14 Aug 2014 18:53:21 +0000 (20:53 +0200)]
Simplified $__arraymul techmap rule

10 years agoAdded module->ports
Clifford Wolf [Thu, 14 Aug 2014 14:13:42 +0000 (16:13 +0200)]
Added module->ports

10 years agoRefactoring of CellType class
Clifford Wolf [Thu, 14 Aug 2014 13:46:51 +0000 (15:46 +0200)]
Refactoring of CellType class

10 years agoRIP $safe_pmux
Clifford Wolf [Thu, 14 Aug 2014 09:39:46 +0000 (11:39 +0200)]
RIP $safe_pmux

10 years agoSome improvements in FSM mapping and recoding
Clifford Wolf [Thu, 14 Aug 2014 09:22:45 +0000 (11:22 +0200)]
Some improvements in FSM mapping and recoding

10 years agoAdded "abc -D" for setting delay target
Clifford Wolf [Thu, 14 Aug 2014 09:05:25 +0000 (11:05 +0200)]
Added "abc -D" for setting delay target

10 years agoUpdated ABC to 4935c2b946de
Clifford Wolf [Thu, 14 Aug 2014 08:19:12 +0000 (10:19 +0200)]
Updated ABC to 4935c2b946de

10 years agoAdded techmap support for actual lookahead carry unit
Clifford Wolf [Wed, 13 Aug 2014 16:40:57 +0000 (18:40 +0200)]
Added techmap support for actual lookahead carry unit

10 years agoPreparations for lookahead ALU support in techmap.v
Clifford Wolf [Wed, 13 Aug 2014 14:36:30 +0000 (16:36 +0200)]
Preparations for lookahead ALU support in techmap.v

10 years agoFilter ANSI escape sequences from ABC output
Clifford Wolf [Wed, 13 Aug 2014 11:40:29 +0000 (13:40 +0200)]
Filter ANSI escape sequences from ABC output

10 years agoNew interface for $__alu in techmap.v
Clifford Wolf [Wed, 13 Aug 2014 11:04:28 +0000 (13:04 +0200)]
New interface for $__alu in techmap.v

10 years agoAdded support for non-standard """ macro bodies
Clifford Wolf [Wed, 13 Aug 2014 11:03:38 +0000 (13:03 +0200)]
Added support for non-standard """ macro bodies

10 years agoFixed handling of constant-true branches in proc_clean
Clifford Wolf [Tue, 12 Aug 2014 15:35:22 +0000 (17:35 +0200)]
Fixed handling of constant-true branches in proc_clean

10 years agoAdded test_verific mode to tests/fsm/generate.py
Clifford Wolf [Tue, 12 Aug 2014 13:43:30 +0000 (15:43 +0200)]
Added test_verific mode to tests/fsm/generate.py

10 years agoFixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf [Tue, 12 Aug 2014 13:39:48 +0000 (15:39 +0200)]
Fixed SigBit(RTLIL::Wire *wire) constructor

10 years agoFixed building verific bindings
Clifford Wolf [Tue, 12 Aug 2014 13:21:06 +0000 (15:21 +0200)]
Fixed building verific bindings

10 years agoAdded multi-dim memory test (requires iverilog git head)
Clifford Wolf [Tue, 12 Aug 2014 08:37:47 +0000 (10:37 +0200)]
Added multi-dim memory test (requires iverilog git head)

10 years agoAnother build fix by americanrouter (via reddit)
Clifford Wolf [Mon, 11 Aug 2014 13:55:41 +0000 (15:55 +0200)]
Another build fix by americanrouter (via reddit)

10 years agoFixed FSM mapping for multiple reset-like signals
Clifford Wolf [Sun, 10 Aug 2014 10:04:02 +0000 (12:04 +0200)]
Fixed FSM mapping for multiple reset-like signals

10 years agoFixed "share" for complex scenarios with never-active cells
Clifford Wolf [Sat, 9 Aug 2014 15:07:20 +0000 (17:07 +0200)]
Fixed "share" for complex scenarios with never-active cells

10 years agoDo not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf [Sat, 9 Aug 2014 13:17:54 +0000 (15:17 +0200)]
Do not share any $reduce_* cells (its complicated and not worth it anyways)

10 years agoSome improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf [Sat, 9 Aug 2014 12:49:51 +0000 (14:49 +0200)]
Some improvements in fsm_opt and fsm_map for FSM with unreachable states

10 years agoImproved FSM tests
Clifford Wolf [Fri, 8 Aug 2014 12:30:45 +0000 (14:30 +0200)]
Improved FSM tests

10 years agoAnother fsm_extract bugfix
Clifford Wolf [Fri, 8 Aug 2014 12:55:11 +0000 (14:55 +0200)]
Another fsm_extract bugfix

10 years agoFixed "fsm -export"
Clifford Wolf [Fri, 8 Aug 2014 12:49:06 +0000 (14:49 +0200)]
Fixed "fsm -export"

10 years agoFixed sharing of reduce operator
Clifford Wolf [Fri, 8 Aug 2014 12:24:09 +0000 (14:24 +0200)]
Fixed sharing of reduce operator

10 years agoFixed fsm_extract for wreduced muxes
Clifford Wolf [Fri, 8 Aug 2014 11:47:20 +0000 (13:47 +0200)]
Fixed fsm_extract for wreduced muxes

10 years agoAdded FSM test bench
Clifford Wolf [Fri, 8 Aug 2014 11:12:18 +0000 (13:12 +0200)]
Added FSM test bench

10 years agoAdded "sat -prove-skip"
Clifford Wolf [Fri, 8 Aug 2014 11:11:54 +0000 (13:11 +0200)]
Added "sat -prove-skip"

10 years agoFixed build with gcc-4.6
Clifford Wolf [Thu, 7 Aug 2014 20:37:01 +0000 (22:37 +0200)]
Fixed build with gcc-4.6

10 years agoUse "-keepdc" in "miter -equiv -flatten"
Clifford Wolf [Thu, 7 Aug 2014 14:42:35 +0000 (16:42 +0200)]
Use "-keepdc" in "miter -equiv -flatten"

10 years agoAlso allow "module foobar(input foo, output bar, ...);" syntax
Clifford Wolf [Thu, 7 Aug 2014 14:41:27 +0000 (16:41 +0200)]
Also allow "module foobar(input foo, output bar, ...);" syntax

10 years agoAdded adff2dff.v (for techmap -share_map)
Clifford Wolf [Thu, 7 Aug 2014 14:14:38 +0000 (16:14 +0200)]
Added adff2dff.v (for techmap -share_map)

10 years agoAdded AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf [Wed, 6 Aug 2014 13:43:46 +0000 (15:43 +0200)]
Added AST_MULTIRANGE (arrays with more than 1 dimension)

10 years agoVarious improvements in memory_dff pass
Clifford Wolf [Wed, 6 Aug 2014 12:31:38 +0000 (14:31 +0200)]
Various improvements in memory_dff pass

10 years agoVarious fixes and improvements in wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 17:01:41 +0000 (19:01 +0200)]
Various fixes and improvements in wreduce pass

10 years agoRemoved old "constmap" from wreduce code
Clifford Wolf [Tue, 5 Aug 2014 14:53:53 +0000 (16:53 +0200)]
Removed old "constmap" from wreduce code

10 years agoAdded support for truncating of wires to wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 12:47:03 +0000 (14:47 +0200)]
Added support for truncating of wires to wreduce pass

10 years agoCleanups and improvements in wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 11:11:04 +0000 (13:11 +0200)]
Cleanups and improvements in wreduce pass

10 years agoAdded mux support to wreduce command
Clifford Wolf [Tue, 5 Aug 2014 10:49:53 +0000 (12:49 +0200)]
Added mux support to wreduce command

10 years agoImproved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf [Tue, 5 Aug 2014 10:15:53 +0000 (12:15 +0200)]
Improved scope resolution of local regs in Verilog+AST frontend

10 years agoFixed AST handling of variables declared inside a functions main block
Clifford Wolf [Tue, 5 Aug 2014 06:35:51 +0000 (08:35 +0200)]
Fixed AST handling of variables declared inside a functions main block

10 years agoAdded "show -signed"
Clifford Wolf [Mon, 4 Aug 2014 13:33:51 +0000 (15:33 +0200)]
Added "show -signed"

10 years agoAdded support for non-standard "module mod_name(...);" syntax
Clifford Wolf [Mon, 4 Aug 2014 13:19:24 +0000 (15:19 +0200)]
Added support for non-standard "module mod_name(...);" syntax

10 years agoAdded RTLIL::IdString::in(...)
Clifford Wolf [Mon, 4 Aug 2014 13:08:35 +0000 (15:08 +0200)]
Added RTLIL::IdString::in(...)

10 years agoFixed "share" for memory read ports
Clifford Wolf [Sun, 3 Aug 2014 18:19:50 +0000 (20:19 +0200)]
Fixed "share" for memory read ports

10 years agoAdded "wreduce" to some of the standard test benches
Clifford Wolf [Sun, 3 Aug 2014 18:03:16 +0000 (20:03 +0200)]
Added "wreduce" to some of the standard test benches

10 years agoProgress in "wreduce" pass
Clifford Wolf [Sun, 3 Aug 2014 18:02:42 +0000 (20:02 +0200)]
Progress in "wreduce" pass

10 years agoAdded "wreduce" command (work in progress)
Clifford Wolf [Sun, 3 Aug 2014 13:02:05 +0000 (15:02 +0200)]
Added "wreduce" command (work in progress)

10 years agoAdded query() API to ModIndex
Clifford Wolf [Sun, 3 Aug 2014 13:00:38 +0000 (15:00 +0200)]
Added query() API to ModIndex

10 years agoAdded ID() macro for static IdStrings
Clifford Wolf [Sun, 3 Aug 2014 12:59:13 +0000 (14:59 +0200)]
Added ID() macro for static IdStrings

10 years agoImplemented recursive techmap
Clifford Wolf [Sun, 3 Aug 2014 10:40:43 +0000 (12:40 +0200)]
Implemented recursive techmap

10 years agoFixes in show command (related to new IdString)
Clifford Wolf [Sun, 3 Aug 2014 10:40:23 +0000 (12:40 +0200)]
Fixes in show command (related to new IdString)

10 years agoImplemented simplemap support for "techmap -extern"
Clifford Wolf [Sat, 2 Aug 2014 19:55:13 +0000 (21:55 +0200)]
Implemented simplemap support for "techmap -extern"

10 years agoFixed a va_list corruption in logv_error()
Clifford Wolf [Sat, 2 Aug 2014 19:54:30 +0000 (21:54 +0200)]
Fixed a va_list corruption in logv_error()

10 years agoBe more conservative with printing decimal numbers in verilog backend
Clifford Wolf [Sat, 2 Aug 2014 19:54:02 +0000 (21:54 +0200)]
Be more conservative with printing decimal numbers in verilog backend

10 years agoImproved verilog output for ordinary $mux cells
Clifford Wolf [Sat, 2 Aug 2014 19:10:08 +0000 (21:10 +0200)]
Improved verilog output for ordinary $mux cells

10 years agoBugfix in "techmap -extern"
Clifford Wolf [Sat, 2 Aug 2014 18:54:30 +0000 (20:54 +0200)]
Bugfix in "techmap -extern"

10 years agoRemoved at() method from RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 17:08:02 +0000 (19:08 +0200)]
Removed at() method from RTLIL::IdString

10 years agoNo implicit conversion from IdString to anything else
Clifford Wolf [Sat, 2 Aug 2014 16:58:40 +0000 (18:58 +0200)]
No implicit conversion from IdString to anything else

10 years agoMore bugfixes related to new RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 14:03:18 +0000 (16:03 +0200)]
More bugfixes related to new RTLIL::IdString

10 years agoLimit size of log_signal buffer to 100 elements
Clifford Wolf [Sat, 2 Aug 2014 13:52:21 +0000 (15:52 +0200)]
Limit size of log_signal buffer to 100 elements

10 years agoImprovements in new RTLIL::IdString implementation
Clifford Wolf [Sat, 2 Aug 2014 13:44:10 +0000 (15:44 +0200)]
Improvements in new RTLIL::IdString implementation

10 years agoFixed a performance bug in opt_reduce
Clifford Wolf [Sat, 2 Aug 2014 13:12:16 +0000 (15:12 +0200)]
Fixed a performance bug in opt_reduce

10 years agoImplemented new reference counting RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 13:11:35 +0000 (15:11 +0200)]
Implemented new reference counting RTLIL::IdString

10 years agoFixed memory corruption related to id2cstr()
Clifford Wolf [Sat, 2 Aug 2014 11:34:07 +0000 (13:34 +0200)]
Fixed memory corruption related to id2cstr()

10 years agoMore cleanups related to RTLIL::IdString usage
Clifford Wolf [Sat, 2 Aug 2014 11:11:01 +0000 (13:11 +0200)]
More cleanups related to RTLIL::IdString usage

10 years agoPreparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf [Fri, 1 Aug 2014 22:45:25 +0000 (00:45 +0200)]
Preparations for RTLIL::IdString redesign: cleanup of existing code

10 years agoAdded logfile hash to statistics footer
Clifford Wolf [Fri, 1 Aug 2014 17:43:28 +0000 (19:43 +0200)]
Added logfile hash to statistics footer

10 years agoReplaced sha1 implementation
Clifford Wolf [Fri, 1 Aug 2014 17:01:10 +0000 (19:01 +0200)]
Replaced sha1 implementation

10 years agoAdded per-pass cpu usage statistics
Clifford Wolf [Fri, 1 Aug 2014 16:42:10 +0000 (18:42 +0200)]
Added per-pass cpu usage statistics

10 years agoAdded ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf [Fri, 1 Aug 2014 14:53:15 +0000 (16:53 +0200)]
Added ModIndex helper class, some changes to RTLIL::Monitor

10 years agoPacked SigBit::data and SigBit::offset in a union
Clifford Wolf [Fri, 1 Aug 2014 13:25:42 +0000 (15:25 +0200)]
Packed SigBit::data and SigBit::offset in a union

10 years agoConsolidated hana test benches into fewer files
Clifford Wolf [Fri, 1 Aug 2014 01:57:37 +0000 (03:57 +0200)]
Consolidated hana test benches into fewer files

for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..

10 years agoAdded "test_autotb -n <num_iter>" option
Clifford Wolf [Fri, 1 Aug 2014 01:55:51 +0000 (03:55 +0200)]
Added "test_autotb -n <num_iter>" option

10 years agoRenamed modwalker.h to modtools.h
Clifford Wolf [Thu, 31 Jul 2014 21:30:18 +0000 (23:30 +0200)]
Renamed modwalker.h to modtools.h

10 years agoVarious cleanups in Makefile, Renamed default configurations
Clifford Wolf [Thu, 31 Jul 2014 21:14:17 +0000 (23:14 +0200)]
Various cleanups in Makefile, Renamed default configurations

10 years agoAdded compiler + compiler version + compiler flags to version string
Clifford Wolf [Thu, 31 Jul 2014 21:07:00 +0000 (23:07 +0200)]
Added compiler + compiler version + compiler flags to version string

10 years agoFixed build of verific bindings
Clifford Wolf [Thu, 31 Jul 2014 14:45:23 +0000 (16:45 +0200)]
Fixed build of verific bindings

10 years agoRenamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf [Thu, 31 Jul 2014 14:38:54 +0000 (16:38 +0200)]
Renamed port access function on RTLIL::Cell, added param access functions

10 years agoAdded "trace" command
Clifford Wolf [Thu, 31 Jul 2014 13:02:16 +0000 (15:02 +0200)]
Added "trace" command

10 years agoAdded RTLIL::Monitor
Clifford Wolf [Thu, 31 Jul 2014 12:34:12 +0000 (14:34 +0200)]
Added RTLIL::Monitor

10 years agoAdded module->design and cell->module, wire->module pointers
Clifford Wolf [Thu, 31 Jul 2014 12:11:39 +0000 (14:11 +0200)]
Added module->design and cell->module, wire->module pointers

10 years agoMoved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf [Thu, 31 Jul 2014 11:19:47 +0000 (13:19 +0200)]
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

10 years agoRenamed "stdcells.v" to "techmap.v"
Clifford Wolf [Thu, 31 Jul 2014 00:32:00 +0000 (02:32 +0200)]
Renamed "stdcells.v" to "techmap.v"

10 years agoAdded "techmap -assert"
Clifford Wolf [Thu, 31 Jul 2014 00:21:41 +0000 (02:21 +0200)]
Added "techmap -assert"

10 years agoReorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf [Thu, 31 Jul 2014 00:21:06 +0000 (02:21 +0200)]
Reorganized stdcells.v (no actual code change, just moved and indented stuff)

10 years agoAdded "yosys -A"
Clifford Wolf [Wed, 30 Jul 2014 23:05:27 +0000 (01:05 +0200)]
Added "yosys -A"

10 years agoAdded "yosys -Q"
Clifford Wolf [Wed, 30 Jul 2014 22:53:21 +0000 (00:53 +0200)]
Added "yosys -Q"

10 years agoAdded techmap CONSTMAP feature
Clifford Wolf [Wed, 30 Jul 2014 20:04:30 +0000 (22:04 +0200)]
Added techmap CONSTMAP feature

10 years agoFixed counting verilog line numbers for "// synopsys translate_off" sections
Clifford Wolf [Wed, 30 Jul 2014 18:18:48 +0000 (20:18 +0200)]
Fixed counting verilog line numbers for "// synopsys translate_off" sections

10 years agoAdded write_file command
Clifford Wolf [Wed, 30 Jul 2014 17:59:29 +0000 (19:59 +0200)]
Added write_file command