mesa.git
5 years agoradv: Use pbb_allow for framebuffer BREAK_BATCH.
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:10:36 +0000 (01:10 +0200)]
radv: Use pbb_allow for framebuffer BREAK_BATCH.

Ported from radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agoradeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.
Marek Olšák [Tue, 23 Jul 2019 01:20:29 +0000 (21:20 -0400)]
radeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.

This doesn't implement the color buffer load.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agotgsi/scan: add uses_fbfetch
Marek Olšák [Tue, 23 Jul 2019 01:08:48 +0000 (21:08 -0400)]
tgsi/scan: add uses_fbfetch

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoradeonsi: fail if importing a texture with incorrect last_level or samples
Marek Olšák [Mon, 22 Jul 2019 22:07:06 +0000 (18:07 -0400)]
radeonsi: fail if importing a texture with incorrect last_level or samples

v2: don't fail if the texture comes from an incompatible driver.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
5 years agoradeonsi: rewrite si_get_opaque_metadata, also for gfx10 support
Marek Olšák [Mon, 22 Jul 2019 22:03:13 +0000 (18:03 -0400)]
radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoradeonsi: simplify si_get_input_prim and remove incorrect TODO comment
Marek Olšák [Sat, 20 Jul 2019 01:12:43 +0000 (21:12 -0400)]
radeonsi: simplify si_get_input_prim and remove incorrect TODO comment

u_vertices_per_prim(QUADS) is the same as TRIANGLES.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoradeonsi/gfx10: fix and enable CLEAR_STATE
Marek Olšák [Thu, 18 Jul 2019 03:29:22 +0000 (23:29 -0400)]
radeonsi/gfx10: fix and enable CLEAR_STATE

it was a driver bug.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoradeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]
Marek Olšák [Wed, 17 Jul 2019 23:32:12 +0000 (19:32 -0400)]
radeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoac/nir: implement nir_op_pack_{us}norm_2x16
Marek Olšák [Wed, 17 Jul 2019 22:54:42 +0000 (18:54 -0400)]
ac/nir: implement nir_op_pack_{us}norm_2x16

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agomesa/st: rewrite src var when lowering tex_src_plane
Pierre-Eric Pelloux-Prayer [Thu, 18 Jul 2019 13:04:05 +0000 (15:04 +0200)]
mesa/st: rewrite src var when lowering tex_src_plane

The assign_extra_samplers() adds the needed extra samplers but they need
to be used in the nir_tex_instr.
Otherwise the plane information is simply lost and all nir_tex_instr use the
same sampler.
Here's an example of the bug:

NIR before st_nir_lower_tex_src_plane:
vec1 32 ssa_8 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_9 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord), ssa_8 (plane)
vec1 32 ssa_10 = load_const (0x00000001 /* 0.000000 */)
vec4 32 ssa_11 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord), ssa_10 (plane)

After:

vec4 32 ssa_9 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord)
vec4 32 ssa_11 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord)

This fixes the following piglit test for radeonsi + NIR:
  - ext_image_dma_buf_import-sample_nv12
  - ext_image_dma_buf_import-sample_yuv420
  - ext_image_dma_buf_import-sample_yvu420

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
5 years agou_blitter: add a msaa parameter to util_blitter_clear
Pierre-Eric Pelloux-Prayer [Mon, 22 Jul 2019 14:14:20 +0000 (16:14 +0200)]
u_blitter: add a msaa parameter to util_blitter_clear

Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agou_blitter: enable msaa when dst num samples is > 1
Pierre-Eric Pelloux-Prayer [Mon, 22 Jul 2019 12:02:14 +0000 (14:02 +0200)]
u_blitter: enable msaa when dst num samples is > 1

Commit ea5b7de138b broke some piglit tests on radeonsi (Bonaire hardware).
This commit fixes half of the regression by enabling msaa if the dest surface has
more than 1 sample (instead of hardcoding it to false).

Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agonir/gather_info: Look for uses of helper invocations
Jason Ekstrand [Fri, 7 Jun 2019 23:07:46 +0000 (18:07 -0500)]
nir/gather_info: Look for uses of helper invocations

The one obvious omission here is gl_HelperInvocation itself.  However,
the spec doesn't require that we generate then when gl_HelperInvocation
is used, it merely mandates that we report them if they are there.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agonir/gather_info: Move setting uses_64bit out of the switch
Jason Ekstrand [Fri, 7 Jun 2019 23:03:10 +0000 (18:03 -0500)]
nir/gather_info: Move setting uses_64bit out of the switch

Otherwise, as we add things to the switch, we're going to forget and add
some 64-bit op at some point in the future and it'll stop getting
flagged.  There's no reason why we can't do the check for derivatives.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agonir: Add a nir_tex_instr_has_implicit_derivatives helper
Jason Ekstrand [Fri, 7 Jun 2019 22:58:15 +0000 (17:58 -0500)]
nir: Add a nir_tex_instr_has_implicit_derivatives helper

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agonir: Move nir_alu_instr_is_comparison to the ALU section
Jason Ekstrand [Fri, 7 Jun 2019 22:57:35 +0000 (17:57 -0500)]
nir: Move nir_alu_instr_is_comparison to the ALU section

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/genxml: Add new test for subgroups.
Rafael Antognolli [Tue, 16 Jul 2019 21:26:47 +0000 (14:26 -0700)]
intel/genxml: Add new test for subgroups.

Make sure that a <group> tag within another <group> tag work just fine.

v2: rename 'halfbyte' to 'byte' to match the size (Lionel).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/genxml: Add basic infra for encoding/decoding unit tests.
Rafael Antognolli [Tue, 16 Jul 2019 17:28:25 +0000 (10:28 -0700)]
intel/genxml: Add basic infra for encoding/decoding unit tests.

Adding option to print quiet.

v2: Add license header.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Decode <group> inside <group>.
Rafael Antognolli [Mon, 15 Jul 2019 23:04:44 +0000 (16:04 -0700)]
intel/gen_decoder: Decode <group> inside <group>.

Now we can decode a <group> tag inside another <group> tag, and properly
print its indices and content.

v2: Use push/pop stack to fields, groups and iters (Lionel).
v3: Add assert(iter->level < DECODE_MAX_ARRAY_DEPTH) (Lionel).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Add the concept of array "levels".
Rafael Antognolli [Fri, 12 Jul 2019 23:30:39 +0000 (16:30 -0700)]
intel/gen_decoder: Add the concept of array "levels".

We currently only support one level, which is the basic level of a
<group> tag.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Add array field.
Rafael Antognolli [Fri, 12 Jul 2019 23:13:56 +0000 (16:13 -0700)]
intel/gen_decoder: Add array field.

We currently use the group->next pointer to iterate through the <group>
tags. This change them to be a type of field, so we can descend into
them while iterating, and then go back to the original position. Will be
useful when we want to decode <group>'s inside <group>'s, and when there
are more <field>'s after a <group> tag.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Rename internally "group" to "array".
Rafael Antognolli [Thu, 11 Jul 2019 23:02:46 +0000 (16:02 -0700)]
intel/gen_decoder: Rename internally "group" to "array".

A gen_group (group in most of the code) can be of several types:
   - instruction
   - struct
   - register
   - group (?!?)

The <group> tag actually represents an array of elements. So at least
in our code, lets call it an array to avoid confusion with gen_group.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Add gen_spec_load_filename() function.
Rafael Antognolli [Tue, 16 Jul 2019 17:07:37 +0000 (10:07 -0700)]
intel/gen_decoder: Add gen_spec_load_filename() function.

Refactor the code from gen_spec_load_from_path() into a separate
function, that can be used with a xml file that doesn't fit the genX.xml
filename format.

Will be used soon for implementing unit tests for gen_decoder.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/gen_decoder: Fix parsing of small genxml file.
Rafael Antognolli [Tue, 16 Jul 2019 17:00:18 +0000 (10:00 -0700)]
intel/gen_decoder: Fix parsing of small genxml file.

When using gen_spec_load_from path, only abort decoding if the read
length is 0. Previously, we were aborting if finding an EOF, even if
something was read from the file.

Also only kill the decoded file if no commands or structs were found,
and print a message in such case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agokmsro: Extend to include mxsfb-drm
Guido Günther [Sun, 21 Jul 2019 14:20:18 +0000 (16:20 +0200)]
kmsro: Extend to include mxsfb-drm

This allows using the LCDIF display controllers (with the mxsfb drm
modesetting driver) along with the Etnaviv render-only drivers. LCDIF is
found on i.MX SoCs.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoanv: Implement VK_KHR_imageless_framebuffer
Sagar Ghuge [Thu, 17 Jan 2019 18:28:36 +0000 (10:28 -0800)]
anv: Implement VK_KHR_imageless_framebuffer

v2: Pass pointer instead of struct instance (Lionel)

v3: 1) Fix small nits (Jason)
    2) Add way to detect anv_framebuffer don't have attachments (Jason)
    3) Get rid of unncessary pNext chain walk (Jason)
    4) Keep framebuffer instance in anv_cmd_state (Jason)

v4: 1) Dump attachments from cmd_buffer (Jason)

v5: 1) Fix condition check and add assertion (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopanfrost/midgard: Allocate registers once (per-screen)
Alyssa Rosenzweig [Tue, 23 Jul 2019 14:59:00 +0000 (07:59 -0700)]
panfrost/midgard: Allocate registers once (per-screen)

This should save a lot of per-compile time by using the RA the way it's
actually supposed to be used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoanv: fix use of comma operator
Lionel Landwerlin [Tue, 23 Jul 2019 11:12:43 +0000 (14:12 +0300)]
anv: fix use of comma operator

This doesn't fix any bug at the moment because the next statement is
'true' which happens to be APIMODE_D3D, but if that changes it could.

The fixes tags is as far I could go but the error predates it (2016 is
probably far enough).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 8db6f2e6ebb9 ("anv/pipeline: Roll genX_pipeline_util.h into genX_pipeline.c")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir: use | instead of || operator
Andrii Simiklit [Mon, 22 Jul 2019 15:00:34 +0000 (18:00 +0300)]
nir: use | instead of || operator

warning: use of logical '||' with constant operand
note: use '|' for a bitwise operation

Fixes: 758fdce9fee ("nir: Add some generic helpers for writing lowering passes")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
5 years agopanfrost: Fix T6XX Support
Arnaud Patard [Tue, 23 Jul 2019 13:42:00 +0000 (06:42 -0700)]
panfrost: Fix T6XX Support

While testing kmscube with mesa master, it turns out that kmscube is not
working anymore. After bisecting, commit
5a7688fdecd76c7d9cd87f6f6c93eb32870a2146 is the culprit. A short trial
and error session allowed to find the removed bit of code making kmscube
working again.

This patch adds it back.

Fixes: 5a7688fde ("panfrost: Use 64-bit descriptors globally")
v2: Add comment pointing out this is magic. [Alyssa, trivial]

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Use correct definition for is_t6xx
Alyssa Rosenzweig [Tue, 23 Jul 2019 13:56:51 +0000 (06:56 -0700)]
panfrost: Use correct definition for is_t6xx

Rather than anything "early Midgard", limit us specifically to T6XX, as
certain workarounds only apply to genuine T6XX, not T7XX.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agonir: don't return void
Eric Engestrom [Fri, 19 Jul 2019 21:23:38 +0000 (22:23 +0100)]
nir: don't return void

Fixes: 14531d676b11999123c0 ("nir: make nir_const_value scalar")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
5 years agoutil: fix asprintf() fallback
Eric Engestrom [Tue, 23 Jul 2019 09:52:16 +0000 (10:52 +0100)]
util: fix asprintf() fallback

Fixes: 9607d499dcdd09160b13 ("util: add asprintf() wrapper for MSVC")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agost/mesa: Try re-importing resource if necessary in st_vdpau_map_surface
Michel Dänzer [Wed, 17 Jul 2019 10:18:11 +0000 (12:18 +0200)]
st/mesa: Try re-importing resource if necessary in st_vdpau_map_surface

This can be the case if the resource was obtained from
st_vdpau_output/video_surface_gallium.

st_vdpau_output/video_surface_dma_buf do a similar dance internally.

v2:
* Pass PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE instead of 0 for usage.

Bugzilla: https://bugs.freedesktop.org/111099
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> # v1
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi: Allow PIPE_TEXTURE_2D_ARRAY in si_texture_from_handle
Michel Dänzer [Wed, 17 Jul 2019 10:16:15 +0000 (12:16 +0200)]
radeonsi: Allow PIPE_TEXTURE_2D_ARRAY in si_texture_from_handle

Needed for the following st/mesa fix.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agopanfrost: Fake CAPs for dEQP-GLES31
Alyssa Rosenzweig [Tue, 23 Jul 2019 03:11:04 +0000 (20:11 -0700)]
panfrost: Fake CAPs for dEQP-GLES31

We still have some big ticket items left on GLES 3.0, but it's often
helpful to be able to access higher dEQP levels for debugging features
that just don't quite match a particular API.

Plus, this opens up a whole slew of new features to poke at if boredom
overtakes, ahem.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agonvc0/ir: Fix assert accessing null pointer
Mark Menzynski [Fri, 19 Jul 2019 11:09:02 +0000 (13:09 +0200)]
nvc0/ir: Fix assert accessing null pointer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111167

Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann<tobias.klausmann@freenet.de>
5 years agoradv/gfx10: enable CLEAR_state
Samuel Pitoiset [Tue, 23 Jul 2019 06:41:15 +0000 (08:41 +0200)]
radv/gfx10: enable CLEAR_state

It actually works.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agodocs: update calendar, add news item and link release notes for 19.1.3
Juan A. Suarez Romero [Tue, 23 Jul 2019 11:20:00 +0000 (11:20 +0000)]
docs: update calendar, add news item and link release notes for 19.1.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
5 years agodocs: add sha256 checksums for 19.1.3
Juan A. Suarez Romero [Tue, 23 Jul 2019 11:18:10 +0000 (11:18 +0000)]
docs: add sha256 checksums for 19.1.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 33e57d0ace83e4f5deab0211474cd84607878024)

5 years agodocs: add release notes for 19.1.3
Juan A. Suarez Romero [Tue, 23 Jul 2019 11:07:52 +0000 (11:07 +0000)]
docs: add release notes for 19.1.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 09a1b2bdbab20635888b3b226bd1e9a8e31a75ec)

5 years agolima/ppir: fix branch codegen register encode
Erico Nunes [Mon, 22 Jul 2019 23:04:30 +0000 (01:04 +0200)]
lima/ppir: fix branch codegen register encode

The branch instruction has 6 bits per register operand which allows it
to specify a component in the register.
Fix codegen so that it outputs the right component, otherwise it always
outputs the x component.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agolima/ppir: fix debug logs in regalloc
Erico Nunes [Sun, 21 Jul 2019 22:55:48 +0000 (00:55 +0200)]
lima/ppir: fix debug logs in regalloc

The macros already prepend "ppir: ", remove them from the actual strings
so it doesn't appear duplicated.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agolima/ppir: fix alignment on regalloc spilling loads
Erico Nunes [Sun, 21 Jul 2019 22:55:24 +0000 (00:55 +0200)]
lima/ppir: fix alignment on regalloc spilling loads

The spilling code spills entire vec4 registers regardless of the
components used by the spilled uses.
The inserted stores code force the 4 components, but these loads were
using a variable number of components, causing bugs on loading the
spilled registers.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agoradv: fix dumping disassembly with RADV_DEBUG=shaders
Samuel Pitoiset [Tue, 23 Jul 2019 07:55:24 +0000 (09:55 +0200)]
radv: fix dumping disassembly with RADV_DEBUG=shaders

Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info flag set")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agost/nir: use asprintf() wrapper to fix MSVC issues
Eric Engestrom [Fri, 19 Jul 2019 21:13:21 +0000 (22:13 +0100)]
st/nir: use asprintf() wrapper to fix MSVC issues

Fixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoutil: add asprintf() wrapper for MSVC
Eric Engestrom [Fri, 19 Jul 2019 21:09:34 +0000 (22:09 +0100)]
util: add asprintf() wrapper for MSVC

Fixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogallium: remove boolean from state tracker APIs
Ilia Mirkin [Thu, 4 Jul 2019 18:41:00 +0000 (14:41 -0400)]
gallium: remove boolean from state tracker APIs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agogallium: switch boolean -> bool at the interface definitions
Ilia Mirkin [Thu, 4 Jul 2019 15:41:41 +0000 (11:41 -0400)]
gallium: switch boolean -> bool at the interface definitions

This is a relatively minimal change to adjust all the gallium interfaces
to use bool instead of boolean. I tried to avoid making unrelated
changes inside of drivers to flip boolean -> bool to reduce the risk of
regressions (the compiler will much more easily allow "dirty" values
inside a char-based boolean than a C99 _Bool).

This has been build-tested on amd64 with:

Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d
                 vc4 i915 svga virgl swr panfrost iris lima kmsro
Gallium st:      mesa xa xvmc xvmc vdpau va

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agost/nir: fix arb fragment stage conversion
Dave Airlie [Tue, 23 Jul 2019 00:40:05 +0000 (10:40 +1000)]
st/nir: fix arb fragment stage conversion

The comment even justifies the wrongness wrongly.

We should be translating to pipe values properly here or else
fragment maps to tess ctrl.

Fixes: 3d7611e9a6c ("st/nir: use NIR for asm programs")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi: fix warning: ‘ret’ may be used uninitialized
Marek Olšák [Mon, 22 Jul 2019 19:59:49 +0000 (15:59 -0400)]
radeonsi: fix warning: ‘ret’ may be used uninitialized

Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agotgsi: fix warning: ‘interp’ may be used uninitialized
Marek Olšák [Mon, 22 Jul 2019 19:59:22 +0000 (15:59 -0400)]
tgsi: fix warning: ‘interp’ may be used uninitialized

Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agogallivm: fix warning: ‘op’ may be used uninitialized
Marek Olšák [Mon, 22 Jul 2019 19:58:58 +0000 (15:58 -0400)]
gallivm: fix warning: ‘op’ may be used uninitialized

Reviewed-by: Dave Airlie <airlied@redhat.com>
5 years agoiris: Support storage images that have matching typed formats for reads
Kenneth Graunke [Mon, 22 Jul 2019 23:53:32 +0000 (16:53 -0700)]
iris: Support storage images that have matching typed formats for reads

Even if we don't directly support typed reads on a format, we can often
translate them to a reasonable matching format.  Advertise those too.

5 years agoiris: Stop advertising MSAA storage images by mistake
Kenneth Graunke [Mon, 22 Jul 2019 23:18:40 +0000 (16:18 -0700)]
iris: Stop advertising MSAA storage images by mistake

st_extensions.c sets const->MaxImageSamples (GL_MAX_IMAGE_SAMPLES) by
looping over [16, 15, .. 1x] MSAA modes, and RGBA/BGRA/ARGB/ABGR 8888
color formats, calling pipe->is_format_supported() for each, with
the usage set to PIPE_BIND_SHADER_IMAGE.  If any are supported, it
selects that number of samples.

We were checking if sample_count <= 1, which meant that we were getting
a value of 1x MSAA, rather than the expected 0x (feature doesn't exist).

But, only on Icelake because Gen11 adds support for typed read messages
for R8G8B8A8_UNORM.  The lack of typed read messages for these formats
was tricking the check on Gen9 to say no correctly.  This caused some
Icelake conformance failures, because we don't implement this feature.

Just check for sample_count == 0 instead.

5 years agoegl: Only expose 565 pbuffer configs if X can export them as DRI3 images
Kenneth Graunke [Thu, 18 Jul 2019 00:03:17 +0000 (17:03 -0700)]
egl: Only expose 565 pbuffer configs if X can export them as DRI3 images

Glamor in xorg-server 1.20 cannot expose 16bpp pixmaps when running in
the usual 24bpp mode.  This meant our 565 pbuffer configs would
ultimately fail to create a backing pixmap, leading to crashes.

To hack around this, make a 16bpp pixmap and try and export it.
If it works, expose the configs.  Otherwise, just skip them.

This also disables them on DRI2.  These configs were only added to pass
conformance requirements, and I doubt anybody cares about testing out
565 pbuffer visuals on DRI2-only drivers.

v2: Don't leak the fds (caught by Eric Anholt)
v3: Don't free(fds), it's not malloc'd

Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.")
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoegl: Make the 565 pbuffer-only config single buffered.
Kenneth Graunke [Sat, 23 Mar 2019 01:00:55 +0000 (18:00 -0700)]
egl: Make the 565 pbuffer-only config single buffered.

In commit dacb11a585face5ca179c34cfc588a71a425c1e0, Eric found the first
matching 565 pbuffer config, and stopped.  Our double-buffered configs
come first in the list, so we added that, making a pbuffer-only config
that claimed to be double buffered.  This doesn't make sense, since
pixmaps/pbuffers are fundamentally not double buffered.

When using that config, every call to eglCreatePbufferSurface would fail
with EGL_BAD_MATCH.  The call chain looks like this:

   - eglCreatePbufferSurface
   - dri3_create_pbuffer_surface
   - dri3_create_surface
   - dri2_get_dri_config

which eventually does:

   const bool double_buffer = surface_type == EGL_WINDOW_BIT;

and then fails to find a matching config, because it ends up looking
for a single-buffered config - and there aren't any.

To fix this, make the 565 pbuffer config single-buffered.  This fixes
at least 51 dEQP-EGL.* tests.

Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoegl: Quiet warning about front buffer rendering for pixmaps/pbuffers
Kenneth Graunke [Fri, 28 Jun 2019 17:11:01 +0000 (10:11 -0700)]
egl: Quiet warning about front buffer rendering for pixmaps/pbuffers

pbuffer configs cause a million of these warnings to trigger, but
when using pixmaps or buffers, there is only one surface, so this
warning doesn't make much sense.  Retain it for window surfaces for now.

Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomesa: Fix ReadBuffers with pbuffers
Kenneth Graunke [Fri, 28 Jun 2019 19:56:38 +0000 (12:56 -0700)]
mesa: Fix ReadBuffers with pbuffers

pbuffers are internally single-buffered.  Marek fixed DrawBuffers to
handle this case, but we need to fix ReadBuffers too.  Otherwise,
pretty much every conformance test fails because glReadPixels breaks.

v2: Refactor the switch into a helper (suggested by Eric Anholt)

Fixes: 35294f2eca8 ("mesa: fix pbuffers because internally they are front buffers")
Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomesa: fix assertion failure in TexImage
Marek Olšák [Mon, 22 Jul 2019 19:28:42 +0000 (15:28 -0400)]
mesa: fix assertion failure in TexImage

Check the assertion after error checking.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111194

Fixes: 9dd1f7cec01 ("mesa: pass gl_texture_object as arg to not depend on state")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agonir: Remove a bunch of large stack arrays
Jason Ekstrand [Mon, 22 Jul 2019 05:51:24 +0000 (00:51 -0500)]
nir: Remove a bunch of large stack arrays

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
5 years agointel/fs: Stop stack allocating large arrays
Jason Ekstrand [Mon, 22 Jul 2019 05:28:27 +0000 (00:28 -0500)]
intel/fs: Stop stack allocating large arrays

Normally, we haven't worried too much about stack sizes as Linux tends
to be fairly friendly towards large stacks.  However, when running DXVK
apps under wine, we're suddenly subject to Windows' more stringent stack
limitations and can run out of space more easily.  In particular, some
of the shaders in Elite Dangerous: Horizons have quite a few registers
and the arrays in split_virtual_grfs are large enough to blow a 1 MiB
stack leading to crashes during shader compilation.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108662
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
5 years agoegl/android: Update color_buffers querying for buffer age
Nataraj Deshpande [Fri, 19 Jul 2019 15:44:13 +0000 (08:44 -0700)]
egl/android: Update color_buffers querying for buffer age

color_buffers[] is currently hard coded to 3 for android which fails
in droid_window_dequeue_buffer when ANativeWindow creates color_buffers
>3 while querying buffer age during dEQP partial_update tests on chromeOS.

The patch removes static color_buffers[], queries for MIN_UNDEQUEUED_BUFFERS,
sets native window buffer count and allocates the correct number of
color_buffers as per android.

Fixes dEQP-EGL.functional.partial_update* tests on chromebooks with
enabling EGL_KHR_partial_update.

v2: update comment instead of removing (Eric Engestrom)
v3: change static array to dynamic allocated color_buffers
    querying MIN_UNDEQUEUED_BUFFERS (Chia-I Wu olv@chromium.org)

Fixes: 2acc69da8ce "EGL/Android: Add EGL_EXT_buffer_age extension"
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
5 years agointel/compiler: Use nir_opt_conditional_discard
Caio Marcelo de Oliveira Filho [Fri, 19 Jul 2019 17:34:53 +0000 (10:34 -0700)]
intel/compiler: Use nir_opt_conditional_discard

anv vkpipeline-db results for SKL:

total instructions in shared programs: 3622461 -> 3611281 (-0.31%)
instructions in affected programs: 396452 -> 385272 (-2.82%)
helped: 2062
HURT: 1

total cycles in shared programs: 1458144669 -> 1458105320 (<.01%)
cycles in affected programs: 4171830 -> 4132481 (-0.94%)
helped: 1874
HURT: 180

total loops in shared programs: 2437 -> 2437 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 8745 -> 8748 (0.03%)
spills in affected programs: 8 -> 11 (37.50%)
helped: 1
HURT: 1

total fills in shared programs: 23392 -> 23395 (0.01%)
fills in affected programs: 8 -> 11 (37.50%)
helped: 1
HURT: 1

LOST:   0
GAINED: 1

No changes to shader-db on i965 or iris.  The glsl compiler already
does a similar optimization.

Improvement suggested by Daniel Schürmann.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopan/decode: Disable magic divisor debugging
Alyssa Rosenzweig [Mon, 22 Jul 2019 15:34:26 +0000 (08:34 -0700)]
pan/decode: Disable magic divisor debugging

Memory corruption (for both legitimate and illegitimate reasons) causes
this to hang pantrace.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Report spills:fills to shader-db
Alyssa Rosenzweig [Mon, 22 Jul 2019 13:32:48 +0000 (06:32 -0700)]
pan/midgard: Report spills:fills to shader-db

Route this info through so we can track how we're doing on register
spilling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Reenable pipeline register creation
Alyssa Rosenzweig [Fri, 19 Jul 2019 23:27:39 +0000 (16:27 -0700)]
panfrost/midgard: Reenable pipeline register creation

This was disabled to permit regression-free RA work. Now that the spill
code is in place, we can reenable, with some caveats about efficacy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Report tls_size
Alyssa Rosenzweig [Fri, 19 Jul 2019 23:23:52 +0000 (16:23 -0700)]
panfrost/midgard: Report tls_size

Pipe through the number of bytes of spilled memory used from the
compiler into the main driver, where it will be used to allocate the
Thread Local Storage buffer.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Set `initialized` in more cases
Alyssa Rosenzweig [Fri, 19 Jul 2019 23:11:27 +0000 (16:11 -0700)]
panfrost: Set `initialized` in more cases

Indirect linear writes were not being marked as initialized, causing the
back blit to be dropped, breaking the listed tests.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/ci: Update expectations
Alyssa Rosenzweig [Fri, 19 Jul 2019 22:53:25 +0000 (15:53 -0700)]
panfrost/ci: Update expectations

We've fixed some shader tests.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Promote to *move*, not rewrite for non-SSA
Alyssa Rosenzweig [Fri, 19 Jul 2019 22:51:51 +0000 (15:51 -0700)]
panfrost/midgard: Promote to *move*, not rewrite for non-SSA

Fixes promoted uniform loads to registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Dump MIR of RA failure
Alyssa Rosenzweig [Fri, 19 Jul 2019 22:38:49 +0000 (15:38 -0700)]
panfrost/midgard: Dump MIR of RA failure

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard; Dump successor graph when printing MIR
Alyssa Rosenzweig [Fri, 19 Jul 2019 21:21:35 +0000 (14:21 -0700)]
pan/midgard; Dump successor graph when printing MIR

We just use the pointers of the midgard_block*, which is crude, but it
gets the point across and will help debug successor related issues.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Remove debug statement
Alyssa Rosenzweig [Fri, 19 Jul 2019 21:20:43 +0000 (14:20 -0700)]
pan/midgard: Remove debug statement

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Implement register spilling
Alyssa Rosenzweig [Fri, 19 Jul 2019 20:21:11 +0000 (13:21 -0700)]
panfrost/midgard: Implement register spilling

Now that we run RA in a loop, before each iteration after a failed
allocation we choose a spill node and spill it to Thread Local Storage
using st_int4/ld_int4 instructions (for spills and fills respectively).

This allows us to compile complex shaders that normally would not fit
within the 16 work register limits, although it comes at a fairly steep
performance penalty.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Add mir_has_arg helper
Alyssa Rosenzweig [Fri, 19 Jul 2019 19:14:43 +0000 (12:14 -0700)]
panfrost/midgard: Add mir_has_arg helper

Helps scan the MIR for uses of an index.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Check write-before-read in liveness analysis
Alyssa Rosenzweig [Fri, 19 Jul 2019 19:11:09 +0000 (12:11 -0700)]
panfrost/midgard: Check write-before-read in liveness analysis

If we write to an index before reading it, the old copy we're checking
liveness for isn't live in this block, even if it does get read later.
Fixes abnormally high register pressure in shaders with loops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard/disasm: Check for certain tag errors
Alyssa Rosenzweig [Fri, 19 Jul 2019 18:02:56 +0000 (11:02 -0700)]
panfrost/midgard/disasm: Check for certain tag errors

Midgard bundles contain a tag, as well as a copy of the tag of the next
bundle to facilitate prefetch. Do some simple static analysis to detect
certain tag errors (particularly on shaders without branching).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Add OP_IS_CSEL helper
Alyssa Rosenzweig [Fri, 19 Jul 2019 17:51:08 +0000 (10:51 -0700)]
pan/midgard: Add OP_IS_CSEL helper

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Add mir_rewrite_index_src_single helper
Alyssa Rosenzweig [Fri, 19 Jul 2019 17:50:34 +0000 (10:50 -0700)]
pan/midgard: Add mir_rewrite_index_src_single helper

Rather than rewriting an index away across the whole block, we expose
finer (per-instruction) granularity for rewrites.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Ignore inline_constant in liveness
Alyssa Rosenzweig [Fri, 19 Jul 2019 16:11:56 +0000 (09:11 -0700)]
pan/midgard: Ignore inline_constant in liveness

It doesn't make any sense to look at it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost/midgard: Implement load/store scratch opcodes
Alyssa Rosenzweig [Fri, 19 Jul 2019 14:50:48 +0000 (07:50 -0700)]
panfrost/midgard: Implement load/store scratch opcodes

These are used to load/store from Thread Local Storage, which is memory
allocated per-thread (corresponding to ctx->scratchpad in the command
stream) and used for register spilling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midg/disasm: Check for int varying ops
Alyssa Rosenzweig [Wed, 17 Jul 2019 20:11:26 +0000 (13:11 -0700)]
pan/midg/disasm: Check for int varying ops

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Remove "aliasing"
Alyssa Rosenzweig [Tue, 16 Jul 2019 21:40:32 +0000 (14:40 -0700)]
pan/midgard: Remove "aliasing"

It was a crazy idea that didn't pan out. We're better served by a good
copyprop pass. It's also unused now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Promote uniform registers late
Alyssa Rosenzweig [Tue, 16 Jul 2019 21:10:08 +0000 (14:10 -0700)]
panfrost: Promote uniform registers late

Rather than creating either a load or a uniform register read with a
fixed beginning offset, we always create a load and then promote to a
uniform register later. This will allow us to promote in a register
pressure aware manner.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Call scheduler/RA in a loop
Alyssa Rosenzweig [Tue, 16 Jul 2019 16:45:11 +0000 (09:45 -0700)]
pan/midgard: Call scheduler/RA in a loop

This will allow us to insert instructions as a result of register
allocation, permitting spilling to be implemented. As a side effect,
with the assert commented out this would fix a bunch of glamor crashes
(due to RA failures) so MATE becomes useable.

Ideally we'll have scheduling or RA actually sorted out before the
branch point but if not this gives us a one-line out to get X working...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Remove custom register selection callback
Alyssa Rosenzweig [Tue, 16 Jul 2019 16:16:39 +0000 (09:16 -0700)]
pan/midgard: Remove custom register selection callback

What we have is equivalent to the default callback; let's use that.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoradv: fix crash in vkCmdClearAttachments with unused attachment
Samuel Pitoiset [Mon, 22 Jul 2019 08:12:48 +0000 (10:12 +0200)]
radv: fix crash in vkCmdClearAttachments with unused attachment

depth_stencil_attachment and/or ds_resolve attachment can be NULL.

This fixes crashes with
dEQP-VK.renderpass.suballocation.unused_clear_attachments.*

Cc: 19.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoi965: free object labels when deleting
Sergii Romantsov [Wed, 17 Jul 2019 15:59:28 +0000 (18:59 +0300)]
i965: free object labels when deleting

Some leaks detected with GL_KHR_debug on i965.

CC: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoradv/gfx10: update descriptors for inline uniform blocks
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:33 +0000 (15:51 +0200)]
radv/gfx10: update descriptors for inline uniform blocks

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv/gfx10: emit the GS NGG prologue before the nested barrier
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:32 +0000 (15:51 +0200)]
radv/gfx10: emit the GS NGG prologue before the nested barrier

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv/gfx10: do not allocate space for the ZPASS_DONE bug
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:31 +0000 (15:51 +0200)]
radv/gfx10: do not allocate space for the ZPASS_DONE bug

GFX10 isn't affected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv/gfx10: do not set ELEMENT_SIZE for buffer descriptors
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:30 +0000 (15:51 +0200)]
radv/gfx10: do not set ELEMENT_SIZE for buffer descriptors

This field doesn't exist.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: clean up fill_geom_tess_rings()
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:29 +0000 (15:51 +0200)]
radv: clean up fill_geom_tess_rings()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: change a bunch of >= GFX9 to == GFX9
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:28 +0000 (15:51 +0200)]
radv: change a bunch of >= GFX9 to == GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac/nir: do not clamp shadow reference on GFX10
Samuel Pitoiset [Thu, 18 Jul 2019 13:51:27 +0000 (15:51 +0200)]
ac/nir: do not clamp shadow reference on GFX10

RadeonSI only uses Z32_FLOAT_CLAMP for upgraded depth textures
on GFX10 and RADV doesn't promotes Z16 or Z24.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: move nir_opt_conditional_discard out of optimization loop
Daniel Schürmann [Sat, 20 Jul 2019 17:21:14 +0000 (19:21 +0200)]
radv: move nir_opt_conditional_discard out of optimization loop

This late optimization pass is only affected by nir_opt_if() and handles all cases
in a single pass. It's enough to call it once after the optimization loop.
No changes on vkpipeline-db.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agov3d: fill logicop_func in the fragment shader key when precompiling shaders
Iago Toral Quiroga [Fri, 19 Jul 2019 07:54:54 +0000 (09:54 +0200)]
v3d: fill logicop_func in the fragment shader key when precompiling shaders

Since logicop_func 0 is PIPE_LOGIOP_CLEAR, we were trigger lowerinng
of logic ops on precompiled shaders, which we don't want to do. Also, this
had the side effect of making shader-db crash, as during this lowering we
would try to read the color format swizzle information from the fragment shader
key that we don't populate in precompiled shaders because right now we only
need it when logic operations are enabled.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agov3d: Avoid scheduling an instruction that stalls waiting for SFU retval
Jose Maria Casanova Crespo [Tue, 9 Jul 2019 17:23:25 +0000 (19:23 +0200)]
v3d: Avoid scheduling an instruction that stalls waiting for SFU retval

If we detect that a scheduling candidate will stall because having a
register source that is the written by the SFU unit in the previous
instruction we reduce its priority so any non stalling operation would
be chosen.

The latency of SFU operations is defined as 2. So they would be scheduled
earlier if other candidates have the same priority.

Finally we won't merge instructions that stall to a previously chosen one.
As the result of the previous one would be waiting for an extra cycle.

Although shader-db result show that instruction are hurt with an increase
of 0.35% the sum of instructions + stalls is reduced a 0.52%. And
the total of sfu-stalls is reduced a 63.51%. It implies also a small
increase in the max-temps metric because of scheduling earlier SFU
operations.

total instructions in shared programs: 9102719 -> 9117851 (0.17%)
instructions in affected programs: 4324628 -> 4339760 (0.35%)
helped: 4162
HURT: 12128
helped stats (abs) min: 1 max: 10 x̄: 1.28 x̃: 1
helped stats (rel) min: 0.09% max: 4.76% x̄: 0.66% x̃: 0.51%
HURT stats (abs)   min: 1 max: 27 x̄: 1.69 x̃: 1
HURT stats (rel)   min: 0.05% max: 7.69% x̄: 0.87% x̃: 0.68%
95% mean confidence interval for instructions value: 0.90 0.96
95% mean confidence interval for instructions %-change: 0.47% 0.50%
Instructions are HURT.

total max-temps in shared programs: 1327728 -> 1327812 (<.01%)
max-temps in affected programs: 4730 -> 4814 (1.78%)
helped: 61
HURT: 134
helped stats (abs) min: 1 max: 2 x̄: 1.08 x̃: 1
helped stats (rel) min: 2.70% max: 13.33% x̄: 4.89% x̃: 4.17%
HURT stats (abs)   min: 1 max: 3 x̄: 1.12 x̃: 1
HURT stats (rel)   min: 1.54% max: 20.00% x̄: 6.10% x̃: 5.26%
95% mean confidence interval for max-temps value: 0.28 0.58
95% mean confidence interval for max-temps %-change: 1.80% 3.52%
Max-temps are HURT.

total sfu-stalls in shared programs: 99551 -> 36324 (-63.51%)
sfu-stalls in affected programs: 95029 -> 31802 (-66.53%)
helped: 25882
HURT: 0
helped stats (abs) min: 1 max: 27 x̄: 2.44 x̃: 2
helped stats (rel) min: 5.26% max: 100.00% x̄: 79.86% x̃: 100.00%
95% mean confidence interval for sfu-stalls value: -2.47 -2.42
95% mean confidence interval for sfu-stalls %-change: -80.18% -79.54%
Sfu-stalls are helped.

total inst-and-stalls in shared programs: 9202270 -> 9154175 (-0.52%)
inst-and-stalls in affected programs: 5618516 -> 5570421 (-0.86%)
helped: 22728
HURT: 855
helped stats (abs) min: 1 max: 31 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.07% max: 16.67% x̄: 1.14% x̃: 0.92%
HURT stats (abs)   min: 1 max: 5 x̄: 1.25 x̃: 1
HURT stats (rel)   min: 0.12% max: 5.26% x̄: 1.24% x̃: 0.86%
95% mean confidence interval for inst-and-stalls value: -2.07 -2.01
95% mean confidence interval for inst-and-stalls %-change: -1.07% -1.05%
Inst-and-stalls are helped.

v2: Rename v3d_qpu_generates_sfu_stalls to v3d_qpu_instr_is_sfu (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agov3d: add shader-db stat to count SFU stalls
Jose Maria Casanova Crespo [Tue, 2 Jul 2019 16:31:09 +0000 (18:31 +0200)]
v3d: add shader-db stat to count SFU stalls

SFU operations have a latency of 2 cicles, so if their results
are used in the following cycle to a SFU instruction, the GPU
stalls for an extra cycle until the result is available.

This adds the number of stalls to the shader-db debug mode and
sum of instruction + stalls to evaluate optimizations to schedule
instructions that avoid generating sfu-stalls.

v2: Rename v3d_qpu_generates_sfu_stalls to v3d_qpu_instr_is_sfu (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>