constraints.md (BC): Only allow -1 operands.

* config/i386/constraints.md (BC): Only allow -1 operands.
* config/i386/sse.md (mov<mode>_internal): Add (v,C) alternative.
Add "enabled" attribute.  Update XI mode attribute calculation.
* config/i386/i386.md (*movxi_internal_avx512f): Add (v,C) alternative.
(*movoi_internal_avx): Update XI mode attribute calculation.
(*movti_internal): Ditto.

testsuite/ChangeLog:

* gcc.target/i386/avx256-unaligned-load-1.c: Update scan strings.
* gcc.target/i386/avx256-unaligned-store-1.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-2.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-3.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-4.c: Ditto.

From-SVN: r235693

re PR bootstrap/70704 (AIX bootstrap comparison failure)

PR bootstrap/70704
* configure.ac (--enable-stage1-checking): Add missing
--enable-checking=.
* configure: Regenerated.

From-SVN: r235692

sh.md (push, [...]): Remove constraints.

gcc/
* config/sh/sh.md (push, pop, ic_invalidate_line, cstoresi4, cstoredi4,
cstoresf4, cstoredf4, fix_truncsfsi2): Remove constraints.

From-SVN: r235691

rs6000.c (altivec_expand_lv_builtin): Do not use switch statement on instruction code.

* config/rs6000/rs6000.c (altivec_expand_lv_builtin): Do not use switch
statement on instruction code.  Remove trailing spaces.
(altivec_expand_stv_builtin): Likewise.

From-SVN: r235690

sh.h (TARGET_SH4): Remove and use default implementation.

gcc/
* config/sh/sh.h (TARGET_SH4): Remove and use default implementation.
(TARGET_FPU_DOUBLE): Simplify.
(BASE_ARG_REG, DOUBLE_TYPE_SIZE, OPTIMIZE_MODE_SWITCHING): Replace
'TARGET_SH4 || TARGET_SH2A_DOUBLE' conditions with 'TARGET_FPU_DOUBLE'.
* config/sh/sh.c: Replace 'TARGET_SH4 || TARGET_SH2A_DOUBLE' conditions
with 'TARGET_FPU_DOUBLE'.
* config/sh/sh.md: Likewise.

From-SVN: r235689

linux.h (SH_DIV_STRATEGY_DEFAULT, [...]): Remove.

gcc/
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT,
SH_DIV_STR_FOR_SIZE): Remove.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT,
SH_DIV_STR_FOR_SIZE): Remove.

From-SVN: r235688

predicates.md (any_register_operand, [...]): Delete.

gcc/
* config/sh/predicates.md (any_register_operand, zero_extend_operand,
logical_reg_operand): Delete.
(arith_operand, arith_reg_dest, arith_or_int_operand, cmpsi_operand,
arith_reg_or_0_operand, arith_reg_or_0_or_1_operand, logical_operand,
logical_and_operand, movsrc_no_disp_mem_operand): Rewrite using
match_operand and match_test.
(sh_const_vec, sh_1el_vec): Remove redundant checks.  Declare local
variables on their first use.  Return bool values.
* config/sh/sh.h (LOAD_EXTEND_OP): Update comment.
* config/sh/sh.md (andsi3, iorsi3): Use arith_reg_dest for result and
arith_reg_operand for input operand.  Remove empty constraints.
(xorsi3): Delete.
(*xorsi3_compact): Rename to xorsi3.
(zero_extend<mode>si2): Use arith_reg_operand for input operand.
(*zero_extend<mode>si2_disp_mem): Update comment.
(mov_nop): Delete.

From-SVN: r235687

Daily bump.

From-SVN: r235686

* zh_CN.po: Update.

From-SVN: r235681

* sv.po: Update.

From-SVN: r235679

Make-lang.in (ACATSCMD): New variable.

ada/
* gcc-interface/Make-lang.in (ACATSCMD): New variable.
(check-acats): Use it.
(check_acats_targets): Likewise.
testsuite/
* ada/acats/run_acats: Rename into...
* ada/acats/run_acats.sh: ...this.  Only export BASE variable.
* ada/acats/run_all.sh: Remove redundant test.
(target_run): Move around.
(target_gnatchop): Use newly built executable.
(target_gnatmake): Likewise.
Check that the compilation of impbit succeeds.

From-SVN: r235678

config.guess: Revert r235676.

/
* config.guess: Revert r235676.
* config.sub: Revert r235676.

libjava/
* classpath/config.guess: Revert r235676.
* classpath/config.sub: Revert r235676.

From-SVN: r235677

config.guess: Remove SH5 support.

/
* config.guess:  Remove SH5 support.
* config.sub: Likewise.
* configure: Likewise.
* configure.ac: Likewise.

config/
* picflag.m4:  Remove SH5 support.

gcc/
* config/sh/t-sh: Remove SH5 support.
* config.gcc: Likewise.
* configure: Likewise.

contrib/
* compare-all-tests: Remove SH5 support.
* config-list.mk: Likewise.

libada/
* configure: Remove SH5 support.

libgcc/
* config.host: Remove SH5 support.
* configure: Likewise.

libiberty/
* configure: Remove SH5 support.

libjava/
* classpath/config.guess: Remove SH5 support.
* classpath/config.sub: Likewise.

From-SVN: r235676

Handle -fcilkplus in Mac OS X LINK_COMMAND_SPEC

* config/darwin.h (LINK_COMMAND_SPEC_A): Handle -fcilkplus.

From-SVN: r235675

sh.c (register_sh_passes, [...]): Remove TARGET_SH1 checks.

gcc/
* config/sh/sh.c (register_sh_passes, sh_option_override,
sh_print_operand, prepare_move_operands,
sh_can_follow_jump): Remove TARGET_SH1 checks.
* config/sh/sh.h (TARGET_VARARGS_PRETEND_ARGS, VALID_REGISTER_P,
PROMOTE_MODE): Likewise.
* config/sh/sh.md (adddi3, addsi3, subdi3, subsi3, andsi3,
movdi): Likewise.

From-SVN: r235674

thunk3.C: Remove SH5 checks.

testsuite/
* g++.old-deja/g++.jason/thunk3.C: Remove SH5 checks.
* gcc.dg/20021029-1.c: Likewise.
* gcc.target/sh/attr-isr-trap_exit.c: Likewise.
* gcc.target/sh/attr-isr-trapa.c: Likewise.
* gcc.target/sh/cmpstr.c: Likewise.
* gcc.target/sh/cmpstrn.c: Likewise.
* gcc.target/sh/memset.c: Likewise.
* gcc.target/sh/pr21255-2-mb.c: Likewise.
* gcc.target/sh/pr21255-2-ml.c: Likewise.
* gcc.target/sh/pr39423-1.c: Likewise.
* gcc.target/sh/pr49468-di.c: Likewise.
* gcc.target/sh/pr49468-si.c: Likewise.
* gcc.target/sh/pr49880-1.c: Likewise.
* gcc.target/sh/pr49880-2.c: Likewise.
* gcc.target/sh/pr49880-3.c: Likewise.
* gcc.target/sh/pr50751-1.c: Likewise.
* gcc.target/sh/pr50751-4.c: Likewise.
* gcc.target/sh/pr50751-7.c: Likewise.
* gcc.target/sh/pr51244-1.c: Likewise.
* gcc.target/sh/pr51244-10.c: Likewise.
* gcc.target/sh/pr51244-11.c: Likewise.
* gcc.target/sh/pr51244-12.c: Likewise.
* gcc.target/sh/pr51244-13.c: Likewise.
* gcc.target/sh/pr51244-14.c: Likewise.
* gcc.target/sh/pr51244-17.c: Likewise.
* gcc.target/sh/pr51244-18.c: Likewise.
* gcc.target/sh/pr51244-19.c: Likewise.
* gcc.target/sh/pr51244-4.c: Likewise.
* gcc.target/sh/pr51244-5.c: Likewise.
* gcc.target/sh/pr51244-7.c: Likewise.
* gcc.target/sh/pr51244-8.c: Likewise.
* gcc.target/sh/pr51244-9.c: Likewise.
* gcc.target/sh/pr51697.c: Likewise.
* gcc.target/sh/pr52483-1.c: Likewise.
* gcc.target/sh/pr52483-2.c: Likewise.
* gcc.target/sh/pr52483-3.c: Likewise.
* gcc.target/sh/pr52483-5.c: Likewise.
* gcc.target/sh/pr52933-1.c: Likewise.
* gcc.target/sh/pr52933-2.c: Likewise.
* gcc.target/sh/pr52933-3.c: Likewise.
* gcc.target/sh/pr53568-1.c: Likewise.
* gcc.target/sh/pr53976-1.c: Likewise.
* gcc.target/sh/pr53988-1.c: Likewise.
* gcc.target/sh/pr53988.c: Likewise.
* gcc.target/sh/pr54089-1.c: Likewise.
* gcc.target/sh/pr54089-6.c: Likewise.
* gcc.target/sh/pr54089-7.c: Likewise.
* gcc.target/sh/pr54089-8.c: Likewise.
* gcc.target/sh/pr54089-9.c: Likewise.
* gcc.target/sh/pr54236-1.c: Likewise.
* gcc.target/sh/pr54236-2.c: Likewise.
* gcc.target/sh/pr54236-3.c: Likewise.
* gcc.target/sh/pr54236-4.c: Likewise.
* gcc.target/sh/pr54386.c: Likewise.
* gcc.target/sh/pr54602-1.c: Likewise.
* gcc.target/sh/pr54685.c: Likewise.
* gcc.target/sh/pr54760-1.c: Likewise.
* gcc.target/sh/pr54760-2.c: Likewise.
* gcc.target/sh/pr54760-3.c: Likewise.
* gcc.target/sh/pr54760-4.c: Likewise.
* gcc.target/sh/pr54760-5.c: Likewise.
* gcc.target/sh/pr54760-6.c: Likewise.
* gcc.target/sh/pr55146.c: Likewise.
* gcc.target/sh/pr55160.c: Likewise.
* gcc.target/sh/pr59278.c: Likewise.
* gcc.target/sh/pr59401-1.c: Likewise.
* gcc.target/sh/pr59533-1.c: Likewise.
* gcc.target/sh/pr63260.c: Likewise.
* gcc.target/sh/pragma-isr-trap-exit.c: Likewise.
* gcc.target/sh/pragma-isr-trapa.c: Likewise.
* gcc.target/sh/strlen.c: Likewise.
* gcc.target/sh/torture/pr30807.c: Likewise.
* gcc.target/sh/torture/pr34777.c: Likewise.
* gcc.target/sh/torture/pr64652.c: Likewise.
* gcc.target/sh/torture/pr65505.c: Likewise.
* gcc.target/sh/torture/pragma-isr.c: Likewise.
* gcc.target/sh/torture/pragma-isr2.c: Likewise.

From-SVN: r235673

[RS6000] Allow saving of fixed regs.

As I noted a long time ago in the comment on fixed_reg_p, the real
problem with saving fixed/global regs is that exception frame
unwinding might restore them.  So don't emit eh_frame info for any
such reg, and the unwinder won't restore them.

Also, tidy rs6000_savres_strategy.  Delaying some checks means we
won't iterate over regs quite so often.

* config/rs6000/rs6000.c (rs6000_savres_strategy): Force inline
restoring when fixed_reg_p, but allow out-of-line or stmw save.
Check for user regs later to avoid unnecessary looping over regs.
Merge user reg check with non-saved reg check.  Don't force
inline VR restore when static chain used.
(rs6000_frame_related): Omit eh_frame info for user regs when
saving.
(fixed_regs_p): Delete.

From-SVN: r235672

[RS6000] Split SAVRES_STRATEGY

No functional change here.  A single bit becomes two bits, which
always have the same value at the moment.

* config/rs6000/rs6000.c (SAVRES_MULTIPLE): Replace with..
(SAVE_STRATEGY, REST_STRATEGY): ..this.  Renumber and sort enum.
Update all uses.

From-SVN: r235671

[RS6000] PR69645, -ffixed-reg ignored

Treat -ffixed-reg as we do for global asm regs.

PR target/69645
* config/rs6000/rs6000.c (fixed_reg_p): New function.
(fixed_regs_p): Rename from global_regs_p.  Call fixed_reg_p.
Update all uses.

From-SVN: r235670

[RS6000] Simplify setting of fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]

This makes the conditions look the same as other places that deal with
RS6000_PIC_OFFSET_TABLE_REGNUM, eg. first_reg_to_save.  No functional
changes.

* config/rs6000/rs6000.c (rs6000_conditional_register_usage):
Remove redundant PIC_OFFSET_TABLE_REGNUM test.  Replace with
flag_pic test for Darwin.

From-SVN: r235669

Daily bump.

From-SVN: r235668

Goodbye REG_FREQ_CALLS_CROSSED and REG_N_THROWING_CALLS_CROSSED

* regs.h (struct reg_info_t): Delete freq_calls_crossed and
throw_calls_crossed.
(REG_FREQ_CALLS_CROSSED): Delete.
(REG_N_THROWING_CALLS_CROSSED): Delete.
* regstat.c (regstat_bb_compute_ri): Don't calculate
REG_FREQ_CALLS_CROSSED and REG_N_THROWING_CALLS_CROSSED.
(dump_reg_info): Don't print call cross frequency.
* ira.c (combine_and_move_insns): Don't set REG_FREQ_CALLS_CROSSED
and REG_N_THROWING_CALLS_CROSSED.

From-SVN: r235664

Goodbye REG_LIVE_LENGTH

* regs.h (struct reg_info_t): Delete live_length.
(REG_LIVE_LENGTH): Delete macro.
* regstat.c (regstat_bb_compute_ri): Delete artificial_uses,
local_live, local_processed and local_live_last_luid params.
Replace bb_index param with bb.  Don't set REG_LIVE_LENGTH.
Formatting fixes.
(regstat_compute_ri): Adjust for above.  Don't set
REG_LIVE_LENGTH.
(dump_reg_info): Don't print live length.
* ira.c (update_equiv_regs): Replace test of REG_LIVE_LENGTH
with test of setjmp_crosses.  Don't set REG_LIVE_LENGTH.
Localize loop_depth var.

From-SVN: r235663

re PR c++/66644 (Rejects C++11 in-class anonymous union members initialization)

/cp
2016-04-29  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/66644
* class.c (check_field_decl): Remove final int* parameter, change
the return type to bool; fix logic in order not to reject multiple
initialized fields in anonymous struct.
(check_field_decls): Adjust call.

/testsuite
2016-04-29  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/66644
* g++.dg/cpp0x/nsdmi-anon-struct1.C: New.

From-SVN: r235662

ira.c validate_equiv_mem

This function is used to validate REG_EQUIV notes generated by ira,
and to validate potential insn combines performed by ira.  The two
conditions are not exactly the same, with reload being more
restrictive.  Separate them so more combines/moves can occur.

For example, this sequence from cfgexpand.c:expand_gimple_cond
callq  _Z18update_bb_for_insnP15basic_block_def
mov    0x10(%rbx),%rdi
mov    0x0(%rip),%rbp        # x_rtl+0x34
callq  _Z9safe_as_aIP8rtx_insn7rtx_defET_PT0_
mov    %r13,%rdx
mov    %rbp,%rsi
mov    %rax,%rdi
callq  _Z18create_basic_blockP7rtx_defS0_P15basic_block_def

becomes
callq  _Z18update_bb_for_insnP15basic_block_def
mov    0x10(%rbx),%rdi
callq  _Z9safe_as_aIP8rtx_insn7rtx_defET_PT0_
mov    0x0(%rip),%rsi        # x_rtl+0x34
mov    %r13,%rdx
mov    %rax,%rdi
callq  _Z18create_basic_blockP7rtx_defS0_P15basic_block_def

* ira.c (enum valid_equiv): New.
(validate_equiv_mem): Return enum.
(update_equiv_mem): Create replacement in more cases.
(add_store_equivs): Update validate_equiv_mem call.

From-SVN: r235661

ira.c use DF infrastructure for combine_and_move_insns

This patch actually improves generated code, because REG_DEAD notes
used by the old insn scan are not always present.  On x86_64, see
gcc/wide-int-print.o:print_hex for an example of a function that is
smaller and uses one less callee saved reg.

* ira.c (combine_and_move_insns): Rather than scanning insns,
use DF infrastucture to find use and def insns.

From-SVN: r235660

ira.c combine_and_move_insns, and ordering of functions

Notes added by add_store_equivs are not used directly or indirectly by
combine_and_move_insns.  add_store_equivs can therefore run later
without affecting the output of combine_and_move_insns, and thus
add_store_equivs need not take into account potentially moved insns.
Since not all potentially combined/moved insns are in fact combined or
moved, this may allow add_store_equivs to add more REG_EQUIV notes.

grow_reg_equivs isn't needed until the reload reg_equivs array is
changed.

ira.c (combine_and_move_insns): Move invariant conditions..
(ira.c): ..to here.  Call combine_and_move_insns before
add_store_equivs.  Call grow_reg_equivs later.  Allocate
req_equiv later using max_reg_num() rather than global max_regno.
(contains_replace_regs): Delete.
(add_store_equivs): Remove contains_replace_regs test.

From-SVN: r235659

ira.c tidies: validate_equiv_mem_from_store

* ira.c (struct equiv_mem_data): New.
(equiv_mem, equiv_mem_modified): Delete static vars.
(validate_equiv_mem_from_store): Use "data" param to communicate..
(validate_equiv_mem): ..from here.

From-SVN: r235658

ira.c tidies: split update_reg_equivs

* ira.c (add_store_equivs, combine_and_move_insns): New functions,
split out from..
(update_reg_equivs): ..here.  Move allocation and freeing of
reg_equiv, and calls to grow_reg_equivs, init_alias_analysis,
end_alias_analysis to..
(ira): ..here.

From-SVN: r235657

ira.c tidies: move pdx_subregs into reg_equiv

Where pdx_subregs[regno] is used, reg_equiv[regno] is also used.

* ira.c (pdx_subregs): Delete.
(struct equivalence): Add pdx_subregs field.
(set_paradoxical_subreg): Remove pdx_subregs param.  Update
pdx_subregs access.
(update_equiv_regs): Don't create or free pdx_subregs.  Update
pdx_subregs access.

From-SVN: r235656

altivec.h: Change definitions of vec_xl and vec_xst.

[gcc]

2016-04-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/altivec.h: Change definitions of vec_xl and
vec_xst.
* config/rs6000/rs6000-builtin.def (LD_ELEMREV_V2DF): New.
(LD_ELEMREV_V2DI): New.
(LD_ELEMREV_V4SF): New.
(LD_ELEMREV_V4SI): New.
(LD_ELEMREV_V8HI): New.
(LD_ELEMREV_V16QI): New.
(ST_ELEMREV_V2DF): New.
(ST_ELEMREV_V2DI): New.
(ST_ELEMREV_V4SF): New.
(ST_ELEMREV_V4SI): New.
(ST_ELEMREV_V8HI): New.
(ST_ELEMREV_V16QI): New.
(XL): New.
(XST): New.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
descriptions for VSX_BUILTIN_VEC_XL and VSX_BUILTIN_VEC_XST.
* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Map from
TARGET_P9_VECTOR to RS6000_BTM_P9_VECTOR.
(altivec_expand_builtin): Add handling for
VSX_BUILTIN_ST_ELEMREV_<MODE> and VSX_BUILTIN_LD_ELEMREV_<MODE>.
(rs6000_invalid_builtin): Add error-checking for
RS6000_BTM_P9_VECTOR.
(altivec_init_builtins): Define builtins used to implement vec_xl
and vec_xst.
(rs6000_builtin_mask_names): Define power9-vector.
* config/rs6000/rs6000.h (MASK_P9_VECTOR): Define.
(RS6000_BTM_P9_VECTOR): Define.
(RS6000_BTM_COMMON): Include RS6000_BTM_P9_VECTOR.
* config/rs6000/vsx.md (vsx_ld_elemrev_v2di): New define_insn.
(vsx_ld_elemrev_v2df): Likewise.
(vsx_ld_elemrev_v4sf): Likewise.
(vsx_ld_elemrev_v4si): Likewise.
(vsx_ld_elemrev_v8hi): Likewise.
(vsx_ld_elemrev_v16qi): Likewise.
(vsx_st_elemrev_v2df): Likewise.
(vsx_st_elemrev_v2di): Likewise.
(vsx_st_elemrev_v4sf): Likewise.
(vsx_st_elemrev_v4si): Likewise.
(vsx_st_elemrev_v8hi): Likewise.
(vsx_st_elemrev_v16qi): Likewise.
* doc/extend.texi: Add prototypes for vec_xl and vec_xst.  Correct
grammar.

[gcc/testsuite]

2016-04-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/vsx-elemrev-1.c: New.
* gcc.target/powerpc/vsx-elemrev-2.c: New.
* gcc.target/powerpc/vsx-elemrev-3.c: New.
* gcc.target/powerpc/vsx-elemrev-4.c: New.

From-SVN: r235654

tree-ssa-threadedge.c (simplify_control_stmt_condition): Split out into ...

2016-04-29  Patrick Palka  <ppalka@gcc.gnu.org>

* tree-ssa-threadedge.c (simplify_control_stmt_condition): Split
out into ...
(simplify_control_stmt_condition_1): ... here.  Recurse into
BIT_AND_EXPRs and BIT_IOR_EXPRs.

* gcc.dg/tree-ssa/ssa-thread-14.c: New test.
* gcc.dg/tree-ssa/ssa-thread-11.c: Update expected output.

From-SVN: r235653

re PR middle-end/70626 (bogus results in 'acc parallel loop' reductions)

gcc/c-family/
PR middle-end/70626
* c-common.h (c_oacc_split_loop_clauses): Add boolean argument.
* c-omp.c (c_oacc_split_loop_clauses): Use it to duplicate
reduction clauses in acc parallel loops.

gcc/c/
PR middle-end/70626
* c-parser.c (c_parser_oacc_loop): Don't augment mask with
OACC_LOOP_CLAUSE_MASK.
(c_parser_oacc_kernels_parallel): Update call to
c_oacc_split_loop_clauses.

gcc/cp/
PR middle-end/70626
* parser.c (cp_parser_oacc_loop): Don't augment mask with
OACC_LOOP_CLAUSE_MASK.
(cp_parser_oacc_kernels_parallel): Update call to
c_oacc_split_loop_clauses.

gcc/fortran/
PR middle-end/70626
* trans-openmp.c (gfc_trans_oacc_combined_directive): Duplicate
the reduction clause in both parallel and loop directives.

gcc/testsuite/
PR middle-end/70626
* c-c++-common/goacc/combined-reduction.c: New test.
* gfortran.dg/goacc/reduction-2.f95: Add check for kernels reductions.

libgomp/
PR middle-end/70626
* testsuite/libgomp.oacc-c++/template-reduction.C: Adjust test.
* testsuite/libgomp.oacc-c-c++-common/combined-reduction.c: New test.
* testsuite/libgomp.oacc-fortran/combined-reduction.f90: New test.

From-SVN: r235651

escape: Remove previously existing analysis.

* Make-lang.in (GO_OBJS): Remove go/dataflow.o, go/escape.o.

    Reviewed-on: https://go-review.googlesource.com/18261

From-SVN: r235649

Update scan-assembler-not in PR target/70155 tests

Since PIC leads to the *movdi_internal pattern, check for nonexistence
of the *movdi_internal pattern in PR target/70155 tests only if PIC is
off.

* gcc.target/i386/pr70155-1.c: Check for nonexistence of the
*movdi_internal pattern only if PIC off.
* gcc.target/i386/pr70155-2.c: Likewise.
* gcc.target/i386/pr70155-3.c: Likewise.
* gcc.target/i386/pr70155-4.c: Likewise.
* gcc.target/i386/pr70155-5.c: Likewise.
* gcc.target/i386/pr70155-6.c: Likewise.
* gcc.target/i386/pr70155-7.c: Likewise.
* gcc.target/i386/pr70155-8.c: Likewise.
* gcc.target/i386/pr70155-15.c: Likewise.
* gcc.target/i386/pr70155-17.c: Likewise.
* gcc.target/i386/pr70155-22.c: Likewise.

From-SVN: r235647

re PR target/69810 (PowerPC64: unrecognizable insn)

        PR target/69810
        * config/rs6000/rs6000.md (EXTQI): Don't allow extension to HImode.
        (zero_extendqi<mode>2_dot): Revert earlier conversion from
        define_insn_and_split to define_insn.
        (zero_extendqi<mode>2_dot2): Same.
        (extendqi<mode>2_dot): Same.
        (extendqi<mode>2_dot2): Same.

From-SVN: r235646

Remove trailing whitespace from libstdc++-v3 files

2016-04-29  Chris Gregory  <czipperz@gmail.com>

* config/*: Remove trailing whitespace.
* src/*: Likewise.
* testsuite/tr1/*: Likewise.
* testsuite/util/*: Likewise.

From-SVN: r235645

re PR tree-optimization/70803 (gcc.dg/vect/pr56625.c FAILs)

gcc/testsuite/ChangeLog
PR tree-optimization/70803
* gcc.dg/vect/pr56625.c: Require vect_int_mult.

From-SVN: r235644

Add DW_LANG_Rust

include/
* dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
DW_LANG_Rust_old>: New constants.

From-SVN: r235643

i386.md (unspec): Add UNSPEC_PROBE_STACK.

* config/i386/i386.md (unspec): Add UNSPEC_PROBE_STACK.
(probe_stack): New expander.
(probe_stack_<mode>): New insn pattern.

From-SVN: r235642

i386.md (operations with memory inputs setting flags peephole2): Remove uneeded REG_P checks.

* config/i386/i386.md
(operations with memory inputs setting flags peephole2):
Remove uneeded REG_P checks.  Cleanup pattern generation.

From-SVN: r235641

crt1.S: Remove SH5 support.

libgcc/
* config/sh/crt1.S: Remove SH5 support.
* config/sh/crti.S: Likewise.
* config/sh/crtn.S: Likewise.
* config/sh/lib1funcs-4-300.S: Likewise.
* config/sh/lib1funcs-Os-4-200.S: Likewise.
* config/sh/lib1funcs.S: Likewise.
* config/sh/linux-unwind.h: Likewise.
* config/sh/t-sh64: Delete.

From-SVN: r235640

tree-vect-loop.c (vect_transform_loop): Fix nb_iterations_upper_bound computation for vectorized loop.

gcc/

* tree-vect-loop.c (vect_transform_loop): Fix
nb_iterations_upper_bound computation for vectorized loop.

gcc/testsuite/

* gcc.target/i386/vect-unpack-2.c (avx512bw_test): Avoid
optimization of vector loop.
* gcc.target/i386/vect-unpack-3.c: New test.
* gcc.dg/vect/vect-nb-iter-ub-1.c: New test.
* gcc.dg/vect/vect-nb-iter-ub-2.c: New test.
* gcc.dg/vect/vect-nb-iter-ub-3.c: New test.

From-SVN: r235639

re PR c/70852 (ice in warn_for_memset)

PR c/70852
* c-common.c (warn_for_memset): Check domain before accessing it.

* gcc.dg/pr70852.c: New test.

From-SVN: r235638

re PR sanitizer/70342 (g++ -fsanitize=undefined never finishes compiling (>24h) in qtxmlpatterns test suite)

PR sanitizer/70342
* fold-const.c (tree_single_nonzero_warnv_p): For TARGET_EXPR, use
TARGET_EXPR_SLOT as a base.

* g++.dg/ubsan/null-7.C: New test.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r235637

arc.md (*loadqi_update): Replace use of 'rI' constraint with 'rCm2' constraints to limit possible...

2016-04-29  Andrew Burgess  <andrew.burgess@embecosm.com>

        * config/arc/arc.md (*loadqi_update): Replace use of 'rI'
        constraint with 'rCm2' constraints to limit possible immediate
        size.
        (*load_zeroextendqisi_update): Likewise.
        (*load_signextendqisi_update): Likewise.
        (*loadhi_update): Likewise.
        (*load_zeroextendhisi_update): Likewise.
        (*load_signextendhisi_update): Likewise.
        (*loadsi_update): Likewise.
        (*loadsf_update): Likewise.

From-SVN: r235636

predicates.md (constm1_operand): Fix comparison.

* config/i386/predicates.md (constm1_operand): Fix comparison.

From-SVN: r235635

[ARC] Handle FPX NaN within optimized floating point library.

gcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

* testsuite/gcc.target/arc/ieee_eq.c: New test.

libgcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/ieee-754/eqdf2.S: Handle FPX NaN.

From-SVN: r235633

longlong.h (umul_ppmm): Remove SHMEDIA checks.

include/
* longlong.h (umul_ppmm): Remove SHMEDIA checks.
(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.

gcc/
* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
remaining SH5 related settings.
* config/sh/sh-protos.h (shmedia_cleanup_truncate,
shmedia_prepare_call_address): Delete.
* config/sh/sh.c (sh_print_operand, output_stack_adjust,
DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments.
* config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC,
UNSUPPORTED_SH2A): Remove m5 checks.
(sh_divide_strategy_e): Remove SH5 division strategies.
(TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default.
* config/sh/sh.md (divsf3): Reinstate define_expand pattern.

From-SVN: r235632

[ARC] Fix obsolete constraint.

include/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

* longlong.h (add_ssaaaa): Replace obsolete 'J' constraint with
'Cal' constraint.
(sub_ddmmss): Likewise.

From-SVN: r235631

S/390: Improve documentation of s390_reload_costs.

gcc/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

* config/s390/s390.c (s390_rtx_costs): Update documentation.

From-SVN: r235630

PR/69089: C++-11: Ingore "alignas(0)".

gcc/c-family/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

PR/69089
* c-common.c (handle_aligned_attribute): Allow 0 as an argument to the
"aligned" attribute.

gcc/testsuite/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

PR/69089
* g++.dg/cpp0x/alignas6.C: New test.

From-SVN: r235629

Clean up tests where a later dg-do completely overrides another.

The attached patch cleans up some (mostly unnecessary) dg-do
directives in the gcc.dg and gcc.target test cases.

gcc/testsuite/ChangeLog:

2016-04-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>

* gcc/testsuite/gcc.dg/cpp/mac-dir-2.c: Remove pointless duplicate
dg-do.
* gcc/testsuite/gcc.dg/pr27003.c: Likewise.
* gcc/testsuite/gcc.dg/tree-ssa/cswtch.c: Likewise.
* gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c: Likewise.
* gcc/testsuite/gcc.dg/tree-ssa/predcom-4.c: Likewise.
* gcc/testsuite/gcc.dg/tree-ssa/predcom-5.c: Likewise.
* gcc.target/arc/mxy.c: Likewise.
* gcc.target/arc/mswape.c: Likewise.
* gcc.target/arc/mrtsc.c: Likewise.
* gcc.target/arc/mcrc.c: Likewise.
* gcc.target/arc/mdsp-packa.c: Likewise.
* gcc.target/arc/mdvbf.c: Likewise.
* gcc.target/arc/mlock.c: Likewise.
* gcc.target/arc/mmac-24.c: Likewise.
* gcc.dg/spec-options.c: Switch order of the two "dg-do run".

From-SVN: r235628

S/390: Replace LDER with LDR.

For performance reasons it is important to write the full 64 bits of
an FPR target reg even when dealing with 32 bit values.  So we chose
lder over ler for 32 bit float register moves.  lder zero-extends the
32 bit value from the source reg to 64 bit in the target.  However,
since it actually doesn't matter whether we write the upper 32 bits
with zeros or with any other garbage we can also use ldr instead.  It
is bit shorter and therefore will do good for I-Cache usage.

gcc/ChangeLog:

2016-04-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

* config/s390/2964.md ("z13_unit_fxu", "z13_0"): Remove lder.
* config/s390/s390.md ("movsi_larl", "*movsi_esa", "mov<mode>"):
Change lder to ldr.
* config/s390/vector.md ("mov<mode>"): Likewise.

From-SVN: r235627

S/390: Memory constraint cleanup

This fixes an issue with the long displacement memory address
constraints S and T.  These were defined to only accept long
displacement addresses.  This is wrong since a memory constraint must
not reject an address with a 0 displacement.  Reload relies on being
able to turn an invalid memory address into a valid one by reloading
the address into a base register.  The S and T constraints would
reject such an address.

This isn't really a problem for the backend since we used the
constraints with that knowledge there but it is a problem for people
writing inline assemblies.

gcc/ChangeLog:

2016-04-29  Ulrich Weigand  <uweigand@de.ibm.com>

* config/s390/constraints.md ("U", "W"): Invoke
s390_mem_constraint with "ZR" and "ZT".
* config/s390/s390.c (s390_check_qrst_address): Reject invalid
addresses when using LRA.  Accept also short displacements for S
and T constraints.  Do not check for long displacement target for
S and T constraints.
(s390_mem_constraint): Remove handling of U and W constraints.
* config/s390/s390.md (various patterns): Remove the short
displacement constraints (Q and R) if a long displacement
constraint is present.  Add longdisp as required CPU capability.
* config/s390/vector.md: Likewise.
* config/s390/vx-builtins.md: Likewise.

From-SVN: r235626

avr-related reload fix from Senthil Kumar Selvaraj

PR target/60040
* reload1.c (reload): Call finish_spills before
restarting reload loop. Skip select_reload_regs
if update_eliminables_and_spill returns true.

testsuite/
PR target/60040
* gcc.target/avr/pr60040-1.c: New.
* gcc.target/avr/pr60040-2.c: New.

From-SVN: r235625

pr18589-10.c: Adjust.

2016-04-29  Richard Biener  <rguenther@suse.de>

* gcc.dg/tree-ssa/pr18589-10.c: Adjust.

From-SVN: r235624

[ARC] Fix unwanted match for sign extend 16-bit constant.

The combine pass may conclude umulhisi3_imm pattern can accept also sign
extended 16-bit constants. This patch prohibits the combine in considering
this pattern as suitable.

gcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
(umulhisi3_imm): Update predicates and constraint letters.
(umulhisi3_reg): Declare instruction as commutative.
* config/arc/constraints.md (J12, J16): New constraints.
* config/arc/predicates.md (short_unsigned_const_operand): New
predicate.
(arc_short_operand): Likewise.
* testsuite/gcc.target/arc/umulsihi3_z.c: New file.

From-SVN: r235623

re PR tree-optimization/13962 ([tree-ssa] make "fold" use alias information to optimize pointer comparisons)

2016-04-29  Richard Biener  <rguenther@suse.de>

PR tree-optimization/13962
PR tree-optimization/65686
* tree-ssa-alias.h (ptrs_compare_unequal): Declare.
* tree-ssa-alias.c (ptrs_compare_unequal): New function
using PTA to compare pointers.
* match.pd: Add pattern for pointer equality compare simplification
using ptrs_compare_unequal.

* gcc.dg/uninit-pr65686.c: New testcase.

From-SVN: r235622

stor-layout.c (layout_type): Do not build a pointer-to-element type for arrays.

2016-04-29  Richard Biener  <rguenther@suse.de>

* stor-layout.c (layout_type): Do not build a pointer-to-element
type for arrays.

From-SVN: r235621

i386.md (Load+RegOp to Mov+MemOp peephole2): Use SWI mode iterator.

* config/i386/i386.md (Load+RegOp to Mov+MemOp peephole2):
Use SWI mode iterator.  Use general_reg_operand predicate.
(Load+RegOp to Mov+MemOp peephole2 with vector regs): Split
peephole to MMX and SSE part.  Use mmx_reg_operand and sse_reg_operand
predicates.

From-SVN: r235620

Daily bump.

From-SVN: r235619

re PR middle-end/70843 (ICE in add_expr, at tree.c:7913)

PR middle-end/70843
* fold-const.c (operand_equal_p): Don't verify hash value equality
if arg0 == arg1.
* tree.c (inchash::add_expr): Handle STATEMENT_LIST.  Ignore BLOCK
and OMP_CLAUSE.

* gcc.dg/pr70843.c: New test.

From-SVN: r235615

c-array-notation.c (fix_builtin_array_notation_fn): Fix final argument to build_modify_expr in two cases.

2016-04-28  Andrew MacLeod  <amacleod@redhat.com>

* c-array-notation.c (fix_builtin_array_notation_fn): Fix final
argument to build_modify_expr in two cases.

From-SVN: r235614

compiler: Mark concurrent calls.

    If a call expression is executed in an independent goroutine via
    use of a Go statement, mark it as concurrent.

    Reviewed-on: https://go-review.googlesource.com/18700

From-SVN: r235608

re PR target/70858 (__builtin_ia32_bextr_u64 ICE with '-m32 -march=core-avx2')

PR target/70858
* config/i386/i386.c (bdesc_special_args): Add | OPTION_MASK_ISA_64BIT
to __builtin_ia32_lwpval64 and __builtin_ia32_lwpins64.
(bdesc_args): Add | OPTION_MASK_ISA_64BIT to __builtin_ia32_bextr_u64,
__builtin_ia32_bextri_u64, __builtin_ia32_bzhi_di,
__builtin_ia32_pdep_di and __builtin_ia32_pext_di.

* gcc.target/i386/pr70858.c: New test.

From-SVN: r235607

rs6000: Clean up rs6000_stack_info a bit

- Rename "info_ptr" to "info", as in all other routines;
- Don't set fields to 0, the whole struct already is set to 0;
- Fix formatting a bit.

* config/rs6000/rs6000.c (compute_save_world_info): Rename info_ptr
to info.  Don't initialize separate fields to 0.  Clean up
formatting a bit.

From-SVN: r235606

nps400-1.c: New file.

2016-04-28  Andrew Burgess  <andrew.burgess@embecosm.com>

        * gcc.target/arc/nps400-1.c: New file.

From-SVN: r235603

compiler: Export String_index_expression.

    Exports String_index_expression and adds the getter `string` that
    returns the underlying string.  This will be used to handle string
    indexing different from array indexing in escape analysis.

    Reviewed-on: https://go-review.googlesource.com/18545

From-SVN: r235602

i386.md (peephole2s for operations with memory inputs): Use SWI mode iterator.

* config/i386/i386.md (peephole2s for operations with memory inputs):
Use SWI mode iterator.
(peephole2s for operations with memory outputs): Ditto.
Do not check for stack checking probe.

(probe_stack): Remove expander.

From-SVN: r235601

arc.c (arc_print_operand): Print integer 'H' / 'L'

2016-04-28  Joern Rennecke  <joern.rennecke@embecosm.com>
            Andrew Burgess  <andrew.burgess@embecosm.com>
gcc:
        * config/arc/arc.c (arc_print_operand): Print integer 'H' / 'L'
gcc/testsuite:
        * gcc.target/arc/movh_cl-1.c: New file.

Co-Authored-By: Andrew Burgess <andrew.burgess@embecosm.com>
From-SVN: r235600

* gdbinit.in: Skip line-map.h.

From-SVN: r235598

Implement C++17 [[nodiscard]] attribute.

PR c++/38172
PR c++/54379
gcc/c-family/
* c-lex.c (c_common_has_attribute): Handle nodiscard.
gcc/cp/
* parser.c (cp_parser_std_attribute): Handle [[nodiscard]].
* tree.c (handle_nodiscard_attribute): New.
(cxx_attribute_table): Add [[nodiscard]].
* cvt.c (cp_get_fndecl_from_callee, cp_get_callee_fndecl): New.
(maybe_warn_nodiscard): New.
(convert_to_void): Call it.

From-SVN: r235597

cvt.c (cp_get_callee): New.

* cvt.c (cp_get_callee): New.

* constexpr.c (get_function_named_in_call): Use it.
* cxx-pretty-print.c (postfix_expression): Use it.
* except.c (check_noexcept_r): Use it.
* method.c (check_nontriv): Use it.
* tree.c (build_aggr_init_expr): Use it.
* cp-tree.h: Declare it.

From-SVN: r235596

arc.h (SYMBOL_FLAG_CMEM): Define.

2016-04-28  Joern Rennecke  <joern.rennecke@embecosm.com>
            Andrew Burgess  <andrew.burgess@embecosm.com>
gcc:
        * config/arc/arc.h (SYMBOL_FLAG_CMEM): Define.
        (TARGET_NPS_CMEM_DEFAULT): Provide default definition.
        * config/arc/arc.c (arc_address_cost): Return 0 for cmem_address.
        (arc_encode_section_info): Set SYMBOL_FLAG_CMEM where indicated.
        * config/arc/arc.opt (mcmem): New option.
        * config/arc/arc.md (*extendqihi2_i): Add r/Uex alternative,
        supply length for r/m alternative.
        (*extendqisi2_ac): Likewise.
        (*extendhisi2_i): Add r/Uex alternative, supply length for r/m and
        r/Uex alternative.
        (movqi_insn): Add r/Ucm and Ucm/?Rac alternatives.
        (movhi_insn): Likewise.
        (movsi_insn): Add r/Ucm,Ucm/w alternatives.
        (*zero_extendqihi2_i): Add r/Ucm alternative.
        (*zero_extendqisi2_ac): Likewise.
        (*zero_extendhisi2_i): Likewise.
        * config/arc/constraints.md (Uex): New memory constraint.
        (Ucm): New define_constraint.
        * config/arc/predicates.md (long_immediate_loadstore_operand):
        Return 0 for MEM with cmem_address address.
        (cmem_address_0): New predicates.
        (cmem_address_1): Likewise.
        (cmem_address_2): Likewise.
        (cmem_address): Likewise.
gcc/testsuite:
        * gcc.target/arc/cmem-1.c: New file.
        * gcc.target/arc/cmem-2.c: New file.
        * gcc.target/arc/cmem-3.c: New file.
        * gcc.target/arc/cmem-4.c: New file.
        * gcc.target/arc/cmem-5.c: New file.
        * gcc.target/arc/cmem-6.c: New file.
        * gcc.target/arc/cmem-7.c: New file.
        * gcc.target/arc/cmem-ld.inc: New file.
        * gcc.target/arc/cmem-st.inc: New file.

Co-Authored-By: Andrew Burgess <andrew.burgess@embecosm.com>
From-SVN: r235595

sbitmap: Remove popcount

In r193072 sbitmap_popcount was removed, so we cannot ask for the popcount
of an sbitmap anymore.  Nothing calls sbitmap_alloc_with_popcount either.
This patch removes everything else popcount-related from sbitmap.

* cfganal.c (bitmap_intersection_of_succs): Delete assert checking
dst->popcount.
(bitmap_intersection_of_preds): Ditto.
(bitmap_union_of_succs): Ditto.
(bitmap_union_of_preds): Ditto.
* sbitmap.c (do_popcount): Delete.
(BITMAP_DEBUGGING): Delete.
(sbitmap_verify_popcount): Delete.
(sbitmap_alloc): Don't initialize the popcount field.
(sbitmap_alloc_with_popcount): Delete.
(sbitmap_resize): Don't resize the popcount array.
(sbitmap_vector_alloc): Don't initialize the popcount field.
(bitmap_copy): Don't copy the popcount array.
(bitmap_clear): Don't clear the popcount array.
(bitmap_clear): Delete the popcount array handling.
(bitmap_ior_and_compl): Delete the popcount assert.
(bitmap_not): Ditto.
(bitmap_and_compl): Ditto.
(bitmap_and): Delete the popcount array handling.
(bitmap_xor): Ditto.
(bitmap_ior): Ditto.
(bitmap_or_and): Delete the popcount assert.
(bitmap_and_or): Ditto.
(popcount_table): Delete.
(sbitmap_elt_popcount): Delete.
* sbitmap.h (simple_bitmap_def): Delete the popcount field.
(bitmap_set_bit): Delete the popcount assert.
(bitmap_clear_bit): Ditto.
(sbitmap_free): Don't free the popcount array.
(sbitmap_alloc_with_popcount): Delete declaration.
(sbitmap_popcount): Ditto.

From-SVN: r235592

* ChangeLog: Remove duplicate entry.

From-SVN: r235591

arc.h (SYMBOL_FLAG_CMEM): Define.

2016-04-28  Joern Rennecke  <joern.rennecke@embecosm.com>
            Andrew Burgess  <andrew.burgess@embecosm.com>
gcc:
        * config/arc/arc.h (SYMBOL_FLAG_CMEM): Define.
        (TARGET_NPS_CMEM_DEFAULT): Provide default definition.
        * config/arc/arc.c (arc_address_cost): Return 0 for cmem_address.
        (arc_encode_section_info): Set SYMBOL_FLAG_CMEM where indicated.
        * config/arc/arc.opt (mcmem): New option.
        * config/arc/arc.md (*extendqihi2_i): Add r/Uex alternative,
        supply length for r/m alternative.
        (*extendqisi2_ac): Likewise.
        (*extendhisi2_i): Add r/Uex alternative, supply length for r/m and
        r/Uex alternative.
        (movqi_insn): Add r/Ucm and Ucm/?Rac alternatives.
        (movhi_insn): Likewise.
        (movsi_insn): Add r/Ucm,Ucm/w alternatives.
        (*zero_extendqihi2_i): Add r/Ucm alternative.
        (*zero_extendqisi2_ac): Likewise.
        (*zero_extendhisi2_i): Likewise.
        * config/arc/constraints.md (Uex): New memory constraint.
        (Ucm): New define_constraint.
        * config/arc/predicates.md (long_immediate_loadstore_operand):
        Return 0 for MEM with cmem_address address.
        (cmem_address_0): New predicates.
        (cmem_address_1): Likewise.
        (cmem_address_2): Likewise.
        (cmem_address): Likewise.
gcc/testsuite:
        * gcc.target/arc/cmem-1.c: New file.
        * gcc.target/arc/cmem-2.c: New file.
        * gcc.target/arc/cmem-3.c: New file.
        * gcc.target/arc/cmem-4.c: New file.
        * gcc.target/arc/cmem-5.c: New file.
        * gcc.target/arc/cmem-6.c: New file.
        * gcc.target/arc/cmem-7.c: New file.
        * gcc.target/arc/cmem-ld.inc: New file.
        * gcc.target/arc/cmem-st.inc: New file.

Co-Authored-By: Andrew Burgess <andrew.burgess@embecosm.com>
From-SVN: r235590

rs6000: Rename insn_chain_scanned_p to spe_insn_chain_scanned_p

This makes it clearer this field is only for SPE.

* config/rs6000/rs6000.c (machine_function): Rename
insn_chain_scanned_p to spe_insn_chain_scanned_p.
(rs6000_stack_info): Adjust.

From-SVN: r235588

constraints.md (Usd): Convert to define_constraint.

2016-04-28  Andrew Burgess  <andrew.burgess@embecosm.com>

        * config/arc/constraints.md (Usd): Convert to define_constraint.
        (Us<): Likewise.
        (Us>): Likewise.

From-SVN: r235587

re PR target/70821 (x86_64: __atomic_fetch_add/sub() uses XADD rather than DECL in some cases)

PR target/70821
* config/i386/sync.md (define_peephole2 *atomic_fetch_add_cmp<mode>):
Add new peephole2 where the first insn is *mov<mode>_or instead of
*mov<mode>_internal.

* gcc.target/i386/pr70821.c: New test.

From-SVN: r235586

tracer: Make bb_seen static

bb_seen is not used outside of tracer.c.

* tracer.c (bb_seen): Make static.

From-SVN: r235585

arc-common.c (arc_handle_option): Add NPS400 support, setup defaults.

2016-04-28  Andrew Burgess  <andrew.burgess@embecosm.com>

        * common/config/arc/arc-common.c (arc_handle_option): Add NPS400
        support, setup defaults.
        * config/arc/arc-opts.h (enum processor_type): Add NPS400.
        * config/arc/arc.c (arc_init): Add NPS400 support.
        * config/arc/arc.h (CPP_SPEC): Add NPS400 defines.
        (TARGET_ARC700): NPS400 is also an ARC700.
        * config/arc/arc.opt: Add NPS400 options to -mcpu=.

From-SVN: r235584

nds32: Fix casesi (PR70668)

Expanders do not have more elements in the operands array than declared
in the pattern.  So, we cannot use operands[5] here.  Instead just
declare and use another rtx.

PR target/70668
* config/nds32/nds32.md (casesi): Don't access the operands array
out of bounds.

From-SVN: r235583

i386.md (zeroing peephole2): Use general_reg_operand.

* config/i386/i386.md (zeroing peephole2): Use general_reg_operand.
(or $-1,reg peephole2): Ditto.
(strict_low_part zeroing peephole2): Use SWI12 mode iterator.

From-SVN: r235581

doc/extend.texi: Discourage use of the optimize attribute

* doc/extend.texi (Common Function Attributes) [optimize]:
Discourage use of the optimize attribute.

From-SVN: r235580

Forgotten gcc/java/ChangeLog entry.

From-SVN: r235579

This patch adds support for the signed and unsigned int versions of the...

This patch adds support for the signed and unsigned int versions of the
vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There are
many of the builtins that are missing and this is the first of a series
of patches to add them.

There aren't instructions for the int versions of vec_adde so the
output code is built from other built-ins that do have instructions
which in this case is just two vec_adds with a vec_and to ensure the
carry vector is comprised of only the values 0 or 1.

The new test cases are executable tests which verify that the generated
code produces expected values. C macros were used so that the same
test case could be used for both the signed and unsigned versions. An
extra executable test case is also included to ensure that the modified
support for the __int128 versions of vec_adde is not broken. The same
test case could not be used for both int and __int128 because of some
differences in loading and storing the vectors.

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this ok for trunk?

[gcc]

2016-04-28  Bill Seurer  <seurer@linux.vnet.ibm.com>

* config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
special case builtin.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
support for ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000.c (altivec_init_builtins): Add definition
for __builtin_vec_adde.

[gcc/testsuite]

2016-04-28  Bill Seurer  <seurer@linux.vnet.ibm.com>

* gcc.target/powerpc/vec-adde.c: New test.
* gcc.target/powerpc/vec-adde-int128.c: New test.

From-SVN: r235577

i386.md (sse4_1_round<mode>2): Add avx512f alternative.

* config/i386/i386.md (sse4_1_round<mode>2): Add avx512f alternative.
* config/i386/sse.md (sse4_1_round<ssescalarmodesuffix>): Likewise.

* gcc.target/i386/avx-vround-1.c: New test.
* gcc.target/i386/avx-vround-2.c: New test.
* gcc.target/i386/avx512vl-vround-1.c: New test.
* gcc.target/i386/avx512vl-vround-2.c: New test.

From-SVN: r235576

Don't include minor version in GCJ ABI version (PR java/70839)

PR java/70839
* decl.c (parse_version): Remove minor handling.

From-SVN: r235575

Cilk Plus testsuite needs massive cleanup (PR testsuite/70595)

gcc:
PR testsuite/70595
* doc/sourcebuild.texi (Effective-Target Keywords, Other
attributes): Document cilkplus_runtime.

gcc/testsuite:
PR testsuite/70595
* lib/target-supports.exp (check_libcilkrts_available): Rename to ...
(check_effective_target_cilkplus_runtime): ... this.
* g++.dg/cilk-plus/cilk-plus.exp: Adapt to it.
* gcc.dg/cilk-plus/cilk-plus.exp: Likewise.

* c-c++-common/cilk-plus/CK/cilk-for-2.c: Remove dg-do target selector.
Require cilkplus_runtime.
Don't add -lcilkrts.
* c-c++-common/cilk-plus/CK/cilk-fors.c: Likewise.
* c-c++-common/cilk-plus/CK/cilk_for_grain.c: Likewise.
* c-c++-common/cilk-plus/CK/cilk_for_ptr_iter.c: Likewise.
* c-c++-common/cilk-plus/CK/fib.c: Likewise.
* c-c++-common/cilk-plus/CK/fib_init_expr_xy.c: Likewise.
* c-c++-common/cilk-plus/CK/fib_no_return.c: Likewise.
* c-c++-common/cilk-plus/CK/fib_no_sync.c: Likewise.
* c-c++-common/cilk-plus/CK/nested_cilk_for.c: Likewise.
* c-c++-common/cilk-plus/CK/pr60586.c: Likewise.
* c-c++-common/cilk-plus/CK/pr69826-1.c: Likewise.
* c-c++-common/cilk-plus/CK/pr69826-2.c: Likewise.
* c-c++-common/cilk-plus/CK/spawnee_inline.c: Likewise.
* c-c++-common/cilk-plus/CK/spawner_inline.c: Likewise.
* c-c++-common/cilk-plus/CK/spawning_arg.c: Likewise.
* c-c++-common/cilk-plus/CK/steal_check.c: Likewise.
* c-c++-common/cilk-plus/CK/varargs_test.c: Likewise.
* g++.dg/cilk-plus/CK/catch_exc.cc: Likewise.
* g++.dg/cilk-plus/CK/cilk-for-tplt.cc: Likewise.
* g++.dg/cilk-plus/CK/const_spawn.cc: Likewise.
* g++.dg/cilk-plus/CK/fib-opr-overload.cc: Likewise.
* g++.dg/cilk-plus/CK/fib-tplt.cc: Likewise.
* g++.dg/cilk-plus/CK/for1.cc: Likewise.
* g++.dg/cilk-plus/CK/lambda_spawns.cc: Likewise.
* g++.dg/cilk-plus/CK/lambda_spawns_tplt.cc: Likewise.
* g++.dg/cilk-plus/CK/pr60586.cc: Likewise.
* g++.dg/cilk-plus/CK/pr66326.cc: Likewise.
* g++.dg/cilk-plus/CK/stl_iter.cc: Likewise.
* g++.dg/cilk-plus/CK/stl_rev_iter.cc: Likewise.
* g++.dg/cilk-plus/CK/stl_test.cc: Likewise.

* c-c++-common/cilk-plus/CK/pr63307.c: Remove dg-do target selector.
* c-c++-common/cilk-plus/SE/ef_error3.c: Likewise.

* c-c++-common/cilk-plus/SE/ef_error2.c: Explain target selector.

* c-c++-common/cilk-plus/CK/test__cilk.c: Run if
cilkplus_runtime.

From-SVN: r235574

Update .po files.

gcc/po:
* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
zh_TW.po: Update.

libcpp/po:
* be.po, ca.po, da.po, de.po, el.po, eo.po, es.po, fi.po, fr.po,
id.po, ja.po, nl.po, pr_BR.po, ru.po, sr.po, sv.po, tr.po, uk.po,
vi.po, zh_CN.po, zh_TW.po: Update.

From-SVN: r235571

Verify that context of local DECLs is the current function

2016-04-28  Martin Jambor  <mjambor@suse.cz>

* tree-cfg.c (verify_expr): Verify that local declarations belong to
this function.  Call verify_expr on MEM_REFs and bases of other
handled_components.

From-SVN: r235570

[internal-fn.c][committed] Convert conditional compilation on WORD_REGISTER_OPERATIONS

* internal-fn.c (expand_arith_overflow): Convert preprocessor check
for WORD_REGISTER_OPERATIONS to runtime check.

From-SVN: r235569

[ARC] Pass mfpuda to assembler.

gcc/
2016-04-28  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.h (ASM_SPEC): Pass mfpuda to assembler.

From-SVN: r235568

[ARC] Fix FPX/FPUDA code gen when compiling for big-endian.

gcc/
2016-04-28  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.c (arc_process_double_reg_moves): Fix for
big-endian compilation.
(arc_rtx_costs): Fix high/low naming.
* config/arc/arc.md (addf3): Likewise.
(subdf3): Likewise.
(muldf3): Likewise.

From-SVN: r235567

re PR tree-optimization/70840 (revisit reassoc handling of pow / powi, amend match.pd for powi)

2016-04-28  Richard Biener  <rguenther@suse.de>

PR tree-optimization/70840
* match.pd: powi(-x, y) and powi(|x|,y) -> powi(x,y) if y is even;
Fix pow(copysign(x, y), z) -> pow(x, z) and add powi variant;
Mark x * pow(x,c) -> pow(x,c+1) commutative.
Add powi(x,y) * powi(z,y) -> powi(x*z,y).

From-SVN: r235566

libstdc++/70766 use std::addressof instead of operator&

PR libstdc++/70766
* include/bits/basic_ios.tcc (basic_ios::_M_cache_locale): Use
__addressof.
* include/bits/stream_iterator.h (istream_iterator, ostream_iterator):
Likewise.
* include/std/atomic (atomic<_Tp>): Likewise.
* include/std/shared_mutex (shared_lock): Likewise.
* testsuite/24_iterators/istream_iterator/70766.cc: New test.
* testsuite/24_iterators/ostream_iterator/70766.cc : New test.
* testsuite/29_atomics/atomic/60695.cc: Adjust dg-error line number.
* testsuite/29_atomics/atomic/70766.cc: New test.
* testsuite/30_threads/shared_lock/70766.cc: New test.

From-SVN: r235565

hashtable_policy.h (__detail::_Insert_base, [...]): Improve comments.

* include/bits/hashtable_policy.h (__detail::_Insert_base,
__detail::_Insert): Improve comments.

From-SVN: r235564

[AArch64] Define WORD_REGISTER_OPERATIONS to zero and comment why

* config/aarch64/aarch64.h (WORD_REGISTER_OPERATIONS): Define to 0
and explain why in a comment.

From-SVN: r235563