Clifford Wolf [Sat, 8 Feb 2014 13:21:04 +0000 (14:21 +0100)]
Only count non-trivial attributes when findinf master signal in opt_clean
Clifford Wolf [Sat, 8 Feb 2014 11:27:38 +0000 (12:27 +0100)]
Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output
Clifford Wolf [Fri, 7 Feb 2014 23:06:00 +0000 (00:06 +0100)]
Now also move net labes to the right position in splice cmd
Clifford Wolf [Fri, 7 Feb 2014 22:50:17 +0000 (23:50 +0100)]
Improved detection of primary wire for a signal in opt_clean
Clifford Wolf [Fri, 7 Feb 2014 19:26:40 +0000 (20:26 +0100)]
Added splice command
Clifford Wolf [Fri, 7 Feb 2014 18:51:15 +0000 (19:51 +0100)]
Added log_header() to splitnets
Clifford Wolf [Fri, 7 Feb 2014 18:50:44 +0000 (19:50 +0100)]
Added $slice and $concat to CellTypes list
Clifford Wolf [Fri, 7 Feb 2014 16:44:57 +0000 (17:44 +0100)]
Added $slice and $concat cell types
Clifford Wolf [Fri, 7 Feb 2014 16:39:35 +0000 (17:39 +0100)]
Stronger checking of internal cells
Clifford Wolf [Fri, 7 Feb 2014 15:36:37 +0000 (16:36 +0100)]
Re-enabled abc "retime" after sorting yout the yosys-bigsim problem
Clifford Wolf [Fri, 7 Feb 2014 13:17:00 +0000 (14:17 +0100)]
Added echo command
Clifford Wolf [Fri, 7 Feb 2014 13:16:42 +0000 (14:16 +0100)]
Fixed use of "cmd_error" in passes/cmds/design.cc
Clifford Wolf [Thu, 6 Feb 2014 21:49:14 +0000 (22:49 +0100)]
Fixed gcc compiler warnings with release build
Clifford Wolf [Thu, 6 Feb 2014 21:31:58 +0000 (22:31 +0100)]
Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed)
Clifford Wolf [Thu, 6 Feb 2014 21:18:17 +0000 (22:18 +0100)]
Updated ABC to rev
10cc13a2a0f1
Clifford Wolf [Thu, 6 Feb 2014 21:16:20 +0000 (22:16 +0100)]
Added "retime" to standard ABC recipes
Clifford Wolf [Thu, 6 Feb 2014 21:09:21 +0000 (22:09 +0100)]
Added copy command
Clifford Wolf [Thu, 6 Feb 2014 20:52:07 +0000 (21:52 +0100)]
Added design -stash/-copy-from/-copy-to
Clifford Wolf [Thu, 6 Feb 2014 18:45:03 +0000 (19:45 +0100)]
Added support for s: select expressions (wire width)
Clifford Wolf [Thu, 6 Feb 2014 18:35:33 +0000 (19:35 +0100)]
Added i:, o:, and x: selection pattern
Clifford Wolf [Thu, 6 Feb 2014 18:30:08 +0000 (19:30 +0100)]
Added support for %m selection op
Clifford Wolf [Thu, 6 Feb 2014 18:22:50 +0000 (19:22 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Thu, 6 Feb 2014 18:22:46 +0000 (19:22 +0100)]
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf [Thu, 6 Feb 2014 17:08:02 +0000 (18:08 +0100)]
Merge pull request #23 from hansiglaser/master
new %s: add sub-modules to selection
Johann Glaser [Thu, 6 Feb 2014 16:36:39 +0000 (17:36 +0100)]
new %s: add sub-modules to selection
Clifford Wolf [Thu, 6 Feb 2014 16:32:51 +0000 (17:32 +0100)]
Added support for sat -show @<sel_name>
Clifford Wolf [Thu, 6 Feb 2014 15:15:23 +0000 (16:15 +0100)]
Added sat -set-init-def and sat -tempinduct-def
Clifford Wolf [Thu, 6 Feb 2014 14:49:03 +0000 (15:49 +0100)]
Added opt_const -undriven
Clifford Wolf [Thu, 6 Feb 2014 14:48:42 +0000 (15:48 +0100)]
Added expose -dff
Clifford Wolf [Thu, 6 Feb 2014 13:26:39 +0000 (14:26 +0100)]
Added support for #-comments in same line as command
Clifford Wolf [Thu, 6 Feb 2014 13:01:43 +0000 (14:01 +0100)]
presentation progress
Clifford Wolf [Thu, 6 Feb 2014 12:10:06 +0000 (13:10 +0100)]
Changed techmap description from "simple" to "generic"
Clifford Wolf [Thu, 6 Feb 2014 01:20:55 +0000 (02:20 +0100)]
Added miter -make_outcmp
Clifford Wolf [Thu, 6 Feb 2014 00:40:01 +0000 (01:40 +0100)]
Added sat -set-init-zero support
Clifford Wolf [Thu, 6 Feb 2014 00:28:33 +0000 (01:28 +0100)]
Added support for backslash continuation in script files
Clifford Wolf [Thu, 6 Feb 2014 00:00:11 +0000 (01:00 +0100)]
Added counters sat test case
Clifford Wolf [Wed, 5 Feb 2014 23:59:41 +0000 (00:59 +0100)]
Added sat -verify and -falsify support for non-prove cases
Clifford Wolf [Wed, 5 Feb 2014 22:59:55 +0000 (23:59 +0100)]
Added expose command
Clifford Wolf [Wed, 5 Feb 2014 19:06:34 +0000 (20:06 +0100)]
presentation progress
Clifford Wolf [Wed, 5 Feb 2014 17:52:55 +0000 (18:52 +0100)]
Simplified select "Assertation failed" message generation
Clifford Wolf [Wed, 5 Feb 2014 17:46:47 +0000 (18:46 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 5 Feb 2014 17:46:36 +0000 (18:46 +0100)]
Merge pull request #22 from hansiglaser/master
Little improvements for "select"
Clifford Wolf [Wed, 5 Feb 2014 17:31:10 +0000 (18:31 +0100)]
Added BTOR backend README file
Clifford Wolf [Wed, 5 Feb 2014 17:24:45 +0000 (18:24 +0100)]
Added selection support for r: and selection with relational operators
Johann Glaser [Wed, 5 Feb 2014 15:03:02 +0000 (16:03 +0100)]
be more verbose for select -assert-any and -assert-none
Johann Glaser [Wed, 5 Feb 2014 14:53:02 +0000 (15:53 +0100)]
improved help for "select"
Clifford Wolf [Wed, 5 Feb 2014 14:06:13 +0000 (15:06 +0100)]
presentation progress
Clifford Wolf [Wed, 5 Feb 2014 12:12:50 +0000 (13:12 +0100)]
presentation progress
Clifford Wolf [Wed, 5 Feb 2014 10:22:10 +0000 (11:22 +0100)]
Added read_verilog -setattr
Clifford Wolf [Wed, 5 Feb 2014 10:11:55 +0000 (11:11 +0100)]
Added setattr and setparam commands
Clifford Wolf [Wed, 5 Feb 2014 00:59:30 +0000 (01:59 +0100)]
Updated todo items in README file
Clifford Wolf [Wed, 5 Feb 2014 00:55:39 +0000 (01:55 +0100)]
Removed old unused files from tests/
Clifford Wolf [Tue, 4 Feb 2014 22:45:30 +0000 (23:45 +0100)]
Added support for dump -append
Clifford Wolf [Tue, 4 Feb 2014 22:31:06 +0000 (23:31 +0100)]
Throw errors if non-existing selection variables are used
Clifford Wolf [Tue, 4 Feb 2014 22:23:44 +0000 (23:23 +0100)]
Added select -none
Clifford Wolf [Tue, 4 Feb 2014 22:00:48 +0000 (23:00 +0100)]
presentation progress
Clifford Wolf [Tue, 4 Feb 2014 22:00:32 +0000 (23:00 +0100)]
Fixed detection of init attribute in opt_rmdff
Clifford Wolf [Tue, 4 Feb 2014 21:01:53 +0000 (22:01 +0100)]
Added support for inline commands to abc -script
Clifford Wolf [Tue, 4 Feb 2014 15:51:12 +0000 (16:51 +0100)]
presentation progress
Clifford Wolf [Tue, 4 Feb 2014 15:50:13 +0000 (16:50 +0100)]
Added hierarchy -purge_lib option
Clifford Wolf [Tue, 4 Feb 2014 12:43:34 +0000 (13:43 +0100)]
Added test cases for sat command
Clifford Wolf [Tue, 4 Feb 2014 12:34:37 +0000 (13:34 +0100)]
added sat -falsify
Clifford Wolf [Tue, 4 Feb 2014 11:46:16 +0000 (12:46 +0100)]
Fixed bug in sequential sat proofs and improved handling of asserts
Clifford Wolf [Tue, 4 Feb 2014 11:02:47 +0000 (12:02 +0100)]
Improved handling of reg init in opt_share and opt_rmdff
Clifford Wolf [Mon, 3 Feb 2014 23:57:11 +0000 (00:57 +0100)]
presentation progress
Clifford Wolf [Mon, 3 Feb 2014 15:26:27 +0000 (16:26 +0100)]
presentation progress
Clifford Wolf [Mon, 3 Feb 2014 15:26:10 +0000 (16:26 +0100)]
Addred sat option -ignore_unknown_cells
Clifford Wolf [Mon, 3 Feb 2014 12:01:45 +0000 (13:01 +0100)]
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf [Mon, 3 Feb 2014 12:00:55 +0000 (13:00 +0100)]
Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
Clifford Wolf [Sun, 2 Feb 2014 21:41:24 +0000 (22:41 +0100)]
More opt_const -mux_bool features
Clifford Wolf [Sun, 2 Feb 2014 21:26:26 +0000 (22:26 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 21:11:08 +0000 (22:11 +0100)]
Added opt_const -mux_bool
Clifford Wolf [Sun, 2 Feb 2014 20:46:42 +0000 (21:46 +0100)]
Added support for inverter chains to opt_const
Clifford Wolf [Sun, 2 Feb 2014 20:35:26 +0000 (21:35 +0100)]
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf [Sun, 2 Feb 2014 20:27:26 +0000 (21:27 +0100)]
Only generate write-enable $and if WE is not constant 1 in memory_map
Clifford Wolf [Sun, 2 Feb 2014 20:09:08 +0000 (21:09 +0100)]
Added constant-clock case to opt_rmdff
Clifford Wolf [Sun, 2 Feb 2014 16:57:14 +0000 (17:57 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 16:55:32 +0000 (17:55 +0100)]
Added show -notitle option
Clifford Wolf [Sun, 2 Feb 2014 16:11:19 +0000 (17:11 +0100)]
Added delete command
Clifford Wolf [Sun, 2 Feb 2014 15:47:17 +0000 (16:47 +0100)]
Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax
Clifford Wolf [Sun, 2 Feb 2014 12:30:49 +0000 (13:30 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 12:06:28 +0000 (13:06 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 12:06:21 +0000 (13:06 +0100)]
Added support for blanks after -I and -D in read_verilog
Clifford Wolf [Sat, 1 Feb 2014 21:53:27 +0000 (22:53 +0100)]
Fixed a bug in miter command
Clifford Wolf [Sat, 1 Feb 2014 21:52:44 +0000 (22:52 +0100)]
Added sat -show-inputs and -show-outputs
Clifford Wolf [Sat, 1 Feb 2014 17:23:32 +0000 (18:23 +0100)]
Added show -color support for cells and finished show -label implementation
Clifford Wolf [Sat, 1 Feb 2014 16:28:02 +0000 (17:28 +0100)]
Fixed comment/eol parsing in ilang frontend
Clifford Wolf [Sat, 1 Feb 2014 12:50:23 +0000 (13:50 +0100)]
Added constant size expression support of sized constants
Clifford Wolf [Sat, 1 Feb 2014 12:04:49 +0000 (13:04 +0100)]
Added note about SystemVerilog assert statement to README
Clifford Wolf [Sat, 1 Feb 2014 09:35:56 +0000 (10:35 +0100)]
Added miter command
Clifford Wolf [Fri, 31 Jan 2014 11:48:31 +0000 (12:48 +0100)]
Progress on presentation
Clifford Wolf [Fri, 31 Jan 2014 10:21:29 +0000 (11:21 +0100)]
More changes to techlibs/common/simlib.v for LEC
Clifford Wolf [Thu, 30 Jan 2014 14:25:09 +0000 (15:25 +0100)]
presentation progress
Clifford Wolf [Thu, 30 Jan 2014 13:52:46 +0000 (14:52 +0100)]
Bugfix in name resolution with generate blocks
Clifford Wolf [Thu, 30 Jan 2014 11:32:59 +0000 (12:32 +0100)]
Added yosys -H for command list
Clifford Wolf [Wed, 29 Jan 2014 14:56:58 +0000 (15:56 +0100)]
presentation progress
Clifford Wolf [Wed, 29 Jan 2014 11:15:38 +0000 (12:15 +0100)]
presentation progress
Clifford Wolf [Wed, 29 Jan 2014 10:11:10 +0000 (11:11 +0100)]
Tiny change in example script in README
Clifford Wolf [Wed, 29 Jan 2014 10:10:39 +0000 (11:10 +0100)]
Added -h command line option
Clifford Wolf [Wed, 29 Jan 2014 09:51:02 +0000 (10:51 +0100)]
Added test comments to techlibs/cmos/cmos_cells.lib
projects / yosys.git / log