nmigen.git
5 years agovendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
whitequark [Sat, 15 Jun 2019 15:55:10 +0000 (15:55 +0000)]
vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.

Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.

5 years agobuild.plat: dedent overrides.
Alain Péteut [Sun, 16 Jun 2019 12:06:39 +0000 (14:06 +0200)]
build.plat: dedent overrides.

5 years agovendor.lattice_ice40: never place an inverter on global buffer output.
whitequark [Fri, 14 Jun 2019 20:44:02 +0000 (20:44 +0000)]
vendor.lattice_ice40: never place an inverter on global buffer output.

This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.

5 years agovendor.xilinx_7series: implement inverters.
Jean-François Nguyen [Thu, 13 Jun 2019 12:33:24 +0000 (14:33 +0200)]
vendor.xilinx_7series: implement inverters.

5 years agovendor.xilinx_spartan6: implement DDR I/O buffers and inverters.
Jean-François Nguyen [Wed, 12 Jun 2019 14:56:05 +0000 (16:56 +0200)]
vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.

5 years agocompat.fhdl.structure: fix Case().makedefault().
whitequark [Thu, 13 Jun 2019 03:54:46 +0000 (03:54 +0000)]
compat.fhdl.structure: fix Case().makedefault().

Fixes #100.

5 years agocompat.fhdl.structure: always order default case as the very last.
whitequark [Thu, 13 Jun 2019 03:52:04 +0000 (03:52 +0000)]
compat.fhdl.structure: always order default case as the very last.

5 years agohdl.ast: tighten assertion in Switch().
whitequark [Thu, 13 Jun 2019 03:56:49 +0000 (03:56 +0000)]
hdl.ast: tighten assertion in Switch().

5 years agoSimplify code by using Signal.like(name_suffix="..") appropriately.
whitequark [Wed, 12 Jun 2019 22:28:45 +0000 (22:28 +0000)]
Simplify code by using Signal.like(name_suffix="..") appropriately.

5 years agohdl.ast: add name_suffix=".." option to Signal.like().
whitequark [Wed, 12 Jun 2019 22:21:23 +0000 (22:21 +0000)]
hdl.ast: add name_suffix=".." option to Signal.like().

This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff

5 years agovendor.xilinx_7series: implement DDR I/O buffers.
Jean-François Nguyen [Tue, 11 Jun 2019 17:57:55 +0000 (19:57 +0200)]
vendor.xilinx_7series: implement DDR I/O buffers.

5 years agovendor.lattice_ice40: fix typo.
whitequark [Wed, 12 Jun 2019 17:38:14 +0000 (17:38 +0000)]
vendor.lattice_ice40: fix typo.

5 years agobuild.{dsl,res,plat}: add PinsN and DiffPairsN.
whitequark [Wed, 12 Jun 2019 14:42:39 +0000 (14:42 +0000)]
build.{dsl,res,plat}: add PinsN and DiffPairsN.

5 years agohdl.ast: implement values with custom lowering.
whitequark [Tue, 11 Jun 2019 07:01:44 +0000 (07:01 +0000)]
hdl.ast: implement values with custom lowering.

5 years agoback.pysim: check for a clock being added twice.
whitequark [Tue, 11 Jun 2019 03:54:22 +0000 (03:54 +0000)]
back.pysim: check for a clock being added twice.

This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.

5 years agoback.rtlil: mask memory init values.
whitequark [Tue, 11 Jun 2019 03:43:09 +0000 (03:43 +0000)]
back.rtlil: mask memory init values.

This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.

Fixes #96.

5 years agohdl.mem: coerce memory init values to integers.
whitequark [Tue, 11 Jun 2019 03:38:44 +0000 (03:38 +0000)]
hdl.mem: coerce memory init values to integers.

The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.

5 years agolib.cdc: fix typo.
Simon Kirkby [Sun, 9 Jun 2019 10:24:01 +0000 (18:24 +0800)]
lib.cdc: fix typo.

5 years agovendor.xilinx_spartan6: implement.
Jean-François Nguyen [Thu, 6 Jun 2019 22:48:51 +0000 (00:48 +0200)]
vendor.xilinx_spartan6: implement.

5 years agovendor.xilinx_7series: fix typos.
Jean-François Nguyen [Thu, 6 Jun 2019 22:54:52 +0000 (00:54 +0200)]
vendor.xilinx_7series: fix typos.

5 years agobuild.dsl: fix precondition check in Pins.
whitequark [Thu, 6 Jun 2019 20:40:49 +0000 (20:40 +0000)]
build.dsl: fix precondition check in Pins.

5 years agovendor.xilinx_7series: implement.
Jean-François Nguyen [Thu, 6 Jun 2019 11:53:17 +0000 (13:53 +0200)]
vendor.xilinx_7series: implement.

5 years agobuild.res: allow querying frequency of a previously constrained clock.
whitequark [Wed, 5 Jun 2019 12:51:53 +0000 (12:51 +0000)]
build.res: allow querying frequency of a previously constrained clock.

5 years agobuild.{dsl,res,plat}: apply clock constraints to signals, not resources.
whitequark [Wed, 5 Jun 2019 08:48:36 +0000 (08:48 +0000)]
build.{dsl,res,plat}: apply clock constraints to signals, not resources.

This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.

5 years agobuild.dsl: replace extras= with Attrs().
whitequark [Wed, 5 Jun 2019 07:02:08 +0000 (07:02 +0000)]
build.dsl: replace extras= with Attrs().

This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.

5 years agoTypos and style fixes. NFC.
whitequark [Wed, 5 Jun 2019 02:48:41 +0000 (02:48 +0000)]
Typos and style fixes. NFC.

5 years agovendor.lattice_ice40: normalize device names.
whitequark [Tue, 4 Jun 2019 16:09:08 +0000 (16:09 +0000)]
vendor.lattice_ice40: normalize device names.

Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.

5 years agohdl.ir: rephrase elaboratable warning to not look like an error.
whitequark [Tue, 4 Jun 2019 13:11:15 +0000 (13:11 +0000)]
hdl.ir: rephrase elaboratable warning to not look like an error.

5 years agocompat.fhdl.module: silence "unused elaboratable" warnings.
whitequark [Tue, 4 Jun 2019 13:09:36 +0000 (13:09 +0000)]
compat.fhdl.module: silence "unused elaboratable" warnings.

5 years agocompat.fhdl.specials: fix platform lowering for TSTriple again.
whitequark [Tue, 4 Jun 2019 13:03:56 +0000 (13:03 +0000)]
compat.fhdl.specials: fix platform lowering for TSTriple again.

5 years agocompat.fhdl.specials: fix platform lowering.
whitequark [Tue, 4 Jun 2019 12:26:09 +0000 (12:26 +0000)]
compat.fhdl.specials: fix platform lowering.

get_tristate only has O/OE; the triple is created by get_input_output.

5 years agocompat.fhdl.module: implement some TODO'd deprecation warnings.
whitequark [Tue, 4 Jun 2019 12:00:02 +0000 (12:00 +0000)]
compat.fhdl.module: implement some TODO'd deprecation warnings.

5 years agobuild.run: fix product extraction to work on Windows.
whitequark [Tue, 4 Jun 2019 11:40:56 +0000 (11:40 +0000)]
build.run: fix product extraction to work on Windows.

Before this commit, it would fail with a "Permission denied" error.

5 years agobuild.plat: hide executed commands in quiet builds on Windows.
whitequark [Tue, 4 Jun 2019 11:34:18 +0000 (11:34 +0000)]
build.plat: hide executed commands in quiet builds on Windows.

5 years agobuild.plat: allow (easily) overriding with an empty string on Windows.
whitequark [Tue, 4 Jun 2019 11:33:51 +0000 (11:33 +0000)]
build.plat: allow (easily) overriding with an empty string on Windows.

5 years agocompat.fhdl.module: CompatModule should be elaboratable.
whitequark [Tue, 4 Jun 2019 11:10:46 +0000 (11:10 +0000)]
compat.fhdl.module: CompatModule should be elaboratable.

Fixes #83.

5 years agobuild.res: use ConstraintError iff a constraint invariant is violated.
whitequark [Tue, 4 Jun 2019 10:23:27 +0000 (10:23 +0000)]
build.res: use ConstraintError iff a constraint invariant is violated.

In particular don't use it for type errors.

5 years agohdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
whitequark [Tue, 4 Jun 2019 10:19:54 +0000 (10:19 +0000)]
hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.

5 years agovendor.board: split off into nmigen-boards package.
whitequark [Tue, 4 Jun 2019 09:47:04 +0000 (09:47 +0000)]
vendor.board: split off into nmigen-boards package.

The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.

5 years agobuild.run: simplify using build products locally, e.g. for programming.
whitequark [Tue, 4 Jun 2019 09:13:24 +0000 (09:13 +0000)]
build.run: simplify using build products locally, e.g. for programming.

5 years agobuild.res: simplify emission of port constraints on individual bits.
whitequark [Tue, 4 Jun 2019 08:37:52 +0000 (08:37 +0000)]
build.res: simplify emission of port constraints on individual bits.

5 years agoClean up imports.
whitequark [Tue, 4 Jun 2019 08:18:50 +0000 (08:18 +0000)]
Clean up imports.

This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.

5 years agobuild.run: extract from build.plat.
whitequark [Tue, 4 Jun 2019 07:53:34 +0000 (07:53 +0000)]
build.run: extract from build.plat.

5 years agovendor.board.tinyfpga_bx: clk16 pin does not have a global buffer.
whitequark [Tue, 4 Jun 2019 06:43:10 +0000 (06:43 +0000)]
vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer.

Fixes #82.

5 years agovendor.board.tinyfpga_bx: fix typo.
whitequark [Tue, 4 Jun 2019 06:20:01 +0000 (06:20 +0000)]
vendor.board.tinyfpga_bx: fix typo.

5 years agovendor.conn.pmod: implement.
whitequark [Mon, 3 Jun 2019 16:47:41 +0000 (16:47 +0000)]
vendor.conn.pmod: implement.

Fixes #79.

5 years agoexamples: reorganize into examples/basic and examples/board.
whitequark [Mon, 3 Jun 2019 16:16:44 +0000 (16:16 +0000)]
examples: reorganize into examples/basic and examples/board.

5 years agovendor.board: extract package.
whitequark [Mon, 3 Jun 2019 16:14:59 +0000 (16:14 +0000)]
vendor.board: extract package.

5 years agovendor.tinyfpga_bx: add connectors.
whitequark [Mon, 3 Jun 2019 15:38:49 +0000 (15:38 +0000)]
vendor.tinyfpga_bx: add connectors.

5 years agovendor.icestick: add connectors.
whitequark [Mon, 3 Jun 2019 15:03:43 +0000 (15:03 +0000)]
vendor.icestick: add connectors.

5 years agovendor.ice40_hx1k_blink_evn: add (some) connectors.
whitequark [Mon, 3 Jun 2019 15:03:34 +0000 (15:03 +0000)]
vendor.ice40_hx1k_blink_evn: add (some) connectors.

I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.

5 years agobuild.{plat,res}: add support for connectors.
whitequark [Mon, 3 Jun 2019 15:02:15 +0000 (15:02 +0000)]
build.{plat,res}: add support for connectors.

Fixes #77.

5 years agobuild.dsl: add support for connectors.
whitequark [Mon, 3 Jun 2019 13:03:49 +0000 (13:03 +0000)]
build.dsl: add support for connectors.

5 years agocompat.fhdl.specials: TSTriple is not an elaboratable.
whitequark [Mon, 3 Jun 2019 09:39:38 +0000 (09:39 +0000)]
compat.fhdl.specials: TSTriple is not an elaboratable.

5 years agovendor.fpga.lattice_ice40: implement differential output buffers.
whitequark [Mon, 3 Jun 2019 09:23:11 +0000 (09:23 +0000)]
vendor.fpga.lattice_ice40: implement differential output buffers.

5 years agovendor.fpga.lattice_ice40: implement differential input buffers.
whitequark [Mon, 3 Jun 2019 08:38:12 +0000 (08:38 +0000)]
vendor.fpga.lattice_ice40: implement differential input buffers.

5 years agovendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
whitequark [Mon, 3 Jun 2019 07:54:28 +0000 (07:54 +0000)]
vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.

5 years agovendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers.
whitequark [Mon, 3 Jun 2019 07:43:02 +0000 (07:43 +0000)]
vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers.

5 years agolib.io: add i_clk and o_clk to pin layout with xdr>=1.
whitequark [Mon, 3 Jun 2019 05:56:18 +0000 (05:56 +0000)]
lib.io: add i_clk and o_clk to pin layout with xdr>=1.

5 years agohdl.rec: unbreak hasattr(rec, ...).
whitequark [Mon, 3 Jun 2019 07:16:09 +0000 (07:16 +0000)]
hdl.rec: unbreak hasattr(rec, ...).

hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().

5 years agobuild.{dsl,plat,res}: allow dir="oe".
whitequark [Mon, 3 Jun 2019 04:39:05 +0000 (04:39 +0000)]
build.{dsl,plat,res}: allow dir="oe".

Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.

5 years agolib.io: allow dir="oe".
whitequark [Mon, 3 Jun 2019 04:28:53 +0000 (04:28 +0000)]
lib.io: allow dir="oe".

Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.

5 years agobuild.{res,plat}: use xdr=0 as default, not xdr=1.
whitequark [Mon, 3 Jun 2019 03:32:30 +0000 (03:32 +0000)]
build.{res,plat}: use xdr=0 as default, not xdr=1.

The previous behavior was semantically incorrect.

5 years agobuild.res: allow requesting raw ports, with dir="-".
whitequark [Mon, 3 Jun 2019 03:17:20 +0000 (03:17 +0000)]
build.res: allow requesting raw ports, with dir="-".

This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.

5 years agolib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.
whitequark [Mon, 3 Jun 2019 03:29:27 +0000 (03:29 +0000)]
lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.

5 years agovendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
whitequark [Mon, 3 Jun 2019 03:01:56 +0000 (03:01 +0000)]
vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.

5 years agobuild.res: if not specified, request resource #0.
whitequark [Mon, 3 Jun 2019 02:54:17 +0000 (02:54 +0000)]
build.res: if not specified, request resource #0.

This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.

5 years agovendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
whitequark [Mon, 3 Jun 2019 02:48:55 +0000 (02:48 +0000)]
vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.

The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.

5 years agohdl.ir: accept LHS signals like slices as Instance io ports.
whitequark [Mon, 3 Jun 2019 02:39:14 +0000 (02:39 +0000)]
hdl.ir: accept LHS signals like slices as Instance io ports.

This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)

5 years agohdl.dsl: allow adding submodules with computed name, like with domains.
whitequark [Mon, 3 Jun 2019 02:22:55 +0000 (02:22 +0000)]
hdl.dsl: allow adding submodules with computed name, like with domains.

5 years agohdl.ir: accept expanded (kind, name, value) tuples in Instance.
whitequark [Mon, 3 Jun 2019 02:12:01 +0000 (02:12 +0000)]
hdl.ir: accept expanded (kind, name, value) tuples in Instance.

This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.

5 years agobuild.{res,plat}: propagate extras to pin fragment factories.
whitequark [Mon, 3 Jun 2019 01:58:43 +0000 (01:58 +0000)]
build.{res,plat}: propagate extras to pin fragment factories.

This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.

5 years agobuild.res: simplify. NFC.
whitequark [Mon, 3 Jun 2019 01:28:34 +0000 (01:28 +0000)]
build.res: simplify. NFC.

5 years agobuild.dsl: require a dict for extras instead of a stringly array.
whitequark [Sun, 2 Jun 2019 23:36:21 +0000 (23:36 +0000)]
build.dsl: require a dict for extras instead of a stringly array.

Fixes #72.

5 years agovendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.
whitequark [Sun, 2 Jun 2019 04:12:50 +0000 (04:12 +0000)]
vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.

5 years agovendor.tinyfpga_{b→bx}
whitequark [Sun, 2 Jun 2019 04:11:06 +0000 (04:11 +0000)]
vendor.tinyfpga_{b→bx}

5 years agovendor.tinyfpga_b: fix IO_STANDARD.
whitequark [Sun, 2 Jun 2019 04:04:07 +0000 (04:04 +0000)]
vendor.tinyfpga_b: fix IO_STANDARD.

5 years agovendor.tinyfpga_b: implement.
Simon Kirkby [Sun, 2 Jun 2019 01:20:09 +0000 (09:20 +0800)]
vendor.tinyfpga_b: implement.

5 years agovendor.icestick: fix typo.
whitequark [Sun, 2 Jun 2019 01:13:03 +0000 (01:13 +0000)]
vendor.icestick: fix typo.

5 years agoTravis: update install script.
whitequark [Sat, 1 Jun 2019 17:09:41 +0000 (17:09 +0000)]
Travis: update install script.

5 years agovendor.ice40_hx1k_blink_evn: implement.
whitequark [Sat, 1 Jun 2019 16:47:47 +0000 (16:47 +0000)]
vendor.ice40_hx1k_blink_evn: implement.

5 years agovendor.icestick: implement.
whitequark [Sat, 1 Jun 2019 16:47:20 +0000 (16:47 +0000)]
vendor.icestick: implement.

5 years agovendor.fpga.lattice_ice40: implement.
whitequark [Sat, 1 Jun 2019 16:46:50 +0000 (16:46 +0000)]
vendor.fpga.lattice_ice40: implement.

5 years agobuild.plat: implement.
whitequark [Sat, 1 Jun 2019 16:43:27 +0000 (16:43 +0000)]
build.plat: implement.

5 years agobuild.res: always return a Pin record.
whitequark [Sat, 1 Jun 2019 16:41:30 +0000 (16:41 +0000)]
build.res: always return a Pin record.

In the simple cases, a Pin record consisting of exactly one field
is equivalent in every way to this single field. In the more complex
case however, it can be used as a record, making the code more robust
such that it works with both bidirectional and unidirectional pins.

5 years agobuild.res: accept a list of clocks in ConstraintManager constructor.
whitequark [Sat, 1 Jun 2019 15:41:41 +0000 (15:41 +0000)]
build.res: accept a list of clocks in ConstraintManager constructor.

5 years agoback.rtlil: allow specifying platform for convert().
whitequark [Sun, 26 May 2019 17:10:56 +0000 (17:10 +0000)]
back.rtlil: allow specifying platform for convert().

5 years agoAdd versioneer.
whitequark [Sun, 26 May 2019 11:20:13 +0000 (11:20 +0000)]
Add versioneer.

5 years agohdl.ir: silence unused elaboratable warning on interpreter crash.
whitequark [Sun, 26 May 2019 10:42:52 +0000 (10:42 +0000)]
hdl.ir: silence unused elaboratable warning on interpreter crash.

5 years agobuild.res: add ConstraintManager.
Jean-François Nguyen [Fri, 26 Apr 2019 12:37:08 +0000 (14:37 +0200)]
build.res: add ConstraintManager.

5 years agobuild.dsl: make Pins and DiffPairs iterable.
whitequark [Sat, 25 May 2019 22:37:32 +0000 (22:37 +0000)]
build.dsl: make Pins and DiffPairs iterable.

Returns pin names.

5 years agobuild.dsl: improve repr of Pins() and DiffPairs().
whitequark [Sat, 25 May 2019 22:23:03 +0000 (22:23 +0000)]
build.dsl: improve repr of Pins() and DiffPairs().

5 years agohdl.rec: allow providing fields during construction.
whitequark [Sat, 25 May 2019 21:57:07 +0000 (21:57 +0000)]
hdl.rec: allow providing fields during construction.

This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.

5 years agoConsider Instances a part of containing fragment for use-def purposes.
whitequark [Sat, 25 May 2019 20:09:26 +0000 (20:09 +0000)]
Consider Instances a part of containing fragment for use-def purposes.

Fixes #70.

5 years agoAdd import so that Tristate.elaborate builds
Chris Osterwood [Mon, 20 May 2019 14:39:21 +0000 (07:39 -0700)]
Add import so that Tristate.elaborate builds

5 years agohdl.ir: when adding sync domain to a design, also add it to ports.
whitequark [Wed, 15 May 2019 06:44:50 +0000 (06:44 +0000)]
hdl.ir: when adding sync domain to a design, also add it to ports.

Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.

5 years agohdl.ir: during port propagation, defs should take priority over uses.
whitequark [Mon, 13 May 2019 15:34:13 +0000 (15:34 +0000)]
hdl.ir: during port propagation, defs should take priority over uses.

5 years agoback.rtlil: assign undriven signals to their reset value.
whitequark [Mon, 13 May 2019 07:56:11 +0000 (07:56 +0000)]
back.rtlil: assign undriven signals to their reset value.

Fixes #35.

5 years agohdl: make all public Value classes other than Record final.
whitequark [Sun, 12 May 2019 05:36:35 +0000 (05:36 +0000)]
hdl: make all public Value classes other than Record final.

In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)

Fixes #65.

5 years agohdl.ir: only pull explicitly specified ports to toplevel, if any.
whitequark [Sun, 12 May 2019 05:21:23 +0000 (05:21 +0000)]
hdl.ir: only pull explicitly specified ports to toplevel, if any.

Fixes #30.