ruby: Don't set the block data when a store conditional fails

Previously the Sequencer upon a Store Conditional would
unconditionally set the data of the memory location. This change
checks and prevents a failed Store Conditional from modifying any
data.

Change-Id: Id63c9579d8f054f0e95c6d338a7e31aa48762755
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Fix unproxing of VectorParams

Previously proxy vector parameters would resolve correctly only for
Parent.all. Any other proxy such as Parent.any, or exact ones such as
Parent.addr_range would resolve to a *vector* of the right value
resulting into a vector of a vector. For example if we set:

DirectoryController0.addr_range = [0x100000-0x1fffff, 0x200000-0x2fffff]
DirectoryMemory0.addr_range = Parent.addr_range

where DirectoryController0 is the parent SimObject of DirectoryMemory0
after unproxying the Parent.addr_range VectorParam we would get

DirectoryMemory0.addr_range = [[0x100000-0x1fffff, 0x200000-0x2fffff]]

This change unifies handling of all three proxies to the same correct
unproxy mechanism.

Change-Id: Ie5107f69f58eb700b3e1b92c55210e0d53e6788d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2901
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dev, arm: ignore writes to the SCU

Change-Id: I31808b6d7ca2bc2af41deaec747e3a13bd4f77d2
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3261
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: check address range in the SystemC example

Using a wrong offset or memory size may lead to segmentation faults.
This patch adds an address range check and produces an error message.

Change-Id: I79a72c05879266daf61a83367fe4ae386d1958a4
Reviewed-on: https://gem5-review.googlesource.com/3482
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>

misc: Reorder sources in util/tlm and rewrite build scripts

* Use one SConstruct to build everything instead of one SConstruct for
  each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
  ensures that SystemC does not need to be installed on the host and
  avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes

Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ext: Revamp the systemc SConscripts.

The existing scripts were including pthread code and QT code at the same
time, and also insisting on an having a set of architecture specific
source files for whatever the current architecture is.

This change selects using either QT or pthreads based on the host
architecture, distributes accumulating source files, list source files
explicitly (to avoid including redundant coroutine libraries) and makes
scons insist on an architecture specific QT implementation only if QT is
being used. It also defines a preprocessor symbol which tells some headers
whether or not pthreads are being used, and also clones the scons
environment to avoid leaking flags into the main environment used to
compile gem5 itself.

If the host architecture isn't supported by systemc, a warning will be
printed, and the various build products and SConscript files will be
skipped over.

Change-Id: I1a40123a11e49e02922a054f093246cf197087bf
Reviewed-on: https://gem5-review.googlesource.com/3461
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Rework how VEX prefixes are decoded.

Remove redundant information from the ExtMachInst, hash the vex
information to ensure the decode cache works properly, print the vex info
when printing an ExtMachInst, consider the vex info when comparing two
ExtMachInsts, fold the info from the vex prefixes into existing settings,
remove redundant decode code, handle vex prefixes one byte at a time and
don't bother building up the entire prefix, and let instructions that care
about vex use it in their implementation, instead of developing an entire
parallel decode tree.

This also eliminates the error prone vex immediate decode table which was
incomplete and would result in an out of bounds access for incorrectly
encoded instructions or when the CPU was mispeculating, as it was (as far
as I can tell) redundant with the tables that already existed for two and
three byte opcodes. There were differences, but I think those may have
been mistakes based on the documentation I found.

Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES
instructions which are still legal in that mode. A valid VEX prefix would
look like an LDS/LES with an otherwise invalid modrm encoding, so use that
as a signal to abort processing the VEX and turn the instruction into an
LES/LDS as appropriate.

Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c
Reviewed-on: https://gem5-review.googlesource.com/3501
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

x86: sim: Make 32 bit x86 processes work again.

When the LiveProcess class was renamed to be just Process, the CL author
also changed the syscall function from a virtual function into a regular
one. Unfortunately, the I386Process class overrode the syscall function
to adjust the return address so that control would return to the right
place. Without that adjustment, 32 bit x86 process would segfault and die
immediately after their first system call.

This change reinstates the virtual specifier on the base syscall function,
and adds an override keyword on the I386Process's version so that it won't
be orphaned again in the future. It also fixes some small style issues the
style checker script complained about.

Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d
Reviewed-on: https://gem5-review.googlesource.com/3500
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: generate fully qualified paths for cscope

Change-Id: I318c185b117b9608110544526fbaaa3fdcdeb8bc
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU

The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.

Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

python: Fix PyEvent reference counting bug

The current implementation of reference counting for PyEvents only
partially works. The native object is currently kept alive while it is
in the event queue. However, if the Python object goes out of scope,
the Python side of this object is garbage collected which leaves a
"dangling" native object. This results in confusing error messages
where PyBind is unable to find the Python implementation of an event
when it is triggered.

Implement reference counting using the generalized reference counting
API instead.

Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3222
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim: Add hooks to implement event reference counting

We currently only support deleting an event if it is triggered and not
re-scheduled. This is fine for most native code. However, there are
cases where Python needs to count references to make sure that the
Python object stays live while the native object is live.

Generalise the mechanism used to implement by adding reference
counting hooks to the event base class:

  * Event::acquire() / Event::acquireImpl()
  * Event::release() / Event::releaseImpl()

These calls can be used to implement both reference counting and the
existing AutoDelete functionality. The default implementation in Event
maintains backwards compatibility with the existing AutoDelete feature
by ignoring acquireImpl() and deleting the event on releaseImpl() if
it isn't scheduled anymore.

Since AutoDelete functionality is no longer the only way events can be
managed, this change introduces the new Managed flag. This flag
activates automatic memory management. The acquireImpl()/releaseImpl()
methods are only called from acquire()/release() it is set. To
maintain backwards compatibility, AutoDelete is used as an alias for
Managed.

Change-Id: I5637984c906a9d44c22780712cf1c521b8297149
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix bad stack initialization

This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.

Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Reviewed-on: https://gem5-review.googlesource.com/3401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

arch-arm: Fix some poorly done type max and min in NEON

The ISA code for ARM calculates min and max elements for types using
bit manipulation. That triggers some warnings, treated as errors, as
the compiler can tell that there is an overflow and the sign
flips. Fixed using standard lib definitions instead.

Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

ext: Upgrade PyBind11 to version 2.1.1

Change-Id: I16870dec402d661295f9d013dc23e362b2b2c169
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3225
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

python: Prevent Python wrappers from deleting SimObjects

The PyBind wrappers could potentially delete SimObjects if they don't
have any references. This is not desirable since there could be
pointers to such objects within the C++ world. This problem doesn't
normally occur since Python typically holds a pointer to the root node
as long as the simulator is running.

Prevent SimObject and Param deletion by using a PyBind-prescribed
unique_ptr with a dummy deleter as the pointer wrapper for the Python
world.

Change-Id: Ied14602c9ee69a083a69c5dae1b5fcf8efb4548a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3224
Reviewed-by: Gabe Black <gabeblack@google.com>

python: Fix weird memory issue in wrapped AddrRange vectors

There is a weird issue with the PyBind wrapper of
vector<AddrRange>. Assigning new values to a param that is a vector of
AddrRange sometimes results in an out-of-bounds memory access.

We work around this issue by treating AddrRange vectors as opaque
types. This slightly changes the semantics of the wrapper since Python
now manipulates the real object rather than a copy that has been
converted to a list.

Change-Id: Ie027c06e7a7262214b43b19a76b24fe4b20426c5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3223
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

scons: Enable explicitly building something with no variant.

The SConstruct currently expects all explicit targets to be under a
variant directory like ARM or X86 which tells it what settings to use,
etc. There are things which scons knows how to build however, which do not
live under a variant directory, specifically everything under ext.

This change makes scons not look for a variant directory when it
encounters a target which is built by something in ext. This enables
things like explicitly building the systemc libraries, for example.

Change-Id: I8982a96fe49e3cb970ec78e11cea08703990c686
Reviewed-on: https://gem5-review.googlesource.com/3460
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Remove unused readline import

The readline module is imported by main.py but doesn't seem to be
used.

Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3421
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

base, sim, arch: Fix clang 5.0 warnings

Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:

  * Global templatized static functions result in a warning if they
    are not used. These should either be declared as static inline or
    without the static identifier to avoid the warning.

  * Some templatized classes contain static variables. The
    instantiated versions of these variables / templates need to be
    explicitly declared to avoid a compiler warning.

Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3420
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

base: Refactor the GDB code.

The new version modularizes the implementation of the various commands,
gets rid of dynamic allocation of the register cache, fixes some small
style problems, and uses exceptions to simplify error handling internal to
the GDB stub.

Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2
Reviewed-on: https://gem5-review.googlesource.com/3280
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

configs: fix cpu names in big.LITTLE example

CPU aliases have been dropped, this change fixes the big.LITTLE example.

Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/3300
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published as: 'Full-System
Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko <abutko@lbl.gov>
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2464
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ext: Include SystemC 2.3.1 into gem5

In the past it happened several times that some changes in gem5 broke the
SystemC coupling. Recently Accelera has changed the licence for SystemC
from their own licence to Apache2.0, which is compatible with gem5.
However, SystemC usually relies on the Boost library, but I was able to
exchange the boost calls by c++11 alternatives. The recent SystemC version
is placed into /ext and is integrated into gem5's build system. The goal is
to integrate some SystemC tests for the CI in some following patches.

Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Reviewed-on: https://gem5-review.googlesource.com/2240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Changes to boot Android N

necessary kernel command line options in FSConfig.py

Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d
Reviewed-on: https://gem5-review.googlesource.com/3320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Fix the multiplication microops.

If the operands were 64 bit, an intermediate calculation could lose a
carry bit. This change rearranges that intermediate calculation if the
operand width is large, and reworks the microop implementation in general
in an attempt to make it easier to understand.

Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea
Reviewed-on: https://gem5-review.googlesource.com/3381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

python: Add a helper function to create Python events

Add a helper function, m5.event.create(), to create events from
Python. This function takes a callable Python object (e.g., a
function) as an argument and optionally a priority as a keyword
argument. This function was accidentally dropped from the public API
when switching to PyBind.

Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3220
Reviewed-by: Gabe Black <gabeblack@google.com>

style: fix line lengths and include ordering

The style checker complains about line length and ordering for these
files. This fix should make these two files kosher.

Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d
Reviewed-on: https://gem5-review.googlesource.com/3380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

cpu: fix problem with forwarding and locked load

If a (regular) store is followed closely enough by a locked load that
overlaps, the LSQ will forward the store's data to the locked load and
never tell the cache about the locked load.  As a result, the cache will
not lock the address and all future store-conditional requests on that
address will fail.  This patch fixes that by preventing forwarding if
the memory request is a locked load and adding another case to the LSQ
forwarding logic that delays the locked load request if a store in the
LSQ contains all or part of the data that is requested.

[Merge second and last if blocks because their bodies are the same.]

Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
Reviewed-on: https://gem5-review.googlesource.com/2400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, dev: stub out GIC distributor interrupt groups

We don't implement the GICD_IGROUPRn registers, which is allowed, but
to be correct, they should be RAZ/WI (read as zero, writes ignored).

Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Make the VNC server more resilient.

If the client does something bad, don't kill the whole simulation, just
complain, drop the client and keep going.

Change-Id: I824f2d121e2fe03cdf4323a25c192b68e0370acc
Reviewed-on: https://gem5-review.googlesource.com/3200
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Make the remote GDB stub more resilient to bad connections.

Currently, if the remote gdb stub fails to read a byte from an incoming
packet because the connection has been dropped, the read call will return
anyway and the calling code will have no way to know something bad
happened. It might reattempt the read over and over again waiting for some
particular byte, doomed to never make forward progress.

This change modifies the remote GDB code so that if a read or write call
fails, it will instead detach from the debugger and continue. Before this
change, When simulating a port scan, ie connecting to the debugger port
and then immediately dropping the connection using this command:

nc -v -n -z -w 1 127.0.0.1 7000

gem5 would enter the previously described death spiral. After it, gem5
detaches from the bad connection and resumes execution. Subsequently
attaching with gdb was successful.

This code is written in a C centric style, and would benefit from some
refactoring.

Change-Id: Ie3c0bb35b9cfe3671d0f731e3907548bae0d292f
Reviewed-on: https://gem5-review.googlesource.com/3180
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

syscall_emul: Fix undefined macro behavior

Clang's UBSAN implementation complains about macros that expand to
expressions that contain 'defined'. Explicitly set the various feature
macros to 1 or 0 to avoid this issue.

Change-Id: Iba239dacfe526c43ab9c5da5183a350fc4fdc57d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3241

arm: Remove unused DumpStatsPCEventF class in FreeBSD system

The DumpStatsPCEventF is declared but lacks an implementation. This
confuses RTTI in clang. Remove this class since it is clearly not
needed.

Change-Id: Ib95f09f2ba8593f8d0e072b96afd5f8a9ed31070
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3240
Reviewed-by: B.A. Zeeb <baz21@cam.ac.uk>

scons: Use the generalized switching headers on the GPU ISA.

Now that the switching header implementation has been generalized, there's
no need to have two nearly identical implementations for the two different
groups of headers.

Change-Id: Ie7c24fcddbc672ac5ca2d69bfc35696f42c55580
Reviewed-on: https://gem5-review.googlesource.com/2984
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

scons: arch: Generalize the switching header code.

Factor out the ISA ness of the switching header generating function. Also
turn it into a SCons builder which builds a single header, and a wrapping
method which uses the builder on a group of header files which all target
the same subdirectory.

Change-Id: I87705f97b6ebd9baebd4ebcfea19cc1218a64ad0
Reviewed-on: https://gem5-review.googlesource.com/2983
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Fix up some configs to not use CPU aliases.

Support for CPU aliases were removed recently.

Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f
Reviewed-on: https://gem5-review.googlesource.com/3100
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

scons: Get rid of the all_isa_deps variable.

This value can be computed more directly and more locally near where it's
used.

Change-Id: Ib5f45015494a6c8033ce0ac4b8931688f37492c8
Reviewed-on: https://gem5-review.googlesource.com/2982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: Add the --listener-loopback-only command line option.

This option invokes the Listener::loopbackOnly() static function which
will make the port listeners bind to the loopback device exclusively and
ignore connections on other devices. That prevents external agents like
port scanners from disrupting simulations with spurious connections.

Change-Id: I46b22165046792a6f970826c109bdbce7db25c84
Reviewed-on: https://gem5-review.googlesource.com/3082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Expose the listener loopbackOnly function to python.

Change-Id: Ibb405af54a46a93706a6f476b5314491e84be0c8
Reviewed-on: https://gem5-review.googlesource.com/3081
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Teach the socket listeners how to bind to the loopback.

The loopback device will allow access to various services like remote GDB
debugging, connecting to the terminal, etc., without letting external
agents like port scanners connect and disrupting the simulation.

Change-Id: I76dccbf152fa278ae9f342b25f7e345a1329fbe4
Reviewed-on: https://gem5-review.googlesource.com/3080
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

style: Treat PyBind headers as Python headers

Some PyBind11 headers need to include Python.h. This means that we need
to include PyBind11 headers before any standard library headers. Enforce
this by applying the Python.hh rules for anything in pybind11/.

Change-Id: Id175a4f613960a17f84f98b81bfd02806e905d5a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3120
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

python: Fix debug flag listing regression

The PyBind11 changes slightly modified gem5's internal debug
interfaces. The corresponding change to the public API went missing
before the new bindings were merged. This change updates the Python
glue to use the new interface.

Change-Id: I3ecca5a3f6c35b99d55126d697371124f81a12dd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3140
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util, arm: Support mmapped m5ops on aarch64

Add support for memory-mapped m5ops in the aarch64 version of the m5
utility. To enable support for memory-mapped m5ops, compile the tool
with the define M5OP_ADDR set to the base of the m5op PA range.

Change-Id: I13e21e48536b9849bf4081411b66b2f350f7a8ac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2966

arm: Enable m5ops by default for VExpress_GEM5_V1

Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part
of the CS5 address range in the RS1/RS2 memory map.

Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2965

arm: Add support for memory-mapped m5ops

Add support for a memory mapped m5op interface. When enabled, the TLB
intercepts accesses in the 64KiB region designated by the
ArmTLB.m5ops_base parameter. An access to this range maps to a
specific m5op call. The upper 8 bits of the offset into the range
denote the m5op function to call and the lower 8 bits denote the
subfunction.

Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2964

kvm, arm: Fix incorrect PSTATE sync

The state transfer code wasn't reading back PSTATE correctly from the
CPU prior to updating the thread context and was incorreclty writing
the register as a 32-bit value when updating KVM. Correctly read back
the state before updating gem5's view of PSTATE and cast the value to
a uint64_t.

Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2963
Reviewed-by: Rahul Thakur <rjthakur@google.com>

util: Correctly handle short writes in m5 (read|exec)file

The m5 tool has subcommands that writes a file to the simulated file
system. The implementation of this command currently doesn't check the
return value from write, which leads to compiler warnings and
potentially incorrect behavior. Add the necessary checks.

Change-Id: If558534d3245aa24cf15edf06bd0af4c6ba3908c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2962
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Add the m5_loadsymbol pseudo op to the m5 tool

Change-Id: Ib8bf4eac77170db8b2bf44796fd9d46b02217d03
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Fix incorrect use of m5_loadsymbol

It seems like the m5 utility incorrectly called m5_loadsymbol instead
of m5_addsymbol. Judging by the signature of the loadsymbol command,
the expected behavior is to add a new symbol to gem5's symbol
table. This is behavior is implemented by m5_addsymbol.

Change-Id: I83b61c48d6f8d7b1e8b57d884dfca00481c83c3a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2961
Reviewed-by: Gabe Black <gabeblack@google.com>

misc: fix build failure in cxx_config example

Fix a missing header in the cxx_config example which is used as a
simple example of using libgem5.so without python.

Change-Id: I758bfe42ba735ce0c7eaedd49b94a130e3bd21e3
Reviewed-on: https://gem5-review.googlesource.com/3000
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Get rid of the PHONY_BASE construction variable.

The value of that variable can be computed more directly and more locally
to where it's consumed.

Change-Id: I5ca1f732a34e22d4dae2aeb6ee7fc8adebe1caa0
Reviewed-on: https://gem5-review.googlesource.com/2981
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util: Fix incorrect return type in m5 writefile

Change-Id: Ic24a1c3c1488e970ed27bb6b99262d201f535384
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2960
Reviewed-by: Gabe Black <gabeblack@google.com>

scons: Replace str(foo.get_contents()) with foo.get_text_contents().

For Value() nodes, the get_contents() method and the get_text_contents()
method are just aliases to the same thing, both of which return a value
which has already been converted using str(). The str() which was included
explicitly in the SConscript was redundant, except that it showed that the
value from get_contents was being treated as a string. To avoid the
redundancy but to still leave a hint to the value's type, this change
converts those bits of code to use get_text_contents() and removes the
str().

Change-Id: I8f7da9b652f749e741b553c9a0e2248ae15ec3ca
Reviewed-on: https://gem5-review.googlesource.com/3084
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Make env['USE_PYTHON'] a source for createEnumStrings.

That clues scons in to the fact that the contents of the target of that
function depends on the value of that construction variable.

Change-Id: I803322ea1a178152da3d95dffffe20acd4271c88
Reviewed-on: https://gem5-review.googlesource.com/3083
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Remove support for CPU aliases.

This was added for backwards compatability, but it adds a decent amount
of complexity.

The table below shows what CPU class name to use in place of a given
alias.

+==========+========================================================+
|  Alias   |                       CPU class                        |
+==========+========================================================+
| timing   | TimingSimpleCPU                                        |
| atomic   | AtomicSimpleCPU                                        |
| minor    | MinorCPU                                               |
| detailed | DrivO3CPU                                              |
| kvm      | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch |
| trace    | TraceCPU                                               |
+==========+========================================================+

Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08
Reviewed-on: https://gem5-review.googlesource.com/2940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

syscall_emul: Argument retrieval bug fix

This commit fixes a stack-buffer underflow
by fixing the way the array is indexed.

Change-Id: I44400e2b99a2f8e1f48f673cd110b9dcd6480a72
Reviewed-on: https://gem5-review.googlesource.com/3040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

scons: Merge reading test SConscripts into makeEnv.

We're already visiting each of the environments, there's no reason to
track them all and then set up test SConscripts on a second pass.

Change-Id: I2d1166f58ac907e874d6ad5de7bd53ff7ad645f8
Reviewed-on: https://gem5-review.googlesource.com/2980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Fix the compiler flag used for partial linking.

It seems that g++ can generally handle the -r flag for generating a
relocatable object file, but ld can't always handle the  --relocatable
flag.

Change-Id: I15f32e469590a814131d4e992b392a7ad6c52b83
Reviewed-on: https://gem5-review.googlesource.com/3001
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Remove SWIG

Remove SWIG-specific Python code.

Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2922
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

base, sim, dev: Remove SWIG

Remove SWIG guards and SWIG-specific C++ code.

Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

scons: Remove SWIG support

Remove remaining SWIG support from the build infrastructure.

Change-Id: I7549cd0f952ca3a51481918eefef3a29f03af359
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2920
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

python: Use PyBind11 instead of SWIG for Python wrappers

Use the PyBind11 wrapping infrastructure instead of SWIG to generate
wrappers for functionality that needs to be exported to Python. This
has several benefits:

  * PyBind11 can be redistributed with gem5, which means that we have
    full control of the version used. This avoid a large number of
    hard-to-debug SWIG issues we have seen in the past.

  * PyBind11 doesn't rely on a custom C++ parser, instead it relies on
    wrappers being explicitly declared in C++. The leads to slightly
    more boiler-plate code in manually created wrappers, but doesn't
    doesn't increase the overall code size. A big benefit is that this
    avoids strange compilation errors when SWIG doesn't understand
    modern language features.

  * Unlike SWIG, there is no risk that the wrapper code incorporates
    incorrect type casts (this has happened on numerous occasions in
    the past) since these will result in compile-time errors.

As a part of this change, the mechanism to define exported methods has
been redesigned slightly. New methods can be exported either by
declaring them in the SimObject declaration and decorating them with
the cxxMethod decorator or by adding an instance of
PyBindMethod/PyBindProperty to the cxx_exports class variable. The
decorator has the added benefit of making it possible to add a
docstring and naming the method's parameters.

The new wrappers have the following known issues:

  * Global events can't be memory managed correctly. This was the
    case in SWIG as well.

Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2231
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

ext: Fix undefined macro in pybind

Change-Id: I63a2506d3c028f78cacce8308e2f0e4880531dec
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2230
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

ext: Add pybind rev f4b81b3

Change-Id: I52e4fc9ebf2f59da57d8cf8f3e37cc79598c2f5f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2229
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

scons: Remove the SPAWN hack added earlier.

A previous change forced scons to spawn child processes by exec-ing it
directly rather than going through the shell because the command line
length would be too long for the shell to handle. Now that incremental
linking should keep the command line lengths more under control, that
change should no longer be necessary.

Change-Id: I9e82a62083afd1414324a7fd697bd6d4b76367ae
Reviewed-on: https://gem5-review.googlesource.com/2947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Group Source-s based on what SConscript included them.

The groups won't be perfectly balanced or optimally planned, but this
requires no thought and breaks the object files down into a reasonable
number of reasonably sized groups.

Change-Id: I6542fc807aaf356a9be751093f68e2e29f0b1586
Reviewed-on: https://gem5-review.googlesource.com/2946
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Put Source objects in groups and partially link them.

The groups will be linked together into intermediate partially linked
object files. Right now the hierarchy is assumed to be flat, but with some
effort it could be extended to allow truly hierarchical linking.

Change-Id: I77b77710554e5f05e8b00720a0170afaf4afac2d
Reviewed-on: https://gem5-review.googlesource.com/2945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Add builders for partially linked object files.

These intermediate object files can be used to perform a hierarchical
link.

Change-Id: I27634731734eebe6531ce6b0894abdd59ffdc5c9
Reviewed-on: https://gem5-review.googlesource.com/2944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-sparc: Fix wrong indentation causing warnings for gcc 6

Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Add ATA command used in recent Linux kernels

Add a case for the ATA command ATAPI_IDENTIFY_DEVICE.
This avoids the panic: Unsupported ATA command when booting a recent Linux
kernel. This was tested on 4.8.13.

Change-Id: Ib297a2c02da0730d8698c59801254dd0f5ee9f7f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/2863
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

scons: Add a Transform() for when linking shared libraries.

Change-Id: I7ddba0cc7be559633328011c1c7e2282f509b78c
Reviewed-on: https://gem5-review.googlesource.com/2943
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Find ext build directories automatically.

The ext directories with SConscripts in them are easy to find
automatically. Avoid boilerplate listing them out and SConscript()ing
them manually.

Change-Id: Ib723882aebc00e639eb8ec44904bb05ffa2c6b55
Reviewed-on: https://gem5-review.googlesource.com/2942
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Add MAINTAINERS file

This file defines all of the commit keywords used for gem5 commits and
the maintainter(s) for each of these keywords.

This patch introduces a number of new keywords, and changes to previous
keywords. The new keywords better follow gem5's directory structure and
are more extensible.

Currently, most keywords do not have a maintainer. More maintainers will
be added as more people volunteer to be maintainers.

This patch also updates the CONTRIBUTING.md file to point to this file
instead of listing the keywords separately. When this file is committed
the wiki will also be updated accordingly.

Change-Id: Ib0abfeb39a3ca01b74b340e24dc9a2cd95ff813f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/2760
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: Remove unused options from tests.py

The test sub-command in tests.py incorrectly accepts various
formatting options in its usage string. These options aren't needed
since the test command doesn't produce any output.

Change-Id: I6d4731aa32a25a2286aa66548eaa0154a9392f79
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

x86: fixed branching() computation for branch uops

When a branch micro-op belongs to a flow and the micro-op does not change
the nPC and just updates the nuPC (like a 'rep movs' flow), branching()
function always returns not-taken no matter  actual micro-branch outcome.
Provided fix adds to the equation  nuPC attribute checking since these kind
of branch micro-op only updates that pointer.

This issue has been found while debugging the performance of a copy-loop
implemented with memcopy function. Without the fix, 'rep movss' internal
micro-branch was always predicted as not-taken causing an squash event
after every branch micro-branch execution.

Using the provided test, branch mispredition went from 1922 without the fix
to 7.

Change-Id: I1bcbefae26aef47e3135817ef99b53d0ea0a98fa

scons: When spawning the linker process, don't involve the shell.

The command line can be too long, causing bash to choke. This means we can't
use any shell syntax like shell variables or redirection when linking, but
that should be easy to avoid.

Change-Id: Ie6c8ecab337cef6bd3c7e403346ced06f46f0993
Reviewed-on: https://gem5-review.googlesource.com/2780
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config, arm: Add an example power model

Add a script to demonstrate how power models can be wired to gem5
models. The script is meant as an example only and does not correlate
with any realistic implementation.

Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2721
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

power: Allow global stats in power equations

Allow global stats such as sim_seconds in power equations to make it
possible to convert from event stats to rate stats.

Change-Id: I429abe0ffadc0dbd162eb39e0897143be472ef65
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2720
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: minor fix for the gem5-SystemC/TLM coupling.

This patch has a minor fix for the coupling between gem5 and SystemC-TLM.

It also fixes some typos in the related documentation.

Change-Id: I894568729b8ebdacc5b81c9f46e8f9d137da210f
Reviewed-on: https://gem5-review.googlesource.com/2480
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

riscv: Fix crashes with large or frequent mmaps

This patch fixes a bug where increasing the mmap region too much causes
it to run into already-allocated memory, which causes gem5 to fail an
assertion.  Previously, the stack was incorrectly set up such that the
end of the mmap region and the top of the stack were the same address
and both would grow downward.  With this patch, the top of the stack has
been separated from the end of mmap and moved up, and the mmap region
now grows upward instead of downward.

[Rebase to master branch and remove dependencies.]

Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
Reviewed-on: https://gem5-review.googlesource.com/2680
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

power: Clarify the unit used for the power equations (W)

Change-Id: Iab5070fc9b666fcb5b49b0e2b99a4a1605b3b721
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

power: Add a voltage variable to power expressions

There is currently no good way of extracting the current operating
voltage in MathExprPowerModels. This change adds a magic variable,
'voltage', that can be referenced from such expressions to get the
current operating voltage.

Change-Id: Ice3c9a4a221921a542de5da52f83f3f88862d246
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2662
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

power: Add error checking to MathExprPowerModel

MathExprPower model currently doesn't print any useful error messages
if an expression fails to evaluate. To add insult to injury, the model
only detects a failure when dumping stats and not at
initialization. This change adds a verification step in startup() that
ensures that all of the referenced stats actually exist.

Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ruby: Fix MOESI_CMP_directory for new DMA status changes.

Multiple outstanding DMA requests introduced new DMA states that didn't
be considered into slicc code. This patch implements the missed DMA state
changes on MOESI_CMP_directory protocol.

Change-Id: I700d441d76556b7e77e0d507904af6ec6ba59cc2
Signed-off-by: Michael LeBeane <michael.lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/2380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

riscv: fix Linux problems with LR and SC ops

Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain.  This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.

Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
Reviewed-on: https://gem5-review.googlesource.com/2305
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
Reviewed-on: https://gem5-review.googlesource.com/2304
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Reviewed-on: https://gem5-review.googlesource.com/2345
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Reviewed-on: https://gem5-review.googlesource.com/2341
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

    commit 2c1286865fc2542a0586ca4ff40b00765d17b348
    Author: Brandon Potter <Brandon.Potter@amd.com>
    Date:   Wed Mar 1 14:52:23 2017 -0600

        syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update the stats for 70.twolf for x86 o3-timing mode.

The following CL changed the stats:

    commit 43418e7f81099072fb7d56dae11110ae1d858162
    Author: Brandon Potter <Brandon.Potter@amd.com>
    Date:   Wed Mar 1 13:07:43 2017 -0600

        syscall-emul: Move memState into its own file

It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.

Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update 04.gpu stats.

A new stat was added by the CL:

    commit b043dcf58ad766582aeab162fb855cc3fc95f2cf
    Author: Andreas Sandberg <andreas.sandberg@arm.com>
    Date:   Mon Feb 27 13:17:51 2017 +0000

        gpu-compute: Fix Python/C++ object hierarchy discrepancies

Change-Id: I665a7eb0bea19f379c5fbaaf4686fcbe8c008159
Reviewed-on: https://gem5-review.googlesource.com/2654
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

    commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
    Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
    Date:   Mon Feb 27 10:29:56 2017 +0000

        arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update the 40.m5threads stats.

The change below changed the stats for the o3 version of the 40.m5threads
regression.

    commit 2367198921765848a4f5b3d020a7cc5776209f80
    Author: Brandon Potter <brandon.potter@amd.com>
    Date:   Mon Feb 27 14:10:15 2017 -0500

        syscall_emul: [PATCH 15/22] add clone/execve for threading and
        multiprocess simulations

Change-Id: I601c58d8d1453cf93f2065ea5816b63b553610e0
Reviewed-on: https://gem5-review.googlesource.com/2652
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Rename num_syscalls to numSyscalls in the reference stats.

The name of the stat was changed in the following change which broke all the
reference outputs.

    commit 2367198921765848a4f5b3d020a7cc5776209f80
    Author: Brandon Potter <brandon.potter@amd.com>
    Date:   Mon Feb 27 14:10:15 2017 -0500

        syscall_emul: [PATCH 15/22] add clone/execve for threading and
        multiprocess simulations

Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.

The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.

    commit 073cb266079edddec64ea8cd5169dd2cbef8f812
    Author: Brandon Potter <brandon.potter@amd.com>
    Date:   Mon Feb 27 14:10:02 2017 -0500

        syscall_emul: [patch 14/22] adds identifier system calls

Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update the stats for 04.gpu for x86/linux/gpu-ruby-GPU_Rf0.

These stats were changed by this CL:

    commit a4b546c3a139aeb33f087422637ac06fc4477d11
    Author: Matthew Poremba <matthew.poremba@amd.com>
    Date:   Thu Jan 19 11:58:59 2017 -0500

        ruby: Add occupancy stats to MessageBuffers

Change-Id: I9713ed44d94cba424cdfa92d746dfe8007583b40
Reviewed-on: https://gem5-review.googlesource.com/2649
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update the solaris boot stats for the new op classes.

The change below introduced some new op classes which have their own stats,
and the counts the instructions used to be under have gone down.

    commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318
    Author: Fernando Endo <fernando.endo2@gmail.com>
    Date:   Sat Oct 15 14:58:45 2016 -0500

        cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb
Reviewed-on: https://gem5-review.googlesource.com/2648
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>