configs: Do not require default options for caches

This change is useful when using custom simulation scripts that do not
rely on configs/common/Options.py.
Without this change, the custom script always needed to provide some
value for cache sizes and HW prefetchers configuration; with this change
it is possible to provide no value and use what is defined in the core
configuration as default.

Change-Id: Id0e807c3fa224180d682f366c7307941bab8ce59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36776
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Clean up the __init__s in (Sub)OperandList.

These had a lot of for loops and ifs and nesting. Python lets you avoid
that, which makes the code easier to read and more intuitive to
understand.

Change-Id: I576bf1de9e5b2268717a535ca42f2db669d83ed2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35818
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Convert the x86 i8237 DMA controller to use RegBank.

This gets rid of the requirement to only modify one byte register at a
time, and builds some structure around individual DMA channels.

The one small feature of the i8237 that was implemented is still
implemented, but now with a method of the i8237.

Change-Id: Ibc2b2d75f2a3b860da3f28ae649c6f1a099bdf7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36815
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the "addr" call type in the m5 util.

This verifies that the slightly more complex --addr command line option
behaves as expected.

Also, like the inst and semi call type unit tests, it will either
attempt to successfully perform a call to the "sum" m5 op if it's told
it's running under gem5, or it will attempt to catch itself failing to
run that command by using mprotect to block its access to the mmap-ed
region and then looks at the siginfo_t to make sure the attempted access
was to the right place, etc.

It also will attempt to verify the details of the mmap if possible by
looking up information about its own mmap-ings in /proc. If the file it
would expect to find the mappings in doesn't exist, it prints a warning
and gives up. If it does, it looks through it to find the line
corresponding to the m5 ops, and then checks some details of the mapping
like its size and its offset in the target file. The offset would
correspond to the physical address if using the real /dev/mem.

Change-Id: Icc14cd9ac02eae93c56f1f2aa78fd67d8540a2f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27751
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix VExpressFastmodel timer configs

generic_timer is no longer in the return value of _on_chip_devices. We
should correct the _on_chip_devices. Furthermore, to prevent the timer
conflict with the fastmodel, we should remove unwanted timer.

Change-Id: I6ec7f9749546df3e8f125a5b96e7ed83cab2ea56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36379
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Make CPUID vendor string a param

Modern libraries such as ROCm, MPI, and libnuma use files in Linux'
sysfs to determine the system topology such as number of CPUs, cache
size, cache associativity, etc. If Linux does not recognize the vendor
string returned by CPUID in x86 it will do a generic initialization
which does not include creating these files. In the case of ROCm
(specifically ROCt) this causes failures when getting device properties.

This can be solved by setting the vendor string to, for example,
AuthenticAMD (as qemu does) so that Linux will create the relevant sysfs
files. Unfortunately, simply changing the string in cpuid.cc to
AuthenticAMD causes simulation slowdown and may not be desirable to all
users. This change creates a parameter, defaulting to M5 Simulator as it
currently is, which can be set in python configuration files to change
the vendor string. Example of how to configure this is:

for i in range(len(self.cpus)):
    for j in range(len(self.cpus[i].isa)):
        self.cpus[i].isa[j].vendor_string = "AuthenticAMD"

Change-Id: I8de26d5a145867fa23518718a799dd96b5b9bffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Instantiate SCMI in VExpress_GEM5 platforms

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34380
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: SCMI Implementation

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I8a60418c1edc79c3f403905618af3bc7989f114e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34379
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Implement Arm MHU (Message Handling Unit)

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I895eba1a3421746a602e6a4f88916da9054169a8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34378
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: System is expecting a kvm_vm param for KvmVM

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31217
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kvm, arm: Add parameter to force simulation of Gicv2

By setting simulate_gic to True it will be possible to prevent
the simulation from using the host interrupt controller

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I7c7df798e07bfaddbc2f1e7dd981b6aff621a9d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36795
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add doorbell interface class

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I0d264a74cbf8ca0f780314ad01fb0dd0765a0464
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34377
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Define a ParentMem object for DTB autogen

A memory willing to autogenerate child nodes can do that directly in
the generateDeviceTree method.  However sometimes portions of memory
(child nodes) are tagged for specific applications. Hardcoding the
child node in the parent memory class is not flexible, so we delegate
this to the application model, which is registering the generator
helper via the ParentMem interface

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I5fa5bac0decf5399dbaa3804569998dc5e6d7bc0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34376
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

dev: Add a new RegisterBank which helps handle device registers.

This change includes both the RegisterBank class and register classes,
and a unit test which exercises them.

Change-Id: I28ef0c0b9192ad786625ac83f096f69d8e5af00f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35856
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Delete the now unnecessary create methods.

Most create() methods are no longer necessary. This change deletes them,
and occasionally moves some code from them into the constructors they
call.

Change-Id: Icbab29ba280144b892f9b12fac9e29a0839477e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Move many of the generic files outside an NULL guard.

These files can be compiled successfully even if the ISA is the NULL
ISA.

Change-Id: I67133ea674f678f33b0aa1ef55af719f2869241d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34169
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Handle KVM SE page faults with workload events.

The event in KVM x86 SE mode plays double duty, triggering a system call
or a page fault depending on where it's called from (the system call
handler vs page fault handler).

This means we can eliminate the page fault gem5 op and the
pseudo_inst.hh switching header file.

This change touches a lot of things, but there wasn't really a good
place to split it up which still made sense and was consistent and
functional.

Change-Id: Ic414829917bcbd421893aa6c89d78273e4926b78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34165
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Make standard Params::create() optional.

The *vast* majority of SimObjects use the standard boilerplate version
of their Params::create() method which just returns new
ClassName(*this); Rather than force every class to define this method,
or annoy and frustrate users who forget and then get linker errors, this
change automates the default while leaving the possibility of defining a
custom create() method for non-default cases.

The situations this mechanism handles can be first broken down by
whether the SimObject class has a constructor of the normal form, ie one
that takes a const Params reference as its only parameter.

If no, then no default create() implementation is defined, and one
*must* be defined by the user.

If yes, then a default create() implementation is defined as a weak
symbol. If the user still wants to define their own create method for
some reason, perhaps to add debugging info, to keep track of instances
in c++, etc., then they can and it will override the weak symbol and
take precedence.

The way this is implemented is not straightforward. A set of classes are
defined which use SFINAE which either map in the real Params type or a
dummy based on whether the normal constructor exists in the SimObject
class. Then those classes are used to define *a* create method.
Depending on how the SFINAE works out, that will either be *the* create
method on the real Params struct, or a create method on a dummy class
set up to just absorb the definition and then go away. In either case the
create() method is a weak symbol, but in the dummy case it
doesn't/shouldn't matter.

Annoyingly the compiler insists that the weak symbol be visible. While
that makes total sense normally, we don't actually care what happens to
the weak symbol if it's attached to the dummy class. Unfortunately that
means we need to make the dummy class globally visible, although we put
it in a namespace to keep it from colliding with anything useful.

Change-Id: I3767a8dc8dc03665a72d5e8c294550d96466f741
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35942
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove the syscall gem5 op.

This is now handled by the workload "event" gem5 op.

Change-Id: Ibc195fde14a6174d1978bf280c349ca895e7fda3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34164
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,kvm: Use the new workload event to trigger KVM system calls.

While events are only used for SE mode for now, this moves to using the
common mechanism and gets rid of the need for the system call specific
pseudo inst.

Change-Id: I53468103d7f046b85cc25cbff94b12dbc946f4f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34163
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a new gem5 op for workload events.

This is a way to send a very generic poke to the workload so it can do
something. It's up to the workload to know what information to look for
to interpret an event, such as what PC it came from, what register
values are, or the context of the workload itself (is this SE mode? which
OS is running?).

Change-Id: Ifa4bdf3b5c5a934338c50600747d0b65f4b5eb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34162
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Implement an SE workload for Linux.

Change-Id: I78f6048cfe06be1b08d54dc7d24cb3518e97be0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34158
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Implement an SE workload for Linux.

Change-Id: Ieb7058007e56ce0c8d153c1853e4b92237e98ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34156
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,scons: De-indent the main x86 SConscript file.

Rather than put all the declaration of sources in the body of an "if", if
the "if" wouldn't happen, exit from the SConscript entirely. Then the
other parts of the SConscript can be totally unindented. Also wrap some
lines which were longer than 80 characters.

Change-Id: I113d649cdd051da02d5ab14a4547b26113d2f7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34161
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Separate system call tables into their own files.

These tables take up a lot of space and obscure what's going on in the
file around them. This change moves them into their own files (one for
32 bit and one for 64 bit). It also moves the x86 local definitions of
some system calls into their own file, and creates a SConscript file for
the linux subdirectory.

Change-Id: Ib0978005783b41789ea59695ad95b0336f6353eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34160
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Implement an SE workload for Linux and FreeBSD.

Change-Id: I3bac27ca8d5ed9fa11b519ea29b73c6d09260157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Re-add copyrights that were accidentally removed.

The partial contents of some files were moved into other files, but the
copyright wasn't moved over with them. This propogates the copyright.

Change-Id: I8612e88ffb7584b15924cf747f671ca3cdefbe55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36716
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a missing include to sim/syscall_abi.hh.

This must have been included indirectly in the past.

Change-Id: I8be3a11ca386e420f04d57e51a89c47e6a747e18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36616
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ibd78bef263d186889f4533583ff30f46a0a8643f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34981
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

tests: fix dezip of ubuntu images in long regr

needed to change output open from 'w' to 'wb'
to write binary format

Change-Id: Ia176d86a8ab8cc083ffc9508e051b667936eca2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36615
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch-sparc: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Remove support for Solaris SE mode.

In SPARC and SE mode, system calls are triggered by a trap exception
with the appropriate trap number, and then a handler within the Workload
(formerly the Process) object recognizes the trap number and triggers
the system call.

For Linux, this special handling happens in the Linux specific Workload,
and other types of traps are passed through to the base SPARC SE
Workload class. For Solaris however, no special handling is implemented.
That means that it's actually impossible for a Solaris SE mode program
to actually trigger a system call, and so while there is some code
written for Solaris SE mode, this feature does not actually work at all.

Also, while it's relatively easy to build binaries for Linux on various
architectures using, for instance, the crosstool-ng configs in util/,
there is no ready made option that I could find for building a SPARC
Solaris cross compiler which would run on x86 linux.

Given that the support that exists isn't actually hooked up properly,
SPARC is not one of the most popular ISAs within gem5, Solaris is not a
widely used operating system, we have (to my knowledge) no test binary
to run, and setting up a cross compiler would be non-trivial, it makes
the most sense to me to remove this support.

Change-Id: I896b5abc4bf337bd4e4c06c49de7111a3b2b784c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33996
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Implement an SE workload for Linux and Solaris.

I don't have a binary to test Solaris SE mode, but this *should* still
work.

Change-Id: Iaacc2ddd5193d7341bc65b9fdd5657c26d231cf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu: Use X86ISA instead of TheISA in src/gpu-compute.

These files are nominally not tied to the X86ISA, but in reality they
are because they reach into the GPU TLB, which is defined unchangeably in
the X86ISA namespaces, and uses data structures within it. Rather than try
to pretend that these structures are generic, we'll instead just use X86ISA
instead of TheISA. If this really does become generic in the future, a
base class with the ISA agnostic essentials defined in it can be used
instead, and the ISA specific TLBs can defined their own derived class
which has whatever else they need. Really the compute unit shouldn't be
communicating with the TLB using sender state since those are supposed
to be little notes for the sender to keep with a transaction, not for
communicating between entities across a port.

Change-Id: Ie6573396f6c77a9a02194f5f4595eefa45d6d66b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34174
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Implement an SE workload for Linux.

Change-Id: Ie242698b7f9e6ffffd4abdcbb483ee81d64802d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34157
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>

x86: Delegate process loading to the EmuLinux workload.

This is still triggered by the generic mechanism that tries out all
paths to go from an object file to a process. That's not entirely
necessary since the only loader that should be used when using the
X86ISA::EmuLinux workload is the one it provides, but the rest of gem5
isn't ready for that change yet.

This removes the last lingering reason to keep around the
arch/x86/linux/process.(hh|cc) files, so they have been deleted.

Change-Id: I425b95c9c730f31291790d63bc842e2c0092960d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33904
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I0759baec87b3682a057239a6b3b8f79fe3f5592c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix up for the new standardized create() methods.

Change-Id: I2e3610b5cad37b67d32907a2c2568b504d5ed113
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Implement FPC cache compressor

Implementation of Frequent Pattern Compression, proposed
by Alameldeen et al. in "Frequent Pattern Compression: A
Significance-Based Compression Scheme for L2 Caches".

Change-Id: I6dca8ca6b3043b561140bc681dbdbe9f7cef27d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36395
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Make (de)compression latencies params

Add 4 params to calculate compression and decompression latencies.
A pair of params informs how many chunks are parsed per cycle, and
the other pair informs how many extra cycles are needed after the
chunks are parsed to finish the (de)compression.

Change-Id: Ie67b0c298f06a08011f553789e3a9a1d89dd7c4f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36497
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add support for Proxy division

Allow proxies to use python3's division operations. The dividends
and divisors can be either a proxy or a constant.

Change-Id: I96b854355b8f593edfb1ea52a52548b855b05fc0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36496
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Undefine compression ratio of perfect compression

Commit c0d67b2263aab6a729368373d9cdef9883870241 assumes that the
cache contains a parameter for its compression ratio. This is not
the case upstream, so force the user to provide it instead.

Change-Id: Ic7b4878bede6b0a34e4adfe7e0aa65a0ee48d1f6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36495
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Fix an incorrect print statement in git pre-commit hook

Change-Id: I13d0a705b6cfab654635380e2adbf36243344a62
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36516
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix implementation of TLBI ALLEx instructions

The TLBIALL op in gem5 was designed after the AArch32 TLBIALL instruction.
and was reused by the TLBI ALLEL1, ALLE2, ALLE3 logic.

This is not correct for the following reasons:

- TLBI ALLEx invalidates regardless of the VMID
- TLBI ALLEx (AArch64) is "target regime" oriented, whereas TLBIALL
  (AArch32) is "current regime" oriented

TLBIALL has a different behaviour depending on the current exception
level: if issued at EL1 it will invalidate stage1 translations only; if
at EL2, it will invalidate stage2 translations as well.

TLBI ALLEx is more standard; every TLBI ALLE1 will invalidate stage1 and
stage2 translations. This is because the instruction is not executable
from the guest (EL1)

So for TLBIALL the condition for stage2 forwarding will be:

if (!isStage2 && isHyp) {

Whereas for TLBI ALLEx will be:

if (!isStage2 && target_el == EL1) {

Change-Id: I282f2cfaecbfc883e173770e5d2578b41055bb7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35241
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite the TLB flushing interface

We are now using an overloaded flush method which has
different TLBI ops as arguments.

This is simplifying the interface and it is allowing us to
encode some state in the TLBIOp which will then be passed
to the TLB. This is a step towards making the TLB a stateless
cache of translations

Change-Id: Ic4fbae72dc3cfe756047148b1cf5f144298c8b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reimplement TLB::flushAll

flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D flavours

This will be exploited by the incoming patchset

Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Don't check for Python 2

The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.

Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36535
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Test if binaries can embed the Python interpreter

Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.

Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36383
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replace enable_if<>::type with enable_if_t<>.

This new abreviated form was added for C++14. Now that we're using that
version of the standard, we can move over to it.

Change-Id: Ia291d2b1e73e503c37593b1e1c4c1b3011abc63b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36477
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix VExpressFastmodel interrupt configs

HDLcd interrupt params should receive ArmSPI class

Change-Id: I4a5dacdfe5803511d19f2ed789017fb3b1857bdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Move syscall handling for Linux into the EmuLinux workload.

Change-Id: I3fe1997e62491e9576b787660b7fae5ae99fb5c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33903
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Create an SEWorkload for x86 linux.

This doesn't do anything interesting yet, but soon it will take over
system call duties from the x86 linux processes.

Change-Id: Ic126fc80def0b458de51d3a9c96120c58e5a75ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33902
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,sim: Move BitUnion serialization support to bitunion.hh.

This keeps the BitUnion code centralized and out of the generic
serialization code.

Change-Id: I297638df4f8908096b7c439298fbaf03236f9011
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36283
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Move the serialization backend handlers to their own header.

This way other types which want to enable serialization can include just
these handlers and specialize them as necessary without bringing in all
the other dependencies of the serialization mechanism.

Change-Id: I7310e7741615e23ac0fc762e951bf5eac00aaa74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36281
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Refactor how serialization types are handled in the backend.

The parseParam and showParam functions partially worked using template
specialization, and partially worked using function overloading. The
template specialization could be resolved later once other functions
were added, but the regular function overloads could not. That meant
that it was practically impossible to add new definitions of those two
functions local to the types they worked with.

Also, because C++ does not allow partial specialization of template
functions, it would not be possible to truly use specialization to wire
in BitUnion types.

To fix these problems, these functions have been turned into structs
which wrap static functions. These can be partially specialized as
desired, making them compatible with BitUnions. Also, it's not possible
to overload structures like it is with functions, so only specialization
is considered, not overloading.

While making these changes, these functions (now structs) were also
reworked so that they share implementation more, and are generally
more streamlined.

Given the fact that the previous parseParam and showParam functions
could not actually be expanded beyond serialize.hh, and were not
actually called directly by any code outside of that file, they should
have never been considered part of the API.

Now that these structs actually *can* be specialized outside of this
file, they should be considered part of the interface.

Change-Id: Ic8e677b97fda8378ee1da1f3cf6001e02783fde3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36280
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Narrow the applicability of the default to_number.

That template only works for integral (except bool), floating point,
or enum types, so restrict it to those types. That makes it easier to
detect what types will work with that function.

Change-Id: Ib29a9a0ea75dd617e28bb6850d60be905f93182f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36279
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix API comments for optParamIn.

The top level comment was correct, but the parameter comments talked
about writing parameters instead of reading them. Also simplified the
wording of the return value comment.

Change-Id: I156aba5b69c281ee2f34297bf3f75fd0acfb2b6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36278
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Generalize the arrayParamOut and arrayParamIn functions.

These had been written specifically for the vector, list, set, and C
style array types. This change reworks them to share an implementation,
and to work with more general types. The arrayParamOut method requires
std::begin() and std::end() to accept that type, and the arrayParamIn
method requires either insert or push_back, or the type to be an array.

Also fix up a couple of files which accidentally depended on includes in
the serialize headers which are no longer necessary.

Change-Id: I6ec4fe3bb900603bbb4e35c4efa620c249942452
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36277
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: L1/L2 hit/miss tracking for MOESI_AMD_BASE/GPU_VIPER

L1 and L2 access tracking was not fully implemented.
This patch adds the missing tracking actions, and corrects
several errors for the ones that were there.

Change-Id: I69a59283274c08e94b6650ab5f586cbfe5432503
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33915
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: L3 hit/miss tracking to MOESI_AMD_BASE-dir

L3 access tracking added to the directory controller.

This commit adds L3 hit/miss tracking to the controller.
Hit/miss status is decided when the tag array of the
L3 Cache is checked for the first time for any given request.

Change-Id: Icac122f59509d79135265fb38b112d3f47419b6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33314
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Fix garnet network interface stats

Fixing a bug in garnet network interface where flit source delay is
computed using both tick and cycle.

Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36416
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Update my email address.

Change-Id: Ibbed316125274b742dbcda62f114855176b922e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36382
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use absolute path for VirtIO9PDiod default root

VirtIO9PDiod model requires an absolute path as its parameter. So we
should change the default root path to absolute path as well.

Change-Id: I68a2ae1115e84ed61055298b06b2d0b4bd6410b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36381
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix FastmodelCluster cpu initialization

We should create the thread and the interrupt controller of fastmodel by
calling the create function explicitly.

Change-Id: I269440e144e83fa0a31d8cdf285fed31642f4f73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36380
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix a few accidental transitive includes.

Some files depend on definitions from files that they weren't including
themselves. They were working accidentally by getting those definitions
transitively through other, unrelated headers.

Change-Id: I50c919a4eb6c4484d4ee6b7f4fe02f075132964d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36282
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Implement optParamIn using paramIn.

This means only paramIn needs to be specialized, and then optParamIn
will be as well for free. It also removes some duplicate implementation.

Change-Id: Id124a05d04e1c0897121d0e13dd46efe90e8eed0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36276
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Use getTlb in BaseMMU to reduce boilerplate

Change-Id: I22dcdf0769e854c252788d415d46da113cb8c60a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35735
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I8f09b0dc9844764fbe1a04b34dd963730c91f531
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34978
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove unused demapInstPage and demapDataPage

Change-Id: Iecc2ee8d91bfd3caf38e5f27e9689b7e0d488ed5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34977
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-kvm, arch-x86: Fix KVM on Intel platforms

This is the minimal set of changes from the patch that's been floating
around for a few years originally by Mike Upton.

See http://reviews.gem5.org/r/2613/ and
https://gem5-review.googlesource.com/c/public/gem5/+/7361

The change to the tssDesc is the minimal change to get KVM working on
Intel platforms. However, the other changes seem prudent to add.

Tested on both Intel (i7-7700) and AMD (EPYC 7451) platforms.

Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12278
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Adding a SRAM in VExpress_GEM5_V1

This is added in order to match the RS1 memory map

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I51e7aeafe1468a68fe7a3d78c7a6c405114df88f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34375
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Raise an exception when scons is run a Python2 environment

As gem5 has started to use Python2 incompatible features, compiling
gem5 in a Python2 environment results in an error.

This commit addresses this issue by raising an Exception when scons
is run in a Python2 environment, and adding a few pointers on how to
install Python3 and on how to use scons in a Python3 environment. The
solution works in a system where both Python2 and Python3 are
installed.

JIRA: https://gem5.atlassian.net/browse/GEM5-797

Change-Id: I98d4a39f586f39d9253ab2517b77e86c5ed19466
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36157
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Minor updates to CONTRIBUTING.md

This brings the file slightly more up to date

Change-Id: I1ed3300ec3c4980ed22c6a6fb950fa724897906b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36255
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Wrap __attribute__((aligned())) in a macro in compiler.hh.

This attribute is gcc specific (also implemented by clang for
compatibility), and so should be behind a level of abstraction to make
using different compilers easier.

Change-Id: I7495f011f617268dd7a589dc0bcf1b3b7f515046
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35976
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use compiler.hh macros when available.

Some places were hand coding __attribute__s when macros in compiler.hh
were available to do that job. Using the macros helps abstract away
compiler specific details and should be used when possible.

Change-Id: I94befebcfde2d673e874e9959588f69781bd9021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35975
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ArmPMU DTB generation

This has been implemented by following Linux documentation:

Documentation/devicetree/bindings/arm/pmu.txt

Change-Id: I22583eed3792d5828f9c260e952ec5e8cf9e118b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35476
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Use generateFdtProperty in the PioDevice

Change-Id: I2126bf84e0648fe76570f9645179f90bdf79eb41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35398
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Use generateFdtProperty in the GenericTimer

Change-Id: I4115d14ba65685627b51b0e5438fe5a3ed9328bc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35397
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Automate FdtProperty generation with ArmInterruptPin

Change-Id: I1963bd139d8abd8988d5ceedaf85c74279546078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35396
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, fastmodel: Rewrite Gic.interruptCells

The affinity number (aka PPI partition) is used differently
in GICv2 and GICv3. In GICv2 it is ORed to the triggering type
(3rd cell), whereas it is encoded in the 4th cell in GICv3

Change-Id: I36e45d4ec5fb39befa1a271b531dfed2d8e56c10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Define ArmInterruptType

This is a scoped enum meant to be used mainly in the python world
for DTB autogeneration. By making an ArmInterruptPin self aware of
its own type, we can use it in the C++ world when modelling devices.

For example if a device spec is enforcing a specific triggering behaviour,
its gem5 implementation can query the interrupt type and panic if its
expectations are not met. In this way we are sure what the Linux kernel
sees in the DTB is in sync with how the model really behaves

Change-Id: I66ae3cfbc7b1ed94804f1f882c12eb31f70840da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35395
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Make GPU_VIPER config python3 friendly

There is no xrange in python3. This will be required when eventually
20.2 is released.

Change-Id: I3a0da6353b70e6e17ce1f77d6177d48059e32487
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35855
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: python3 compatibility for apu_se

This patch changes xrange to range, as the former doesn't exist in
python3.

Change-Id: Ibe2c1fb073194e3e0713bb1718f2e323f7c4e397
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36159
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update GCN dockerfile for python3

This patch installs python3 in the GCN dockerfile, due to python3
being required starting in 20.2.

Python2 (python-yaml) is still required in order to compile rocBLAS

Change-Id: I1a6f1707e076e8ca499804119447a8d1f237ffd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36158
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,python: Flip logic on loopback listeners

People are bitten by allowing external connections to gem5 runs too often
(it happend to me again today). This change flips the logic so the
default is to only allow localhost connections.

Change-Id: If9233f5ca383721017b30b5837a26c5042d925fd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36175
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Rework how PCI BARs are set up in python and C++.

In python, the BARs had been configured using three arrays and a scalar
parameter. The arrays tracked the BAR value in the config, whether the
BAR was for a "legacy" IO range, and the size of the BAR, and the
scalar parameter was an offset for the "legacy" IO addresses to map
into the host physical address space. The nature of a BAR was implied
by its raw config space value, with each of the control bits (IO vs.
memory, 64 bit, reserved bits) encoded directly in the value.

Now, the BARs are represented by objects which have different types
depending on what type of BAR they are. There's one for IO, one for
memory, one for the upper 32 bits of a 64 bit BAR (so indices work
out), and one for legacy IO ranges. Each type has parameters which
are appropriate for it, and they're parameters are all grouped together
as a unit instead of being spread across all the previous values.
The legacy IO offset has been removed, since these addresses can be
offset like any other IO address. They can be represented naturally
in the config using their typical IO port numbers, and still be turned
into an address that gem5 will handle correctly in the back end.

Unfortunately, this exposes a problem in the config system where
a VectorParam can't be overwritten successfully one element at a time,
at least when dealing with SimObject classes. It might work with
actual SimObjects in a config, but I haven't tried it. If you were
to do that to, for instance, update the BARs for x86 so that they
used legacy IO ports for the IDE controller, it would complain that
you were trying to instantiate orphaned nodes. Replacing the whole
VectorParam with a new list of BAR objects seems to work, so that's
what's implemented in this change.

On the C++ side, BARs in the config space are treated as flat values
on reads, and are stored in the config structure associated with each
PCI device. On writes, the value is first passed to the BAR object,
and it has a chance to mask any bits which are fixed in hardware and
update its idea of what range it corresponds to in memory.

When sending AddrRanges up to the parent bus to set up routing, the
BARs generate each AddrRange if and only if their type has been
enabled in the config space command register. The BAR object which
represents the upper 32 bits of a 64 bit BAR does not claim to be
IO or memory, and so doesn't contribute a range. It communicates with
the BAR which represents the lower 32 bits, so that that BAR has the
whole base address.

Since the IO or memory BAR enable bits in the command register are now
handled by the PCI device base class, the IDE controller no longer has
to handle that manually. It does still need to keep track of whether
the bus master functionality has been enabled though, which it can
check when those registers are accessed.

There was already a mechanism for decoding addresses based on BARs
in the PCI device base class, but it was overly complicated and not
used consistently across devices. It's been consolidated, and used in
most places where it makes sense.

Finally, a few unnecessary values have been dropped from the base PCI
device's and IDE controller's checkpoint output. These were just local
copies of information already in the BARs, which in turn are already
stored along with the data in the device's config space.

Change-Id: I16d5f8cdf86d7a2d02a6b04d1f9e1b3eb1dd189d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35516
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,mem-ruby: Properly create/handle WriteCompletePkts

There is a flow of packets as so:
WriteResp -> WriteReq -> WriteCompleteResp

These packets share some variables, in particular senderState and a
status vector.

One issue was the WriteResp packet decremented the status vector, which
was used by the WriteCompleteResp packets to determine when to handle
the global memory response. This could lead to multiple
WriteCompleteResp packets attempting to handle the global memory
response.

Because of that, the WriteCompleteResp packets needed to handle the
status vector. this patch moves WriteCompleteResp packet handling back
into ComputeUnit::DataPort::processMemRespEvent from
ComputeUnit::DataPort::recvTimingResp. This helps remove some redundant
code.

This patch has the WriteResp packet return without doing any status
vector handling, and without deleting the senderState, which had
previously caused a segfault.

Another issue was WriteCompleteResp packets weren't being issued for
each active lane, as the coalesced request was being issued too early.
In order to fix that, we have to ensure every active lane puts their
request into their applicable coalesced request before issuing the
coalesced request. Because of that change, we change the issuing of
CoalescedRequests from GPUCoalescer::coalescePacket to
GPUCoalescer::completeIssue.

That change involves adding a new variable to store the
CoalescedRequests that are created in the calls to coalescePacket. This
variable is a map from instruction sequence number to coalesced
requests.

Additionally, the WriteCompleteResp packet was attempting to access
physical memory in hitCallback while not having any data, which
caused a crash. This can be resolved either by not allowing
WriteCompleteResp packets to access memory, or by copying the data
from the WriteReq packet. This patch denies WriteCompleteResp packets
memory access in hitCallback.

Finally, in VIPERCoalescer::writeCompleteCallback there was a map
that held the WriteComplete packets, but no packets were ever being
removed. This patch removes packets that match the address that was
passed in to the function.

Change-Id: I9a064a0def2bf6c513f5295596c56b1b652b0ca4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33656
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove dangling reference to bus port in devices.py

Change-Id: I3f7b65a9e6d4ae88acc474bb0e3a55f28c3cd09b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Clean up some #ifs in _format_string.

These were checking for gcc version 3, well below the minimum version we
support, and were hard wired to be enabled anyway. This change gets rid
of the check and the dead code on the hard wired off branch.

Also, this change cleans up the style in the surviving code and
simplifies it slightly.

Change-Id: I8df73a378f478413c111a4dea962450a37fb4092
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35977
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Standardize the way create() constructs SimObjects.

The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Add support for comma-separated inputs of testlib argparser

Currently, the --isa, --variant and --length options of testlib
do not support comma-separated inputs. This commit adds the
support for such an input for those options.

The argument parser now supports specifying the parameters multiple
times as well as specifying multiple options at a time.

JIRA: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-770

Change-Id: I3c276a9b9d9c6b0b802ecf8e7f1f9a3dfafe45d1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34198
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

cpu: Remove automatic overriding of numThreads in SE on O3.

On the O3 CPU, when the number of threads on the CPU (SMT) is too low to
hold all the old style CPU workload items, then it would increase the
number of threads to match. There are three problems with this.

1. This behavior was only implemented on O3.
2. It could silently hide a bug in the config where the number of
   workload items was accidentally too big.
3. It makes the DerivO3CPUParams struct tamper with itself in the
   create() method, which means not even config.ini will accurately
   reflect the actual config of the system.

Change-Id: I0aab70d4b98093f7f14156ca437e763f031049ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35937
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement Armv8.2-LPA

This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA

Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35956
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement Armv8.2-LVA

Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Use the new M5_WEAK macro to hide [[gnu::weak]].

Other compilers may need to support that macro in other ways.

Change-Id: If6ee05ce69c1bfd24108cf0785fac2d7bc259f0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35940
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Add an M5_WEAK macro to compiler.hh.

On gnu compatible systems, this will be implemented with the
[[gnu::weak]] attribute.

Change-Id: I1add373d648bbca24feab63420a9d87363646b6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35939
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>