spirv: Add vtn_fail and vtn_assert helpers

These helpers are much nicer than just using assert because they don't
kill your process.  Instead, it longjmps back to spirv_to_nir(), cleans
up all the temporary memory, and nicely returns NULL.  While crashing is
completely OK in the Vulkan world, it's not considered to be quite so
nice in GL.  This should help us to make SPIR-V parsing much more
robust.  The one downside here is that vtn_assert is not compiled out in
release builds like assert() is so it isn't free.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

util: Add a NORETURN macro

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

spirv: Do something useful with OpSource

We may as well log the source language and file name.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

spirv: Rework logging

This commit reworks the way that logging works in SPIR-V to provide
richer and more detailed logging infrastructure.  This commit contains
several improvements over the old mechanism:

 1) Log messages are now more detailed.  They contain the SPIR-V byte
    offset as well as source language information from OpSource and
    OpLine.

 2) There is now a logging callback mechanism so that errors can get
    propagated to the client through debug callbak extensions.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

spirv: Re-arrange vtn_builder initialization

This simply moves allocating the vtn_builder and initializing it to the
very beginning before we even parse the header.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

spirv: Parent the nir_shader to the builder while building

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>

freedreno: mark stencil buffer valid too in case of z32x24s8

The separate stencil buffer was not also getting marked as valid if
written by a draw/clear, resulting in gmem2mem getting skipped.  Move
this into fd_batch_resource_used() which also handles the separate
stencil case.

Also fix restore_buffers typo.

Fixes: 4ab6ab80365 freedreno: avoid mem2gmem for invalidated buffers
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: remove use of u_transfer

Freedreno doesn't treat buffers and images differently, so it's use was
kind of pointless.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add -Wno-packed-bitfield-compat for meson build

Otherwise huge amount of spam from instr-a2xx.h.. gcc has no way to know
that freedreno was never built with such an old gcc version to care
about the bugs in old gcc ;-)

Reported-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
[added commit message]
Signed-off-by: Rob Clark <robdclark@gmail.com>

glsl: don't run intrastage array validation when the interface type is not an array

We validate that the interface block array type's definition matches.
However, previously, the function could be called if an non-array
interface block has different type definitions -for example, when the
precision qualifier differs in a GLSL ES shader, we would create two
different types-, and it would return invalid as both definitions are
non-arrays.

We fix this by specifying that at least one definition should be an
array to call the validation.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl/es: precision qualifier doesn't need to match in UBOs

They might mismatch due to the two shaders using different GLSL
versions, and that's ok in desktop GL. In ES, precision qualifiers
don't need to match.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nvc0/ir: Properly lower 64-bit shifts when the shift value is >32

Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"
Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
set-up:

uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
uniform uint64_t uval 0x1400000085010203
uniform int shl 36
uniform int shr 36
uniform int64_t iexpected_shl 0x09ac901000000000
uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
uniform uint64_t uexpected_shl 0x5010203000000000
uniform uint64_t uexpected_shr 0x0000000001400000
draw rect ortho 12 0 4 4

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Match order of gl_LightSourceParameters elements.

spotExponent and spotCosCutoff were swapped in the
gl_builtin_uniform_element struct.
Now the order matches across gl_builtin_uniform_element,
glsl_struct_field and the spec.

Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: Fix gl_NormalScale.

GLSL shaders can access the normal scale factor with the built-in
gl_NormalScale.  Mesa's modelspace lighting optimization uses a different
normal scale factor than defined in the spec.  We have to take care not
to use this factor for gl_NormalScale.

Mesa already defines two seperate states: state.normalScale and
state.internal.normalScale.  The first is used by the glsl compiler
while the later is used by the fixed function T&L pipeline.  Previously
the only difference was some component swizzling.  With this commit
state.normalScale always uses the normal scale factor for eyespace
lighting.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/glsl_to_nir/radeonsi: enable gs support for nir backend

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add si_nir_load_input_gs() to the abi

V2: make use of driver_location and don't expose NIR to the ABI.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: move build_varying_gather_values() to ac_llvm_build.h and expose

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add basic nir -> llvm type helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: create si_llvm_load_input_gs()

This creates a common function that can be shared by the tgsi
and nir backends.

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: pass llvm type to lds_load()

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add llvm_type_is_64bit() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add nir support for gs epilogue

v2: add emit_gs_epilogue() helper function to reduce duplication.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add nir support for es epilogue

v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add nir support for ls epilogue

v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_nir: add gs support to st_nir_assign_var_locations()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_nir: use nir_lower_io_arrays_to_elements() to lower arrays

This pass is more fully featured, it supports geom and tess shaders.
It also supports interpolation intrinsics.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: allow builin arrays to be lowered

Galliums nir drivers expect this to be done.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: add array lowering function that assumes there are no indirects

The gallium glsl->nir pass currently lowers away all indirects on both inputs
and outputs. This fuction allows us to lower vs inputs and fs outputs and also
lower things one stage at a time as we don't need to worry about indirects
on the other side of the shaders interface.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: enable nir varying array splitting

Acked-by: Dave Airlie <airlied@redhat.com>

st/glsl_to_nir: enable NIR link time opts

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/nir: add support for packed inputs

Because NIR can create non vec4 variables when implementing component
packing we need to make sure not to reprocess the same slot again.

Also we can drop the fs_attr_idx counter and just use driver_location.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: move some calls out of st_glsl_to_nir_post_opts()

NIR component packing will be inserted between these calls and the
calling of st_glsl_to_nir_post_opts().

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: call some lowering passes earlier

This is required so that we can enbale NIR linking optimisations.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: add basic NIR opt loop helper

We need to be able to do these NIR opts in the state tracker
rather than the driver in order for the NIR linking opts to
be useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: make st_glsl_to_nir() static

Here we also move the extern C functions to the bottom of the file.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: split the st_glsl_to_nir() function in two

We want to be able to generate NIR then apply NIR optimisations.
Once the optimisations are done we can then apply the new post opt
function which assigns uniforms etc based on the optimised IR.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: create set_st_program() helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl: move nir linking loop to new function st_link_nir()

This will allow us to refactor linking and include some nir link
time optimisations.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nir: fix support for scalar arrays in nir_lower_io_types()

This was just recreating the same vector type we alreay had and
hitting an assert for scalars.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: add st_nir_assign_var_locations() helper

This avoids packed varyings being assigned different driver locations.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: enable nir component packing

SaschaWillems Vulkan demo tessellation:

~4000fps -> ~4600fps

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir: add varying component packing helpers

v2: update shader info input/output masks when pack components
v3: make sure interpolation loc matches, this is required for the
    radeonsi NIR backend.
v4: 33dca36f4f28 fixed nir_gather_info to update outputs_read
    correct, make sure we also adjust this correctly when
    packing components.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)

nir: add varying array splitting pass

V2:
 - fix matrix support, non-array matrices were being skipped in v1

v3:
 - handle lowering of tcs output loads correctly
 - correctly mark indirect locations for either in or out not both
   when processing a stage.
 - use nir_src_copy() when lowering stores.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

freedreno/ir3: relax barriers

Instructions with no barrier_class can move wrt. an EVERYTHING barrier.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: all mem instructions have WAR hazzard

It isn't just load instructions that have write-after-read hazzard.

Fixes stk gaussian blur compute shaders.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add debug option to force emulated indirect

Useful mostly for debugging indirect draw.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: also mark draw-indirect buffer as read

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: small cleanups

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: avoid unneccessary batch flush

In some cases we can end up trying to add a write dependency on ourself,
which shouldn't trigger a flush.

Avoids an extra couple flushes per from in stk.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: avoid mem2gmem for invalidated buffers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: deferred flush support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: rework fence tracking

ctx->last_fence isn't such a terribly clever idea, if batches can be
flushed out of order.  Instead, each batch now holds a fence, which is
created before the batch is flushed (useful for next patch), that later
gets populated after the batch is actually flushed.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: proper locking for iterating dependent batches

In transfer_map(), when we need to flush batches that read from a
resource, we should be holding screen->lock to guard against race
conditions.  Somehow deferred flush seems to make this existing
race more obvious.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: correct max_indicies for indirect draws

Signed-off-by: Rob Clark <robdclark@gmail.com>

spirv: Convert the supported_extensions struct to spirv_options

This is a bit more general and lets us pass additional options into the
spirv_to_nir pass beyond what capabilities we support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

spirv: Only emit functions which are actually used

Instead of emitting absolutely everything, just emit the few functions
that are actually referenced in some way by the entrypoint.  This should
save us quite a bit of time when handed large shader modules containing
many entrypoints.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

spirv: Drop the impl field from vtn_builder

We have a nir_builder and it has an impl field.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

i965: Serialize nir later in the linking process

Fixes MESA_GLSL=cache_fb with piglit
tests/spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.shader_test

Fixes: 0610a624a12 i965/link: Serialize program to nir after linking for shader cache
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

configure: avoid testing for negative compiler options

gcc seems to always accept unsupported negative compiler warning options:

echo "int i;" | gcc -c -xc -Wno-bob - # no error
echo "int i;" | gcc -c -xc -Walice -  # unsupported compiler option

Inverting the options fixes the tests.

V2: fix options in meson build

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Marc Dietrich <marvin24@gmx.de>

broadcom/vc4: Use a single-entry cached last_hindex value.

Since almost all BOs will be in one CL at a time, this cache will almost
always hit except for the first usage of the BO in each CL.

This didn't show up as statistically significant on the minetest trace
(n=340), but if I lop off the throttled lobe of the bimodal distribution,
it very clearly does (0.74731% +/- 0.162093%, n=269).

broadcom/vc4: Decompose single QUADs to a TRIANGLE_FAN.

No significant difference in the minetest replay, but it should reduce
overhead by not requiring that we write quad indices to index buffers that
we repeatedly re-upload (and making the draw packet smaller, as well).

Over the course of the series the actual game seems to be up by 1-2 fps.

broadcom/vc4: Use the new enum functionality of the XML to decode better.

broadcom/vc4: Skip emitting redundant VC4_PACKET_GEM_HANDLES.

Now that there's only one user of it, it's pretty obvious how to avoid
emitting redundant ones.  This should save a bunch of kernel validation
overhead.

No statistically sigificant difference on the minetest trace I was looking
at (n=169), but the maximum FPS is up by .3%

broadcom/vc4: Simplify the relocation handling for index buffers.

Originally there was CL code for handling various relocations back when I
had relocs for the TSDA/TA buffers.  Now that the kernel handles those
entirely on its own, I can inline that code into the one place using it.

broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.

We failed to take the start into account for how many vertices to draw in
this round, so we would end up decrementing count below 0, which as an
unsigned number meant we would loop until the CLs soon ran out of space.

When I wrote the code I was thinking about how to use the previously
emitted shader state (no index bias baked into the elements) by emitting
up to 65535 and then only re-emitting with bias for the second wround, but
that doesn't work if the start is over 65535.  Instead, just delay
emitting shader state until we get into the drawarrays GFXH-515 loop and
always bake the bias in when we're doing the workaround.

broadcom/vc4: Fix the scaling factor for the GFXH-515 workaround.

For triangle strips, we step by max_verts - 2.

meson: use dep_thread instead of dependency('threads') in freedreno

They are the same thing, but this is more consistent with the rest of
the project.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

meson: Add lmsensors support

v2: - Make -Dlmsensors=false work
    - Simplify auto and true cases

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

meson: Add support for gallium extra hud

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glx: Prepare driFetchDrawable for no-config contexts

When we look up the DRI drawable state we need to associate an fbconfig
with the drawable. With GLX_EXT_no_config_context we can no longer infer
that from the context and must instead query the server.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glx: Use __glXSendError instead of open-coding it

This also fixes a bug, the error path through MakeCurrent didn't
translate the error code by the extension's error base.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glx: Simplify some dummy vtable interactions

The dummy vtable has these slots as NULL already, no need to check for
the dummy context explicitly.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs/release-calendar: update and extend

v2: Missing td tag, add Andres + Juan for 17.2.8 and 17.3.3

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs/specs: annotate MESA_set_3dfx_mode as obsolete

Aimed to work with Glide, which hasn't been a thing in over 10 years.
There are no drivers that implement it, so annotate it as obsolete

v2: Move the extension to OLD/

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Reviewed-by: Adam Jackson <ajax@redhat.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

xlib: remove dummy GLX_MESA_set_3dfx_mode implementation

The implementation is a simple 'return EGL_FALSE'. Stop pretending and
simply remove it.

Note: the removal of XMesa API is fine, since there hasn't been any
users for it in years.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

docs/specs: annotate MESA_agp_offset as obsolete

No Mesa driver has implemented the extension in ages. Seemingly non Mesa
drivers don't implement it either.

As mentioned by Ian, the extension is effectively superseded by
ARB_vertex_buffer_object.

v2: Move the extension to OLD/

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Reviewed-by: Adam Jackson <ajax@redhat.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

xlib: remove empty GLX_MESA_agp_offset stubs

The extension was never implemented and seemingly never will.
The DRI based libGL dropped support for it over 10 years ago.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

xlib: remove empty GLX_NV_vertex_array_range stubs

The extension was never implemented and seemingly never will.
The DRI based libGL dropped support for it over 10 years ago.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/gen10: Change the order of PIPE_CONTROL and load register.

I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.

This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.

The bspec describes:

   "WA: Clear tdr register before send EOT in all non-PS shader kernels

   mov(8) tdr0:ud 0x0:ud {NoMask}"

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen10: emit 3DSTATE_MULTISAMPLE more often.

On CNL, we see multiple multisample failures on piglit tests. By
emitting this extra state, though not documented in the bspec, those
failures seem to go away.

This workaround could be removed if we ever find out a better solution,
but it should be good enough for now.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meson: install khrplatform header for EGL as well as GLES

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

meson: install dri internal header

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

i965: Disable regular fast-clears (CCS_D) on gen9+

This partially reverts commit 3e57e9494c2279580ad6a83ab8c065d01e7e634e
which caused a bunch of GPU hangs on several Source titles.  To date, we
have no clue why these hangs are actually happening.  This undoes the
final effect of 3e57e9494c227 and gets us back to not hanging.  Tested
with Team Fortress 2.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Fixes: 3e57e9494c2279580ad6a83ab8c065d01e7e634e
Cc: mesa-stable@lists.freedesktop.org

egl/x11: Remove unneeded free() on always null string

In this condition dri2_dpy->driver_name string always equals
NULL, so call to free() is useless

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium/hud: use #ifdef to test for macro existence

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: remove always-true BRAHMA_BUILD define

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glx/dri3: Remove unused deviceName variable

deviceName string is declared, assigned and freed but actually
never used in dri3_create_screen() function.

Fixes: 2d94601582e ("Add DRI3+Present loader")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

swr/scons: Fix intermittent build failure

gen_rasterizer*.cpp depends on gen_ar_eventhandler.hpp.
Account for new dependency.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

radv: only reset command buffers when the allocation fails

   "vkAllocateCommandBuffers can be used to create multiple command
    buffers. If the creation of any of those command buffers fails, the
    implementation must destroy all successfully created command buffer
    objects from this command, set all entries of the pCommandBuffers
    array to NULL and return the error."

This has been suggested by gabriel@system.is.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not dump meta shaders with RADV_DEBUG=shaders

It's really annoying and this pollutes the output especially
when a bunch of non-meta shaders are compiled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

r600: add ARB_shader_storage_buffer_object support (v3)

This just builds on the image support. Evergreen only has ssbo
for fragment and compute no other stages.

v2: handle images and ssbo in the same shader properly (Ilia)
v3: fix RESQ on buffers,
    fix missing atom emit
    fix first element offset
    use R32 format
    write separate buffer rat store path.
(from running deqp gles3.1 tests)

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600/cayman: looks like cmpxchg moved to Z

On cayman it appears the cmp component is now in Z.

Fixes:
arb_shader_image_load_store-dead-fragments on cayman.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600/shader: fix 64->32 conversions

These didn't handle the TGSI at all properly, this fixes
them to use the common path for 64->32 then adds the 32->int
on at the end.

Fixes:
generated_tests/spec/arb_gpu_shader_fp64/execution/conversion/*

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: do not allocate CMASK or DCC for small surfaces

The idea is ported from RadeonSI, but using 512x512 instead of
256x256 seems slightly better. This improves dota2 performance
by +2%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

radv: do not set DISABLE_LSB_CEIL on GFX9

The state no longer exists on GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove set but unnecessary radv_color_buffer_info::micro_tile_mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not store gfx9_epitch in radv_color_buffer_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

meson: fix glxext.h install

Another typo, the glext.h header was being install instead.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>