Joseph Myers [Tue, 17 Mar 2020 00:34:39 +0000 (00:34 +0000)]
Update gcc sv.po.
* sv.po: Update.
GCC Administrator [Tue, 17 Mar 2020 00:16:15 +0000 (00:16 +0000)]
Daily bump.
Iain Buclaw [Mon, 16 Mar 2020 22:53:20 +0000 (23:53 +0100)]
d: Fix assignment to anonymous union member corrupts sibling members in struct
gcc/d/ChangeLog:
PR d/92309
* types.cc (fixup_anonymous_offset): Don't set DECL_FIELD_OFFSET on
anonymous fields.
gcc/testsuite/ChangeLog:
PR d/92309
* gdc.dg/pr92309.d: New test.
Jonathan Wakely [Mon, 16 Mar 2020 22:53:42 +0000 (22:53 +0000)]
libstdc++: Add default constructor to net::service_already_exists (PR 94199)
The service_already_exists exception type specified in the TS doesn't
have any constructors defined. Since its base class isn't default
constructible, that means has no usable constructors. This may be a
defect in the TS.
This patch fixes it by adding a default constructor, but making it
private. The make_service function is declared as a friend to be able to
call that private constructor.
PR libstdc++/94199
* include/experimental/executor (service_already_exists): Add default
constructor. Declare make_service to be a friend.
* testsuite/experimental/net/execution_context/make_service.cc: New
test.
Iain Buclaw [Mon, 16 Mar 2020 22:04:49 +0000 (23:04 +0100)]
d: Fix multiple definition error when using mixins and interfaces.
gcc/d/ChangeLog:
PR d/92216
* decl.cc (make_thunk): Don't set TREE_PUBLIC on thunks if the target
function is external to the current compilation.
gcc/testsuite/ChangeLog:
PR d/92216
* gdc.dg/imports/pr92216.d: New.
* gdc.dg/pr92216.d: New test.
Jakub Jelinek [Mon, 16 Mar 2020 21:58:41 +0000 (22:58 +0100)]
c: Handle MEM_REF in c_fully_fold* [PR94179]
The recent match.pd changes can generate a MEM_REF which can be seen by the
C FE folding routines. Unlike the C++ FE, they weren't expected in the C FE
yet. MEM_REF should be handled like INDIRECT_REF, except that it has two
operands rather than just one and that we should preserve the type of the
second operand. Given that it already has to be an INTEGER_CST with pointer
type, I think we are fine, the recursive call should return the INTEGER_CST
unmodified and STRIP_TYPE_NOPS will not strip anything.
2020-03-16 Jakub Jelinek <jakub@redhat.com>
PR c/94179
* c-fold.c (c_fully_fold_internal): Handle MEM_REF.
* gcc.c-torture/compile/pr94179.c: New test.
Vladimir N. Makarov [Mon, 16 Mar 2020 20:42:19 +0000 (16:42 -0400)]
Fix PR94185: Do not reuse insn alternative after changing memory subreg.
2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
PR target/94185
* lra-spills.c (remove_pseudos): Do not reuse insn alternative
after changing memory subreg.
2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
PR target/94185
* g++.target/i386/pr94185.C: New test.
Richard Sandiford [Thu, 12 Mar 2020 11:54:27 +0000 (11:54 +0000)]
[testsuite] Avoid duplicate test names in sizeless tests
Jeff pointed out that using:
N: ... /* { dg-error {...} } */
N+1: /* { dg-error {...} "" { target *-*-* } .-1 } */
led to two identical test names for line N. Fixed by adding
a proper test name instead of "".
2020-03-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/testsuite/
* gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Add a test
name to .-1 dg-error tests.
* gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise.
Srinath Parvathaneni [Mon, 16 Mar 2020 17:33:03 +0000 (17:33 +0000)]
[ARM][GCC][3/x]: MVE ACLE intrinsics framework patch.
This patch is part of MVE ACLE intrinsics framework.
The patch supports the use of emulation for the single-precision arithmetic
operations for MVE. This changes are to support the MVE ACLE intrinsics which
operates on vector floating point arithmetic operations.
Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest
2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
emulator calls for dobule precision arithmetic operations for MVE.
2020-03-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/mve_libcall1.c: New test.
* gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise.
Srinath Parvathaneni [Mon, 16 Mar 2020 17:22:39 +0000 (17:22 +0000)]
[ARM][GCC][2/x]: MVE ACLE intrinsics framework patch.
This patch is part of MVE ACLE intrinsics framework.
This patches add support to update (read/write) the APSR (Application Program Status Register)
register and FPSCR (Floating-point Status and Control Register) register for MVE.
This patch also enables thumb2 mov RTL patterns for MVE.
A new feature bit vfp_base is added. This bit is enabled for all VFP, MVE and MVE with floating point
extensions. This bit is used to enable the macro TARGET_VFP_BASE. For all the VFP instructions, RTL patterns,
status and control registers are guarded by TARGET_HAVE_FLOAT. But this patch modifies that and the
common instructions, RTL patterns, status and control registers bewteen MVE and VFP are guarded by
TARGET_VFP_BASE macro.
The RTL pattern set_fpscr and get_fpscr are updated to use VFPCC_REGNUM because few MVE intrinsics
set/get carry bit of FPSCR register.
Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest
2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
feature bit is on and -mfpu=auto is passed as compiler option, do not
generate error on not finding any matching fpu. Because in this case
fpu is not required.
* config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
enabled for MVE and also for all VFP extensions.
(VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
is enabled.
(MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
(MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
along with feature bits mve_float.
(mve): Modify add options in armv8.1-m.main arch for MVE.
(mve.fp): Modify add options in armv8.1-m.main arch for MVE with
floating point.
* config/arm/arm.c (use_return_insn): Replace the
check with TARGET_VFP_BASE.
(thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
TARGET_VFP_BASE.
(arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
well.
(arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
as well.
(arm_compute_frame_layout): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
in MVE as well.
(arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
with equivalent macro TARGET_VFP_BASE.
(arm_expand_epilogue_apcs_frame): Likewise.
(arm_expand_epilogue): Likewise.
(arm_conditional_register_usage): Likewise.
(arm_declare_function_name): Add check to skip printing .fpu directive
in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
"softvfp".
* config/arm/arm.h (TARGET_VFP_BASE): Define.
* config/arm/arm.md (arch): Add "mve" to arch.
(eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
(vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
|| TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
* config/arm/constraints.md (Uf): Define to allow modification to FPCCR
in MVE.
* config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
to not allow for MVE.
* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
enum.
(VUNSPEC_GET_FPSCR): Define.
* config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
instructions which move to general-purpose Register from Floating-point
Special register and vice-versa.
(thumb2_movhi_fp16): Likewise.
(thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
with MCR and MRC instructions which set and get Floating-point Status
and Control Register (FPSCR).
(movdi_vfp): Modify pattern to enable Single-precision scalar float move
in MVE.
(thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
float move patterns in MVE.
(thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
(thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
(push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
TARGET_VFP_BASE check.
(set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
register.
(get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
register.
2020-03-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test.
* gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise.
Srinath Parvathaneni [Mon, 16 Mar 2020 17:06:29 +0000 (17:06 +0000)]
[ARM][GCC][1/x]: MVE ACLE intrinsics framework patch.
This patch creates the required framework for MVE ACLE intrinsics.
The following changes are done in this patch to support MVE ACLE intrinsics.
Header file arm_mve.h is added to source code, which contains the definitions of MVE ACLE intrinsics
and different data types used in MVE. Machine description file mve.md is also added which contains the
RTL patterns defined for MVE.
A new reigster "p0" is added which is used in by MVE predicated patterns. A new register class "VPR_REG"
is added and its contents are defined in REG_CLASS_CONTENTS.
The vec-common.md file is modified to support the standard move patterns. The prefix of neon functions
which are also used by MVE is changed from "neon_" to "simd_".
eg: neon_immediate_valid_for_move changed to simd_immediate_valid_for_move.
In the patch standard patterns mve_move, mve_store and move_load for MVE are added and neon.md and vfp.md
files are modified to support this common patterns.
Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config.gcc (arm_mve.h): Include mve intrinsics header file.
* config/arm/aout.h (p0): Add new register name for MVE predicated
cases.
* config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
common to Neon and MVE.
(ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
(arm_init_simd_builtin_types): Disable poly types for MVE.
(arm_init_neon_builtins): Move a check to arm_init_builtins function.
(arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
ARM_BUILTIN_NEON_LANE_CHECK.
(mve_dereference_pointer): Add function.
(arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
enabled.
(arm_expand_neon_builtin): Moved to arm_expand_builtin function.
(arm_expand_builtin): Moved from arm_expand_neon_builtin function.
* config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
with floating point enabled.
* config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
simd_immediate_valid_for_move.
(simd_immediate_valid_for_move): Renamed from
neon_immediate_valid_for_move function.
* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
error if vfpv2 feature bit is disabled and mve feature bit is also
disabled for HARD_FLOAT_ABI.
(use_return_insn): Check to not push VFP regs for MVE.
(aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
as Neon.
(aapcs_vfp_allocate_return_reg): Likewise.
(thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
address operand for MVE.
(arm_rtx_costs_internal): MVE check to determine cost of rtx.
(neon_valid_immediate): Rename to simd_valid_immediate.
(simd_valid_immediate): Rename from neon_valid_immediate.
(simd_valid_immediate): MVE check on size of vector is 128 bits.
(neon_immediate_valid_for_move): Rename to
simd_immediate_valid_for_move.
(simd_immediate_valid_for_move): Rename from
neon_immediate_valid_for_move.
(neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
function.
(neon_make_constant): Modify call to neon_valid_immediate function.
(neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
for MVE.
(output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
(arm_compute_frame_layout): Calculate space for saved VFP registers for
MVE.
(arm_save_coproc_regs): Save coproc registers for MVE.
(arm_print_operand): Add case 'E' to print memory operands for MVE.
(arm_print_operand_address): Check to print register number for MVE.
(arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
(arm_modes_tieable_p): Check to allow structure mode for MVE.
(arm_regno_class): Add VPR_REGNUM check.
(arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
for APCS frame.
(arm_expand_epilogue): MVE check for enabling pop instructions in
epilogue.
(arm_print_asm_arch_directives): Modify function to disable print of
.arch_extension "mve" and "fp" for cases where MVE is enabled with
"SOFT FLOAT ABI".
(arm_vector_mode_supported_p): Check for modes available in MVE interger
and MVE floating point.
(arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
pointer support.
(arm_conditional_register_usage): Enable usage of conditional regsiter
for MVE.
(fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
(arm_declare_function_name): Modify function to disable print of
.arch_extension "mve" and "fp" for cases where MVE is enabled with
"SOFT FLOAT ABI".
* config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
when target general registers are required.
(TARGET_HAVE_MVE_FLOAT): Likewise.
(FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
for MVE.
(CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
which indicate this is not available for across function calls.
(FIRST_PSEUDO_REGISTER): Modify.
(VALID_MVE_MODE): Define valid MVE mode.
(VALID_MVE_SI_MODE): Define valid MVE SI mode.
(VALID_MVE_SF_MODE): Define valid MVE SF mode.
(VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
(VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
for MVE.
(IS_VPR_REGNUM): Macro to check for VPR_REG register.
(REG_ALLOC_ORDER): Add VPR_REGNUM entry.
(enum reg_class): Add VPR_REG entry.
(REG_CLASS_NAMES): Add VPR_REG entry.
* config/arm/arm.md (VPR_REGNUM): Define.
(conds): Check is_mve_type attrbiute to differentiate "conditional" and
"unconditional" instructions.
(arm_movsf_soft_insn): Modify RTL to not allow for MVE.
(movdf_soft_insn): Modify RTL to not allow for MVE.
(vfp_pop_multiple_with_writeback): Enable for MVE.
(include "mve.md"): Include mve.md file.
* config/arm/arm_mve.h: Add MVE intrinsics head file.
* config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
for vector predicated operands.
* config/arm/iterators.md (VNIM1): Define.
(VNINOTM1): Define.
(VHFBF_split): Define
* config/arm/mve.md: New file.
(mve_mov<mode>): Define RTL for move, store and load in MVE.
(mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
second operand.
* config/arm/neon.md (neon_immediate_valid_for_move): Rename with
simd_immediate_valid_for_move.
(neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
is common to MVE and NEON to vec-common.md file.
(vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
* config/arm/predicates.md (vpr_register_operand): Define.
* config/arm/t-arm: Add mve.md file.
* config/arm/types.md (mve_move): Add MVE instructions mve_move to
attribute "type".
(mve_store): Add MVE instructions mve_store to attribute "type".
(mve_load): Add MVE instructions mve_load to attribute "type".
(is_mve_type): Define attribute.
* config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
standard move patterns in MVE along with NEON and IWMMXT with mode
iterator VNIM1.
(mov<mode>): Modify RTL expand to support standard move patterns in NEON
and IWMMXT with mode iterator V8HF.
(movv8hf): Define RTL expand to support standard "movv8hf" pattern in
NEON and MVE.
* config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
simd_immediate_valid_for_move.
2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
* gcc.target/arm/mve/mve.exp: New file.
* lib/target-supports.exp
(check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check
armv8.1-m.main+mve.fp and returning corresponding options.
(check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call
check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of
MVE with floating point on the current target.
(add_options_for_arm_v8_1m_mve_fp): Proc to call
check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding
compiler options for MVE with floating point.
(check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and
return hard float-abi on success.
Iain Buclaw [Mon, 16 Mar 2020 16:00:07 +0000 (17:00 +0100)]
libphobos: Reset libtool_VERSION to 1:0:0
libphobos/ChangeLog:
2020-03-16 Iain Buclaw <ibuclaw@gdcproject.org>
PR d/92792
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.ac (libtool_VERSION): Reset to 1:0:0.
* libdruntime/Makefile.in: Regenerate.
Aaron Sawdey [Mon, 16 Mar 2020 14:29:05 +0000 (09:29 -0500)]
Fix ChangeLog formatting from my commit last friday.
Uros Bizjak [Mon, 16 Mar 2020 13:38:06 +0000 (14:38 +0100)]
x32 does not support MS ABI, skip testcases that require it.
* testsuite/20_util/bind/91371.cc: Skip for x32.
* testsuite/20_util/is_function/91371.cc: Ditto.
* testsuite/20_util/is_member_function_pointer/91371.cc: Ditto.
* testsuite/20_util/is_object/91371.cc: Ditto.
H.J. Lu [Mon, 16 Mar 2020 10:48:55 +0000 (03:48 -0700)]
i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV
There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.
Remove ext_sse_reg_operand since it is no longer needed.
gcc/
PR target/89229
* config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
check.
* config/i386/predicates.md (ext_sse_reg_operand): Removed.
gcc/testsuite/
PR target/89229
* gcc.target/i386/pr89229-7a.c: New test.
* gcc.target/i386/pr89229-7b.c: Likewise.
* gcc.target/i386/pr89229-7c.c: Likewise.
Iain Buclaw [Mon, 16 Mar 2020 08:48:54 +0000 (09:48 +0100)]
d/dmd: Merge upstream dmd
b061bd744
Fixes an ICE in the parser, and deprecates a previously allowed style of
syntax that deviated from GNU-style extended asm.
Reviewed-on: https://github.com/dlang/dmd/pull/10916
gcc/testsuite/ChangeLog:
2020-03-16 Iain Buclaw <ibuclaw@gdcproject.org>
* gdc.dg/asm1.d: Add new test for ICE in asm parser.
* gdc.dg/asm5.d: New test.
Iain Buclaw [Sun, 15 Mar 2020 12:59:14 +0000 (13:59 +0100)]
libphobos: Merge upstream druntime
6c45dd3a, phobos
68cc18adb.
Surrounds the gcc-style asm operands with parentheses, as the old style
is now deprecated.
Reviewed-on: https://github.com/dlang/druntime/pull/2986
Jakub Jelinek [Mon, 16 Mar 2020 08:03:59 +0000 (09:03 +0100)]
tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167]
The following testcase fails with -fcompare-debug. The problem is that
bar is marked as address_taken only with -g and not without.
I've tracked it down to insert_init_stmt calling gimple_regimplify_operands
even on DEBUG_STMTs. That function will just insert normal stmts before
the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant.
While DCE will turn those statements into debug temporaries, it can cause
differences in SSA_NAMEs and more importantly, the ipa references are
generated from those before the DCE happens.
On the testcase, the DEBUG_STMT value is (int)bar.
We could generate DEBUG_STMTs with debug temporaries instead, but I fail to
see the reason to do that, DEBUG_STMTs allow other expressions and all we
want to ensure is that the expressions aren't too large (arbitrarily
complex), but during inlining/function versioning I don't see why something
would queue a DEBUG_STMT with arbitrarily complex expressions in there.
2020-03-16 Jakub Jelinek <jakub@redhat.com>
PR debug/94167
* tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
DEBUG_STMTs.
* gcc.dg/pr94167.c: New test.
Jakub Jelinek [Mon, 16 Mar 2020 08:02:21 +0000 (09:02 +0100)]
tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167]
The following testcase fails with -fcompare-debug. The problem is that
bar is marked as address_taken only with -g and not without.
I've tracked it down to insert_init_stmt calling gimple_regimplify_operands
even on DEBUG_STMTs. That function will just insert normal stmts before
the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant.
While DCE will turn those statements into debug temporaries, it can cause
differences in SSA_NAMEs and more importantly, the ipa references are
generated from those before the DCE happens.
On the testcase, the DEBUG_STMT value is (int)bar.
We could generate DEBUG_STMTs with debug temporaries instead, but I fail to
see the reason to do that, DEBUG_STMTs allow other expressions and all we
want to ensure is that the expressions aren't too large (arbitrarily
complex), but during inlining/function versioning I don't see why something
would queue a DEBUG_STMT with arbitrarily complex expressions in there.
2020-03-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94166
* tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
as secondary comparison key.
* gcc.dg/pr94166.c: New test.
Bin Cheng [Mon, 16 Mar 2020 03:09:14 +0000 (11:09 +0800)]
Update post order number for merged SCC.
Function loop_distribution::break_alias_scc_partitions needs to compute
SCC with runtime alias edges skipped. As a result, partitions could be
re-assigned larger post order number than SCC's precedent partition and
distributed before the precedent one. This fixes the issue by updating
the merged partition to the minimal post order in SCC.
gcc/
PR tree-optimization/94125
* tree-loop-distribution.c
(loop_distribution::break_alias_scc_partitions): Update post order
number for merged scc.
gcc/testsuite/
PR tree-optimization/94125
* gcc.dg/tree-ssa/pr94125.c: New test.
GCC Administrator [Mon, 16 Mar 2020 00:16:17 +0000 (00:16 +0000)]
Daily bump.
H.J. Lu [Sun, 15 Mar 2020 17:21:08 +0000 (10:21 -0700)]
i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV
There is no need to set mode attribute to V16SFmode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.
gcc/
PR target/89229
* config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
MODE_SF.
* config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
and ext_sse_reg_operand check.
gcc/testsuite/
PR target/89229
* gcc.target/i386/pr89229-6a.c: New test.
* gcc.target/i386/pr89229-6b.c: Likewise.
* gcc.target/i386/pr89229-6c.c: Likewise.
Iain Sandoe [Sun, 15 Mar 2020 14:22:18 +0000 (14:22 +0000)]
coroutines: Fix indentation (NFC).
Whitespace-only change.
gcc/cp/ChangeLog:
2020-03-15 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (co_await_expander): Fix indentation.
Lewis Hyatt [Sun, 15 Mar 2020 12:58:30 +0000 (08:58 -0400)]
driver: Fix redundant descriptions in options
Addresses issues where the two-column format of options descriptions was
used, but the columns were separated by spaces rather than a single tab,
causing the help output to be more verbose than intended.
gcc/ChangeLog:
2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
* common.opt: Avoid redundancy in the help text.
* config/arc/arc.opt: Likewise.
* config/cr16/cr16.opt: Likewise.
gcc/c-family/ChangeLog:
2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
* c.opt: Avoid redundancy in the help text.
gcc/fortran/ChangeLog:
2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
* lang.opt: Avoid redundancy in the help text.
gcc/testsuite/ChangeLog:
2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
* gcc.misc-tests/help.exp: Adapt to new output for
-Walloc-size-larger-than= option.
Jakub Jelinek [Sun, 15 Mar 2020 00:27:40 +0000 (01:27 +0100)]
tree-nested: Fix handling of *reduction clauses with C array sections [PR93566]
tree-nested.c didn't handle C array sections in {,task_,in_}reduction clauses.
2020-03-14 Jakub Jelinek <jakub@redhat.com>
PR middle-end/93566
* tree-nested.c (convert_nonlocal_omp_clauses,
convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
with C/C++ array sections.
* testsuite/libgomp.c/pr93566.c: New test.
GCC Administrator [Sun, 15 Mar 2020 00:16:14 +0000 (00:16 +0000)]
Daily bump.
H.J. Lu [Sat, 14 Mar 2020 23:06:55 +0000 (16:06 -0700)]
i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV
There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.
gcc/
PR target/89229
* config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
check.
gcc/testsuite/
PR target/89229
* gcc.target/i386/pr89229-5a.c: New test.
* gcc.target/i386/pr89229-5b.c: Likewise.
* gcc.target/i386/pr89229-5c.c: Likewise.
Jason Merrill [Sat, 14 Mar 2020 21:10:39 +0000 (17:10 -0400)]
c++: Fix ICE-after-error on partial spec [92068]
Here the template arguments for the partial specialization are valid
arguments for the template, but not for a partial specialization, because
'd' can never be deduced to anything other than an empty pack.
gcc/cp/ChangeLog
2020-03-14 Jason Merrill <jason@redhat.com>
PR c++/92068
* pt.c (process_partial_specialization): Error rather than crash on
extra pack expansion.
Jason Merrill [Sat, 14 Mar 2020 21:10:39 +0000 (17:10 -0400)]
c++: Find parameter pack in typedef in lambda [92909].
find_parameter_packs_r doesn't look through typedefs, which is normally
correct, but that means we need to handle their declarations specially.
gcc/cp/ChangeLog
2020-03-14 Jason Merrill <jason@redhat.com>
PR c++/92909
* pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk
DECL_ORIGINAL_TYPE of a typedef.
Jason Merrill [Sat, 14 Mar 2020 21:10:39 +0000 (17:10 -0400)]
c++: Fix CTAD with multiple-arg ctor template [93248].
When cp_unevaluated_operand is set, tsubst_decl thinks that if it sees a
PARM_DECL that isn't already in local_specializations, we're in a decltype
in a trailing return type or some such, and so we only want a substitution
for a single PARM_DECL. In this case, we want the whole chain, so make sure
cp_unevaluated_operand is cleared.
gcc/cp/ChangeLog
2020-03-14 Jason Merrill <jason@redhat.com>
PR c++/93248
* pt.c (build_deduction_guide): Clear cp_unevaluated_operand for
substituting DECL_ARGUMENTS.
Iain Buclaw [Sat, 14 Mar 2020 18:30:24 +0000 (19:30 +0100)]
libphobos: Merge upstream druntime
7915b6a3
Includes port fixes for Musl on ARM, AArch64, and SystemZ targets.
Reviewed-on: https://github.com/dlang/druntime/pull/2751
https://github.com/dlang/druntime/pull/2843
https://github.com/dlang/druntime/pull/2844
https://github.com/dlang/druntime/pull/2898
Segher Boessenkool [Mon, 17 Feb 2020 12:13:21 +0000 (12:13 +0000)]
rs6000/test: Fix selector in fold-vec-mule-misc.c
Run tests should use vmx_hw, not just powerpc_altivec_ok.
gcc/testsuite/
PR target/94176
* gcc.target/powerpc/fold-vec-mule-misc.c: Use vmx_hw selector.
Jakub Jelinek [Sat, 14 Mar 2020 07:15:08 +0000 (08:15 +0100)]
Fix doubled indefinite articles, mostly in comments.
2020-03-14 Jakub Jelinek <jakub@redhat.com>
* gimple-fold.c (gimple_fold_builtin_strncpy): Change
"a an" to "an" in a comment.
* hsa-common.h (is_a_helper): Likewise.
* tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
* config/arc/arc.c (arc600_corereg_hazard): Likewise.
* config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
* logic.cc (formula::formula): Change "a an" to "an" in a comment.
* parser.c (cp_debug_parser): Change "a an" to "an" in a string
literal.
GCC Administrator [Sat, 14 Mar 2020 00:16:22 +0000 (00:16 +0000)]
Daily bump.
Aaron Sawdey [Fri, 13 Mar 2020 23:14:22 +0000 (18:14 -0500)]
Fix UBSAN error, shifting 64 bit value by 64.
2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/92379
* config/rs6000/rs6000.c (num_insns_constant_multi) Don't shift a
64-bit value by 64 bits (UB).
David Malcolm [Tue, 10 Mar 2020 23:03:37 +0000 (19:03 -0400)]
analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105]
PR analyzer/94099 and PR analyzer/94105 both report ICEs relating to
calling region_model::get_lvalue on a NOP_EXPR.
PR analyzer/94099's ICE happens when generating a checker_path when
encountering an unhandled tree code (NOP_EXPR) in get_lvalue with a
NULL context (from for_each_state_change).
PR analyzer/94105 ICE happens when handling an ARRAY_REF where the
first operand is a NOP_EXPR: the unhandled tree code gives us
a symbolic_region, but the case for ARRAY_REF assumes we have an
array_region.
This patch fixes the ICEs by handling NOP_EXPR within
region_model::get_lvalue, and bulletproofs both of the above sources
of failure.
gcc/analyzer/ChangeLog:
PR analyzer/94099
PR analyzer/94105
* diagnostic-manager.cc (for_each_state_change): Bulletproof
against errors in get_rvalue by passing a
tentative_region_model_context and rejecting if there's an error.
* region-model.cc (region_model::get_lvalue_1): When handling
ARRAY_REF, handle results of error-handling. Handle NOP_EXPR.
gcc/testsuite/ChangeLog:
PR analyzer/94099
PR analyzer/94105
* gcc.dg/analyzer/pr94099.c: New test.
* gcc.dg/analyzer/pr94105.c: New test.
Iain Buclaw [Fri, 13 Mar 2020 20:03:02 +0000 (21:03 +0100)]
d/dmd: Merge upstream dmd
e9420cfbf
1. Implement DIP 1010 - (Static foreach)
Support for 'static foreach' has been added. 'static foreach' is a conditional
compilation construct that is to 'foreach' what 'static if' is to 'if'. It is
a convenient way to generate declarations and statements by iteration.
import std.conv: to;
static foreach(i; 0 .. 10)
{
// a 'static foreach' body does not introduce a nested scope
// (similar to 'static if').
// The following mixin declaration is at module scope:
// declares 10 variables x0, x1, ..., x9
mixin('enum x' ~ to!string(i) ~ ' = i;');
}
import std.range: iota;
// all aggregate types that can be iterated with a standard 'foreach'
// loop are also supported by static foreach:
static foreach(i; iota(10))
{
// we access the declarations generated in the first 'static foreach'
pragma(msg, "x", i, ": ", mixin(`x` ~ to!string(i)));
static assert(mixin(`x` ~ to!string(i)) == i);
}
void main()
{
import std.conv: text;
import std.typecons: tuple;
import std.algorithm: map;
import std.stdio: writeln;
// 'static foreach' has both declaration and statement forms
// (similar to 'static if').
static foreach(x; iota(3).map!(i => tuple(text("x", i), i)))
{
// generates three local variables x0, x1 and x2.
mixin(text(`int `,x[0],` = x[1];`));
scope(exit) // this is within the scope of 'main'
{
writeln(mixin(x[0]));
}
}
writeln(x0," ",x1," ",x2); // first runtime output
}
2. Aliases can be created directly from a '__trait'.
Aliases can be created directly from the traits that return symbol(s) or
tuples. This includes 'getMember', 'allMembers', 'derivedMembers', 'parent',
'getOverloads', 'getVirtualFunctions', 'getVirtualMethods', 'getUnitTests',
'getAttributes' and finally 'getAliasThis'. Previously an 'AliasSeq' was
necessary in order to alias their return. Now the grammar allows to write
shorter declarations:
struct Foo
{
static int a;
}
alias oldWay = AliasSeq!(__traits(getMember, Foo, "a"))[0];
alias newWay = __traits(getMember, Foo, "a");
To permit this it was more interesting to include '__trait' in the basic types
rather than just changing the alias syntax. So additionally, wherever a type
appears a '__trait' can be used, for example in a variable declaration:
struct Foo { static struct Bar {} }
const(__traits(getMember, Foo, "Bar")) fooBar;
static assert(is(typeof(fooBar) == const(Foo.Bar)));
3. fix Issue 10100 - Identifiers with double underscores and allMembers
The identifer whitelist has been converted into a blacklist of all possible
internal D language declarations.
Reviewed-on: https://github.com/dlang/dmd/pull/10791
Vasee Vinayagamoorthy [Fri, 13 Mar 2020 19:43:34 +0000 (19:43 +0000)]
testsuite: Fix misquoted string in bfcvt-nosimd.c
2020-03-13 Vasee Vinayagamoorthy <vaseeharan.vinayagamoorthy@arm.com>
gcc/testsuite/
* gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Fix DejaGnu
typo.
Vladimir N. Makarov [Fri, 13 Mar 2020 18:58:57 +0000 (14:58 -0400)]
PR92303: Try to simplify memory subreg.
2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/92303
* lra-spills.c (remove_pseudos): Try to simplify memory subreg.
Martin Sebor [Fri, 13 Mar 2020 18:29:33 +0000 (12:29 -0600)]
PR c/94040 - ICE on a call to an invalid redeclaration of strftime
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr54261-1.c: Correct built-in declartion.
Eric Botcazou [Fri, 13 Mar 2020 17:02:40 +0000 (18:02 +0100)]
Fix wrong year in ChangeLog.
Martin Sebor [Fri, 13 Mar 2020 16:28:26 +0000 (10:28 -0600)]
PR c/94040 - ICE on a call to an invalid redeclaration of strftime
gcc/c/ChangeLog:
PR c/94040
* c-decl.c (builtin_structptr_type_count): New constant.
(match_builtin_function_types): Reject decls that are incompatible
in types pointed to by pointers.
(diagnose_mismatched_decls): Adjust comments.
gcc/testsuite/ChangeLog:
PR c/94040
* gcc.dg/Wbuiltin-declaration-mismatch-12.c: Relax test to look
for warning name rather than the exact text.
* gcc.dg/Wbuiltin-declaration-mismatch-14.c: New test.
* gcc.dg/Wbuiltin-declaration-mismatch-15.c: New test.
* gcc.dg/pr62090.c: Prune expected warning.
* gcc.dg/pr89314.c: Look for warning name rather than text.
Uros Bizjak [Fri, 13 Mar 2020 15:34:32 +0000 (16:34 +0100)]
testsuite: Assorted x32 testsuite fixes
* gcc.target/i386/pr64409.c: Do not limit compilation to x32 targets.
(dg-error): Quote 'ms_abi' attribute.
* gcc.target/i386/pr71958.c: Do not limit compilation to x32 targets.
Require maybe_x32 effective target.
(dg-options): Add -mx32.
(dg-error): Quote 'ms_abi' attribute.
* gcc.target/i386/pr90096.c (dg-error): Update relative
location of target x32 error.
Segher Boessenkool [Thu, 12 Mar 2020 07:12:50 +0000 (07:12 +0000)]
df: Don't abuse bb->aux (PR94148, PR94042)
The df dataflow solvers use the aux field in the basic_block struct,
although that is reserved for any use by passes. And not only that,
it is required that you set all such fields to NULL before calling
the solvers, or you quietly get wrong results.
This changes the solvers to use a local array for last_change_age
instead, just like it already had a local array for last_visit_age.
PR rtl-optimization/94148
PR rtl-optimization/94042
* df-core.c (BB_LAST_CHANGE_AGE): Delete.
(df_worklist_propagate_forward): New parameter last_change_age, use
that instead of bb->aux.
(df_worklist_propagate_backward): Ditto.
(df_worklist_dataflow_doublequeue): Use a local array last_change_age.
Patrick Palka [Thu, 12 Mar 2020 18:38:42 +0000 (14:38 -0400)]
c++: Redundant -Wdeprecated-declarations warning in build_over_call [PR67960]
In build_over_call, we are emitting a redundant -Wdeprecated-declarations
warning about the deprecated callee function, first from mark_used and again
from build_addr_func <- decay_conversion <- cp_build_addr_expr <- mark_used.
It seems this second deprecation warning coming from build_addr_func will always
be redundant, so we can safely use a warning_sentinel to disable it before
calling build_addr_func. (And any deprecation warning that could come from
build_addr_func would be for FN, so we wouldn't be suppressing too much.)
gcc/cp/ChangeLog:
PR c++/67960
* call.c (build_over_call): Use a warning_sentinel to disable
warn_deprecated_decl before calling build_addr_func.
gcc/testsuite/ChangeLog:
PR c++/67960
* g++.dg/diagnostic/pr67960.C: New test.
* g++.dg/diagnostic/pr67960-2.C: New test.
Richard Biener [Fri, 13 Mar 2020 12:56:26 +0000 (13:56 +0100)]
tree-optimization/94163 constrain alignment set by PRE
This avoids HWI -> unsigned truncation to end up with zero alignment
which set_ptr_info_alignment ICEs on.
2020-03-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/94163
* tree-ssa-pre.c (create_expression_by_pieces): Check
whether alignment would be zero.
Martin Liska [Fri, 13 Mar 2020 12:50:01 +0000 (13:50 +0100)]
Do not strcat to result of getenv.
PR lto/94157
* lto-wrapper.c (run_gcc): Use concat for appending
to collect_gcc_options.
PR lto/94157
* gcc.dg/lto/pr94157_0.c: New test.
Kewen Lin [Fri, 13 Mar 2020 10:51:21 +0000 (05:51 -0500)]
[testsuite] Fix PR93935 to guard case under vect_hw_misalign
This patch is to apply the same fix as r267528 to another similar case
bb-slp-over-widen-2.c which requires misaligned vector access.
gcc/testsuite/ChangeLog
PR testsuite/93935
* gcc.dg/vect/bb-slp-over-widen-2.c: Expect basic block vectorized
messages only on vect_hw_misalign targets.
Jakub Jelinek [Fri, 13 Mar 2020 10:33:16 +0000 (11:33 +0100)]
aarch64: Fix another bug in aarch64_add_offset_1 [PR94121]
> I'm getting this ICE with -mabi=ilp32:
>
> during RTL pass: fwprop1
> /opt/gcc/gcc-
20200312/gcc/testsuite/gcc.dg/pr94121.c: In function 'bar':
> /opt/gcc/gcc-
20200312/gcc/testsuite/gcc.dg/pr94121.c:16:1: internal compiler error: in decompose, at rtl.h:2279
That is a preexisting issue, caused by another bug in the same function.
When mode is SImode and moffset is 0x80000000 (or anything else with the
bit 31 set), we need to sign-extend it.
2020-03-13 Jakub Jelinek <jakub@redhat.com>
PR target/94121
* config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
instead of GEN_INT.
H.J. Lu [Fri, 13 Mar 2020 09:48:59 +0000 (02:48 -0700)]
i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV
There is no need to set mode attribute to XImode nor V8DFmode since
ix86_output_ssemov can properly encode xmm16-xmm31 registers with and
without AVX512VL.
gcc/
PR target/89229
* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
* config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
TARGET_AVX512VL and ext_sse_reg_operand check.
gcc/testsuite/
PR target/89229
* gcc.target/i386/pr89229-4a.c: New test.
* gcc.target/i386/pr89229-4b.c: Likewise.
* gcc.target/i386/pr89229-4c.c: Likewise.
Bu Le [Thu, 12 Mar 2020 22:39:12 +0000 (22:39 +0000)]
aarch64: Add --params to control the number of recip steps [PR94154]
-mlow-precision-div hard-coded the number of iterations to 2 for double
and 1 for float. This patch adds a --param to control the number.
2020-03-13 Bu Le <bule1@huawei.com>
gcc/
PR target/94154
* config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
(-param=aarch64-double-recp-precision=): New options.
* doc/invoke.texi: Document them.
* config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
instead of hard-coding the choice of 1 for float and 2 for double.
Eric Botcazou [Fri, 13 Mar 2020 08:58:44 +0000 (09:58 +0100)]
Fix incorrect filling of delay slots in branchy code at -O2
The issue is that relax_delay_slots can streamline the CFG in some cases,
in particular remove BARRIERs, but removing BARRIERs changes the way the
instructions are associated with (basic) blocks by the liveness analysis
code in resource.c (find_basic_block) and thus can cause entries in the
cache maintained by resource.c to become outdated, thus producing wrong
answers downstream.
The fix is to invalidate the cache entries affected by the removal of
BARRIERs in relax_delay_slots, i.e. for the instructions down to the
next BARRIER.
PR rtl-optimization/94119
* resource.h (clear_hashed_info_until_next_barrier): Declare.
* resource.c (clear_hashed_info_until_next_barrier): New function.
* reorg.c (add_to_delay_list): Fix formatting.
(relax_delay_slots): Call clear_hashed_info_until_next_barrier on
the next instruction after removing a BARRIER.
Eric Botcazou [Fri, 13 Mar 2020 08:16:29 +0000 (09:16 +0100)]
Fix unaligned load with small memcpy on the ARM
store_integral_bit_field is ready to handle BLKmode fields, there is
even a subtlety with their handling on big-endian targets, see e.g.
PR middle-end/50325, but not if they are unaligned, so the fix is
simply to call extract_bit_field for them in order to generate an
unaligned load. As a bonus, this subsumes the big-endian specific
path that was added under PR middle-end/50325.
PR middle-end/92071
* expmed.c (store_integral_bit_field): For fields larger than a
word, call extract_bit_field on the value if the mode is BLKmode.
Remove specific path for big-endian targets and tidy things up a
little bit.
GCC Administrator [Fri, 13 Mar 2020 00:16:15 +0000 (00:16 +0000)]
Daily bump.
Richard Sandiford [Thu, 12 Mar 2020 22:09:27 +0000 (16:09 -0600)]
Remove no-op register to register copies in CSE just like we remove no-op memory to memory copies.
PR rtl-optimization/90275
* cse.c (cse_insn): Delete no-op register moves too.
PR rtl-optimization/90275
* gcc.c-torture/compile/pr90275.c: New test.
Jeff Law [Thu, 12 Mar 2020 19:41:28 +0000 (13:41 -0600)]
Support for the CPEN control register was removed in rev .50 of the RXv1 Instruction Set Architecture manual in Feb 2009. This patch removes it from GCC.
* config/rx/rx.md (CTRLREG_CPEN): Remove.
* config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
Jakub Jelinek [Thu, 12 Mar 2020 17:30:16 +0000 (18:30 +0100)]
maintainer-scripts: Fix up gcc_release without -l, where mkdir was using umask 077 after migration
2020-03-12 Jakub Jelinek <jakub@redhat.com>
* gcc_release (upload_files): Without -l, pass -m 755 to the mkdir
command invoked through ssh.
Jakub Jelinek [Thu, 12 Mar 2020 13:46:28 +0000 (14:46 +0100)]
maintainer-scripts: Fix jit documentation build with update_web_docs_git
scripts/update_web_docs_git -r 9.3.0 -d gcc-9.3.0
failed after the sourceware upgrade, there is no python-sphinx10 package and
python3-sphinx is new enough that the docs build succeeded.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
* update_web_docs_git: Drop SPHINXBUILD=/usr/bin/sphinx-1.0-build.
Richard Biener [Thu, 12 Mar 2020 13:18:35 +0000 (14:18 +0100)]
tree-optimization/94103 avoid CSE of loads with padding
VN currently replaces a load of a 16 byte entity 128 bits of precision
(TImode) with the result of a load of a 16 byte entity with 80 bits of
mode precision (XFmode). That will go downhill since if the padding
bits are not actually filled with memory contents those bits are
missing.
2020-03-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/94103
* tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
punning when the mode precision is not sufficient.
* gcc.target/i386/pr94103.c: New testcase.
Jonathan Wakely [Thu, 12 Mar 2020 11:03:04 +0000 (11:03 +0000)]
libstdc++: Fix test failure due to -Wnonnull warnings
This test fails in the Fedora RPM build (but not elsewhere, for unknown
reasons). The warning is correct, we're passing a null pointer.
* testsuite/tr1/8_c_compatibility/cstdlib/functions.cc: Do not pass
a null pointer to functions with nonnull(1) attribute.
H.J. Lu [Thu, 12 Mar 2020 10:47:45 +0000 (03:47 -0700)]
i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV
There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.
PR target/89229
* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
MODE_V1DF and MODE_V2SF.
* config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
check.
Tobias Burnus [Thu, 12 Mar 2020 09:57:56 +0000 (10:57 +0100)]
[Fortran, OpenACC] Reject vars of different scope in $acc declare (PR94120)
2020-03-12 Tobias Burnus <tobias@codesourcery.com>
PR middle-end/94120
* openmp.c (gfc_match_oacc_declare): Accept function-result
variables; reject variables declared in a different scoping unit.
2020-03-12 Tobias Burnus <tobias@codesourcery.com>
PR middle-end/94120
* gfortran.dg/goacc/pr78260-2.f90: Correct scan-tree-dump-times.
Extend test case to result variables.
* gfortran.dg/goacc/declare-2.f95: Actually check module-declaration
restriction of OpenACC.
* gfortran.dg/goacc/declare-3.f95: Remove case where this
restriction is violated.
* gfortran.dg/goacc/pr94120-1.f90: New.
* gfortran.dg/goacc/pr94120-2.f90: New.
* gfortran.dg/goacc/pr94120-3.f90: New.
Jakub Jelinek [Thu, 12 Mar 2020 08:35:30 +0000 (09:35 +0100)]
doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description
When looking into PR94134, I've noticed bugs in the
ASM_OUTPUT_ALIGNED_DECL_LOCAL documentation. varasm.c has:
#if defined ASM_OUTPUT_ALIGNED_DECL_LOCAL
unsigned int align = symtab_node::get (decl)->definition_alignment ();
ASM_OUTPUT_ALIGNED_DECL_LOCAL (asm_out_file, decl, name,
size, align);
return true;
#elif defined ASM_OUTPUT_ALIGNED_LOCAL
unsigned int align = symtab_node::get (decl)->definition_alignment ();
ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size, align);
return true;
#else
ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded);
return false;
#endif
and the ASM_OUTPUT_ALIGNED_LOCAL documentation properly mentions:
Like @code{ASM_OUTPUT_LOCAL} and mentions the same macro in another place.
The ASM_OUTPUT_ALIGNED_DECL_LOCAL description mentions non-existing macros
ASM_OUTPUT_ALIGNED_DECL and ASM_OUTPUT_DECL instead of the right ones
ASM_OUTPUT_ALIGNED_LOCAL and ASM_OUTPUT_LOCAL.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
* doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
* doc/tm.texi: Regenerated.
Jakub Jelinek [Thu, 12 Mar 2020 08:34:00 +0000 (09:34 +0100)]
tree-dse: Fix mem* head trimming if call has lhs [PR94130]
As the testcase shows, if DSE decides to head trim {mem{set,cpy,move},strncpy}
and the call has lhs, it is incorrect to leave the lhs as is, because it
will then point to the adjusted address (base + head_trim) instead of the
original base.
The following patch fixes that by dropping the lhs of the call and assigning
lhs the original base in a following statement.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94130
* tree-ssa-dse.c: Include gimplify.h.
(increment_start_addr): If stmt has lhs, drop the lhs from call and
set it after the call to the original value of the first argument.
Formatting fixes.
(decrement_count): Formatting fix.
* gcc.c-torture/execute/pr94130.c: New test.
Jakub Jelinek [Thu, 12 Mar 2020 07:28:05 +0000 (08:28 +0100)]
c++: Tweak reshape_init_array_1 [PR94124]
Isn't it wasteful to first copy perhaps a large constructor (recursively)
and then truncate it to very few elts (zero in this case)?
> We should certainly avoid copying if they're the same. The code above for
> only copying the bits that aren't going to be thrown away seems pretty
> straightforward, might as well use it even if the savings aren't likely to
> be large.
Calling vec_safe_truncate with the same number of elts the vector already
has is a nop, so IMHO we just should make sure we only unshare if it
changed.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
PR c++/94124
* decl.c (reshape_init_array_1): Don't unshare constructor if there
aren't any trailing zero elts, otherwise only unshare the first
nelts.
Bin Bin Lv [Thu, 12 Mar 2020 03:32:40 +0000 (23:32 -0400)]
Update myself to MAINTAINERS
This updates myself to the right place in MAINTAINERS.
gcc/ChangeLog
2020-03-11 Bin Bin Lv <shlb@linux.ibm.com>
* MAINTAINERS (Write After Approval): Update myself.
Bin Bin Lv [Thu, 12 Mar 2020 02:25:31 +0000 (22:25 -0400)]
[rs6000] Fix a wrong GC issue
The source file rs6000.c was split up into several smaller source files
through commit
1acf024. However, variable "altivec_builtin_mask_for_load" and
"builtin_mode_to_type[MAX_MACHINE_MODE][2]" were marked with the wrong syntax
"GTY(([options])) type name", which led these two variables were not marked as
roots correctly and wrongly GCed. And when "altivec_builtin_mask_for_load"
was wrongly GCed, the compiling for openJDK is failed with ICEs enabling
precompiled header under mcpu=power7. So roots must be declared using one of
the following syntaxes: "extern GTY(([options])) type name;" and "static
GTY(([options])) type name;".
And the following patch adds variable "altivec_builtin_mask_for_load" and
"builtin_mode_to_type[MAX_MACHINE_MODE][2]" into the roots array.
Bootstrap and regression tests were done on powerpc64le-linux-gnu (LE) with no
regressions.
gcc/ChangeLog
2020-03-11 Bin Bin Lv <shlb@linux.ibm.com>
* config/rs6000/rs6000-internal.h (altivec_builtin_mask_for_load,
builtin_mode_to_type): Remove the declaration.
* config/rs6000/rs6000.h (altivec_builtin_mask_for_load,
builtin_mode_to_type): Add an extern GTY(()) declaration.
* config/rs6000/rs6000.c (altivec_builtin_mask_for_load,
builtin_mode_to_type): Remove the GTY(()) declaration.
Bin Bin Lv [Thu, 12 Mar 2020 01:41:18 +0000 (21:41 -0400)]
Add myself to MAINTAINERS
This adds myself to MAINTAINERS in the Write After Approval section.
gcc/ChangeLog
2020-03-11 Bin Bin Lv <shlb@linux.ibm.com>
* MAINTAINERS (Write After Approval): Add myself.
Jakub Jelinek [Thu, 12 Mar 2020 00:28:55 +0000 (01:28 +0100)]
testsuite: Fix concepts-using2.C failure on 32-bit targets [PR93907]
The test FAILs on 32-bit targets that don't have __int128 type.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
PR c++/93907
* g++.dg/cpp2a/concepts-using2.C (cc): Use long long instead of
__int128 if __SIZEOF_INT128__ isn't defined.
GCC Administrator [Thu, 12 Mar 2020 00:16:14 +0000 (00:16 +0000)]
Daily bump.
Jason Merrill [Wed, 11 Mar 2020 04:53:01 +0000 (00:53 -0400)]
c++: Fix ICE with concepts and aliases [PR93907].
The problem here was that we were checking satisfaction once with 'e', a
typedef of 'void', and another time with 'void' directly, and treated them
as different for hashing based on the assumption that
canonicalize_type_argument would have already removed a typedef that wasn't
a complex dependent alias. But that wasn't happening here, so let's add a
call.
gcc/cp/ChangeLog
2020-03-11 Jason Merrill <jason@redhat.com>
PR c++/93907
* constraint.cc (tsubst_parameter_mapping): Canonicalize type
argument.
Marek Polacek [Fri, 6 Mar 2020 22:30:11 +0000 (17:30 -0500)]
c++: Fix wrong modifying const object error for COMPONENT_REF [PR94074]
I got a report that building Chromium fails with the "modifying a const
object" error. After some poking I realized it's a bug in GCC, not in
their codebase.
Much like with ARRAY_REFs, which can be const even though the array
itself isn't, COMPONENT_REFs can be const although neither the object
nor the field were declared const. So let's dial down the checking.
Here the COMPONENT_REF was const because of the "const_cast<const U &>(m)"
thing -- cxx_eval_component_reference then builds a COMPONENT_REF with
TREE_TYPE (t).
While looking into this I noticed that we don't detect modifying a const
object in certain cases like in
<https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94074#c2>. That's because
we never evaluate an X::X() CALL_EXPR -- there's none. Fixed as per
Jason's suggestion by setting TREE_READONLY on a CONSTRUCTOR after
initialization in cxx_eval_store_expression.
2020-03-11 Marek Polacek <polacek@redhat.com>
Jason Merrill <jason@redhat.com>
PR c++/94074 - wrong modifying const object error for COMPONENT_REF.
* constexpr.c (cref_has_const_field): New function.
(modifying_const_object_p): Consider a COMPONENT_REF
const only if any of its fields are const.
(cxx_eval_store_expression): Mark a CONSTRUCTOR of a const type
as readonly after its initialization has been done.
* g++.dg/cpp1y/constexpr-tracking-const17.C: New test.
* g++.dg/cpp1y/constexpr-tracking-const18.C: New test.
* g++.dg/cpp1y/constexpr-tracking-const19.C: New test.
* g++.dg/cpp1y/constexpr-tracking-const20.C: New test.
* g++.dg/cpp1y/constexpr-tracking-const21.C: New test.
* g++.dg/cpp1y/constexpr-tracking-const22.C: New test.
Patrick Palka [Wed, 11 Mar 2020 15:08:49 +0000 (11:08 -0400)]
libstdc++: Add a test that takes the split_view of a non-forward range
This adds a tests that verifies taking the split_view of a non-forward range
works correctly. Doing so revealed a typo in one of _OuterIter's constructors.
It also revealed that the default constructor of
__gnu_test::test_range::iterator misbehaves, because by delegating to
Iter<T>(nullptr, nullptr) we perform a null-pointer deref at runtime in
input_iterator_wrapper's constructor due to the ITERATOR_VERIFY check therein.
Instead of delegating to this constructor it seems we can just inherit the
protected default constructor, which does not contain this ITERATOR_VERIFY
check.
libstdc++-v3/ChangeLog:
* include/std/ranges (split_view::_OuterIter::_OuterIter): Typo fix,
'address' -> 'std::__addressof'.
* testsuite/std/ranges/adaptors/split.cc: Test taking the split_view of
a non-forward input_range.
* testsuite/util/testsuite_iterators.h (output_iterator_wrapper): Make
default constructor protected instead of deleted, like with
input_iterator_wrapper.
(test_range::iterator): Add comment explaining that this type is used
only when the underlying wrapper is input_iterator_wrapper or
output_iterator_wrapper. Remove delegating defaulted constructor so
that the inherited default constructor is used instead.
Delia Burduv [Wed, 11 Mar 2020 18:01:26 +0000 (18:01 +0000)]
Bug fix: cannot convert 'const short int*' to 'const __bf16*'
This patch fixes a bug introduced by my earlier patch (
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ).
It introduces a new scalar builtin type that was missing in the original
patch.
Bootstrapped cleanly on arm-none-linux-gnueabihf.
Tested for regression on arm-none-linux-gnueabihf. No regression from
before the original patch.
Tests that failed or became unsupported because of the original tests
now work as they did before it.
* config/arm/arm-builtins.c
(arm_init_simd_builtin_scalar_types): New.
* config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
(vld2q_bf16): Used new builtin type.
(vld3_bf16): Used new builtin type.
(vld3q_bf16): Used new builtin type.
(vld4_bf16): Used new builtin type.
(vld4q_bf16): Used new builtin type.
(vld2_dup_bf16): Used new builtin type.
(vld2q_dup_bf16): Used new builtin type.
(vld3_dup_bf16): Used new builtin type.
(vld3q_dup_bf16): Used new builtin type.
(vld4_dup_bf16): Used new builtin type.
(vld4q_dup_bf16): Used new builtin type.
Jakub Jelinek [Wed, 11 Mar 2020 17:35:13 +0000 (18:35 +0100)]
pdp11: Fix handling of common (local and global) vars [PR94134]
As mentioned in the PR, the generic code decides to put the a variable into
lcomm_section, which is a NOSWITCH section and thus the generic code doesn't
switch into a particular section before using
ASM_OUTPUT{_ALIGNED{,_DECL}_}_LOCAL, on many targets that results just in
.lcomm (or for non-local .comm) directives which don't need a switch to some
section, other targets put switch_to_section (bss_section) at the start of
that macro.
pdp11 doesn't do that (and doesn't have bss_section), and so emits the
lcomm/comm variables in whatever section is current (it has only .text/.data
and for DEC assembler rodata).
The following patch fixes that by putting it always into data section, and
additionally avoids emitting an empty line in the assembly for the lcomm
vars.
2020-03-11 Jakub Jelinek <jakub@redhat.com>
PR target/94134
* config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
at the start to switch to data section. Don't print extra newline if
.globl directive has not been emitted.
* gcc.c-torture/execute/pr94134.c: New test.
Kito Cheng [Wed, 11 Mar 2020 09:48:10 +0000 (17:48 +0800)]
RISC-V: Fix testsuite regression due to recent IRA changes.
After IRA changes, atomic version will use one more register, but
non-atomic still use 2 registers, however this testcase isn't testing for
atomic feature, so I decide change the testcase to always use COUNT++
to test.
ChangeLog
gcc/testsuite/
Kito Cheng <kito.cheng@sifive.com>
* gcc.target/riscv/interrupt-2.c: Update testcase and expected output.
Richard Biener [Wed, 11 Mar 2020 14:34:47 +0000 (15:34 +0100)]
fold undefined pointer offsetting
This avoids breaking the old broken pointer offsetting via
(T)(ptr - ((T)0)->x) which should have used offsetof. Breakage
was exposed by the introduction of POINTER_DIFF_EXPR and making
PTA not considering that producing a pointer. The mitigation
for simple cases is to canonicalize
_2 = _1 - 8B;
o_9 = (struct obj *) _2;
to
o_9 = &MEM[_1 + -8B];
eliding one statement and the offending pointer subtraction.
2020-03-11 Richard Biener <rguenther@suse.de>
* match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
New pattern.
* gcc.dg/torture/
20200311-1.c: New testcase.
Matthew Malcomson [Wed, 11 Mar 2020 14:06:21 +0000 (14:06 +0000)]
[testsuite] Add @ lines to check-function-bodies fluff
When using `check-function-bodies`, the subroutine `parse_function_bodies` uses
the `fluff` regexp to remove uninteresting assembly lines.
Arm targets generate assembly with some lines prefixed by `@`, these lines are
left by this process.
As an example of some lines prefixed by `@': the assembly output from the
`stacktest1` function in "bfloat16_simd_3_1.c" is:
.align 2
.global stacktest1
.arch armv8.2-a
.syntax unified
.arm
.fpu neon-fp-armv8
.type stacktest1, %function
stacktest1:
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
sub sp, sp, #8
add r3, sp, #6
vst1.16 {d0[0]}, [r3]
vld1.16 {d0[0]}, [r3]
add sp, sp, #8
@ sp needed
bx lr
.size stacktest1, .-stacktest1
It seems that previous uses of `check-function-bodies` in the arm backend have
avoided problems with such lines since they use the `...` regexp in each place
such fluff occurs.
I'm currently writing a patch that I'd like to match the entire function body,
so I'd like to remove such `@` lines automatically.
gcc/testsuite/ChangeLog:
2020-03-11 Matthew Malcomson <matthew.malcomson@arm.com>
* lib/scanasm.exp (parse_function_bodies): Lines starting with '@' also
counted as fluff.
Eric Botcazou [Wed, 11 Mar 2020 10:29:39 +0000 (11:29 +0100)]
Fix GIMPLE verification failure in LTO mode on Ada code
The issue is that tree_is_indexable doesn't return the same result for
a FIELD_DECL with QUAL_UNION_TYPE and the QUAL_UNION_TYPE, resulting
in two instances of the QUAL_UNION_TYPE in the bytecode. The result
for the type is the correct one (false, since it is variably modified)
while the result for the field is falsely true because:
else if (TREE_CODE (t) == FIELD_DECL
&& lto_variably_modified_type_p (DECL_CONTEXT (t)))
return false;
is not satisfied. The reason for this is that the DECL_QUALIFIER of
fields of a QUAL_UNION_TYPE depends on a discriminant in Ada, which
means that the size of the type does too (CONTAINS_PLACEHOLDER_P),
which in turn means that it is reset to a mere PLACEHOLDER_EXPR by
free_lang_data, which finally means that the size of DECL_CONTEXT is
too, so RETURN_TRUE_IF_VAR is false.
In other words, the CONTAINS_PLACEHOLDER_P property of the DECL_QUALIFIER
of fields of a QUAL_UNION_TYPE hides the variably_modified_type_p property
of these fields, if you look from the outside.
PR middle-end/93961
* tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into
fields whose type is a qualified union.
Eric Botcazou [Wed, 11 Mar 2020 09:47:34 +0000 (10:47 +0100)]
Fix internal error on locally-defined subpools
If the type is derived in the current compilation unit, and Allocate
is not overridden on derivation (as is typically the case with
Root_Storage_Pool_With_Subpools), the entity for Allocate of the
derived type is an alias for System.Storage_Pools.Subpools.Allocate.
The main assertion in gnat_to_gnu_entity fails in this case, since
this is not a definition and Is_Public is false (since the entity
is nested in the same compilation unit).
2020-03-11 Richard Wai <richard@annexi-strayline.com>
* gcc-interface/decl.c (gnat_to_gnu_entity): Also test Is_Public on
the Alias of the entitiy, if is present, in the main assertion.
Jakub Jelinek [Wed, 11 Mar 2020 09:54:22 +0000 (10:54 +0100)]
aarch64: Fix ICE in aarch64_add_offset_1 [PR94121]
abs_hwi asserts that the argument is not HOST_WIDE_INT_MIN and as the
(invalid) testcase shows, the function can be called with such an offset.
The following patch is IMHO minimal fix, absu_hwi unlike abs_hwi allows even
that value and will return (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN
in that case. The function then uses moffset in two spots which wouldn't
care if the value is (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN or
HOST_WIDE_INT_MIN and wouldn't accept it (!moffset and
aarch64_uimm12_shift (moffset)), then in one spot where the signedness of
moffset does matter and using unsigned is the right thing -
moffset < 0x1000000 - and finally has code which will handle even this
value right; the assembler doesn't really care for DImode immediates if
mov x1, -
9223372036854775808
or
mov x1,
9223372036854775808
is used and similarly it doesn't matter if we add or sub it in DImode.
2020-03-11 Jakub Jelinek <jakub@redhat.com>
PR target/94121
* config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
* gcc.dg/pr94121.c: New test.
Jakub Jelinek [Wed, 11 Mar 2020 08:34:59 +0000 (09:34 +0100)]
value-prof: Fix abs uses in value-prof.c [PR93962]
Jeff has recently fixed dump_histogram_value to use std::abs instead of abs,
because on FreeBSD apparently the ::abs isn't overloaded and only has
int abs (int);
Seems on Solaris /usr/include/iso/stdlib_iso.h abs has:
int abs (int);
long abs (long);
overloads but already not
long long abs (long long);
and there is another abs use in get_nth_most_common_value, also on int64_t.
The long long std::abs (long long); overload is there only in C++11 and we
in GCC10 still support C++98.
Martin has said that a counter should never be INT64_MIN, so IMHO it is
better to use abs_hwi which will assert that.
2020-03-11 Jakub Jelinek <jakub@redhat.com>
PR bootstrap/93962
* value-prof.c (dump_histogram_value): Use abs_hwi instead of
std::abs.
(get_nth_most_common_value): Use abs_hwi instead of abs.
Jakub Jelinek [Wed, 11 Mar 2020 08:33:52 +0000 (09:33 +0100)]
dfp: Fix decimal_to_binary [PR94111]
As e.g. decimal_from_decnumber shows, the REAL_VALUE_TYPE representation
contains a decimal128 embedded in ->sig only if it is rvc_normal, for
other kinds like rvc_inf or rvc_nan, ->sig is ignored and everything is
contained in the REAL_VALUE_TYPE flags (cl, sign, signalling and decimal).
decimal_to_binary which is used when folding a decimal{32,64,128} constant
to a binary floating point type ignores this and thus folds infinities and
NaNs into +0.0.
The following patch fixes that by only doing that for rvc_normal.
Similarly to the binary to decimal folding, it goes through a string, in
order to e.g. deal with canonical NaN mantissas, or binary float formats
that don't support infinities and/or NaNs.
2020-03-11 Jakub Jelinek <jakub@redhat.com>
PR middle-end/94111
* dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
is rvc_normal, otherwise use real_to_decimal to print the number to
string.
* gcc.dg/dfp/pr94111.c: New test.
Jakub Jelinek [Wed, 11 Mar 2020 08:32:22 +0000 (09:32 +0100)]
ldist: Further fixes for -ftrapv [PR94114]
As the testcase shows, arithmetics that for -ftrapv would need multiple
basic blocks can show up not just in nb_bytes expressions where we
are calling rewrite_to_non_trapping_overflow for a while already,
but also in the pointer expression to the start of the region.
While the testcase covers just the first hunk and I've failed to create
a testcase for the latter, it is at least in theory possible too, so I've
adjusted that hunk too.
2020-03-11 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94114
* tree-loop-distribution.c (generate_memset_builtin): Call
rewrite_to_non_trapping_overflow even on mem.
(generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
on dest and src.
* gcc.dg/pr94114.c: New test.
Patrick Palka [Mon, 9 Mar 2020 16:10:16 +0000 (12:10 -0400)]
libstdc++: LWG 3286 ranges::size is not required to be valid after ...
... a call to ranges::begin on an input range.
This implements LWG 3286. The new wording for the single-argument constructor
for subrange is implemented by splitting the constructor into two delegating
constructors, one constrained by _S_store_size and the other by !_S_store_size.
Tested on x86_64-pc-linux-gnu, both added tests fail before the patch and pass
with the patch.
libstdc++-v3/ChangeLog:
LWG 3286 ranges::size is not required to be valid after a call to
ranges::begin on an input range
* include/std/ranges (subrange::subrange): Split single-argument
constructor into two, one constrained by _S_store_size and another by
!_S_store_size.
(take_view::begin): Call size() before calling ranges::begin(_M_base).
* testsuite/std/ranges/adaptors/lwg3286.cc: New test.
* testsuite/std/ranges/subrange/lwg3286.cc: New test.
Jeff Law [Wed, 11 Mar 2020 04:16:19 +0000 (22:16 -0600)]
Fix length computation for movsi_insv which resulted in regressions due to out of range branches on the bfin port.
* config/bfin/bfin.md (movsi_insv): Add length attribute.
Marek Polacek [Tue, 10 Mar 2020 22:55:42 +0000 (18:55 -0400)]
c++: Fix wrong conversion error with non-viable overload [PR94124]
This is a bad interaction between sharing a constructor for an array
and stripping its trailing zero-initializers. Here we reuse a ctor
and then strip its 0s. This breaks overload resolution in this test:
D can be initialized from {} but not from {0}, so if we truncate the
constructor not to include the zero, the F(D) overload becomes valid
and then we get the ambiguous conversion error.
PR c++/94124 - wrong conversion error with non-viable overload.
* decl.c (reshape_init_array_1): Unshare a constructor if we
stripped trailing zero-initializers.
* g++.dg/cpp0x/initlist-overload1.C: New test.
Jason Merrill [Tue, 10 Mar 2020 21:31:33 +0000 (17:31 -0400)]
c++: Fix deferred noexcept on constructor [PR93901].
My change in r10-4394 to only update clones when we actually instantiate a
deferred noexcept-spec broke this because deferred parsing updates the
primary function but not the clones. For GCC 10, let's just revert it.
gcc/cp/ChangeLog
2020-03-10 Jason Merrill <jason@redhat.com>
PR c++/93901
* pt.c (maybe_instantiate_noexcept): Always update clones.
Jason Merrill [Tue, 10 Mar 2020 21:51:46 +0000 (17:51 -0400)]
c++: Fix ICE with omitted template args [PR93956].
reshape_init only wants to work on BRACE_ENCLOSED_INITIALIZER_P, i.e. raw
initializer lists, and here was getting a CONSTRUCTOR that had already been
processed for type A<int>. maybe_aggr_guide should also use that test.
gcc/cp/ChangeLog
2020-03-10 Jason Merrill <jason@redhat.com>
PR c++/93956
* pt.c (maybe_aggr_guide): Check BRACE_ENCLOSED_INITIALIZER_P.
Jiufu Guo [Tue, 10 Mar 2020 05:51:57 +0000 (13:51 +0800)]
rs6000: Check -+0 and NaN for smax/smin generation
PR93709 mentioned regressions on maxlocval_4.f90 and minlocval_f.f90 which
relates to max of '-inf' and 'nan'. This regression occur on P9 because
P9 new instruction 'xsmaxcdp' is generated.
And for C code `a < b ? b : a` is also generated as `xsmaxcdp` under -O2
for P9. While this instruction behavior more like C/C++ semantic (a>b?a:b).
This generates prevents 'xsmaxcdp' to be generated for those cases.
'xsmincdp' also is handled in patch.
gcc/
2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/93709
* gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
NAN and SIGNED_ZEROR for smax/smin.
gcc/testsuite
2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/93709
* gcc.target/powerpc/p9-minmax-3.c: New test.
GCC Administrator [Wed, 11 Mar 2020 00:16:14 +0000 (00:16 +0000)]
Daily bump.
Jonathan Wakely [Tue, 10 Mar 2020 22:15:58 +0000 (22:15 +0000)]
libstdc++: Fix uses of _M_current in split_view's outer iterator
These direct uses of _M_current should all be __current() so they are
valid when the base type doesn't satisfy the forward_range concept.
* include/std/ranges (split_view::_OuterIter::__at_end): Use __current
instead of _M_current.
(split_view::_OuterIter::operator++): Likewise.
Jason Merrill [Tue, 10 Mar 2020 20:43:58 +0000 (16:43 -0400)]
c++: Add tests for PR93922 and PR94041.
Jason Merrill [Tue, 10 Mar 2020 20:05:18 +0000 (16:05 -0400)]
c++: Partially revert patch for PR66139.
The patch for 66139 exposed a long-standing bug with
split_nonconstant_init (since 4.7, apparently): initializion of individual
elements of an aggregate are not a full-expressions, but
split_nonconstant_init was making full-expressions out of them. My fix for
66139 extended the use of split_nonconstant_init, and thus the bug, to
aggregate initialization of temporaries within an expression, in which
context (PR94041) the bug is more noticeable. PR93922 is a problem with my
implementation strategy of splitting out at gimplification time, introducing
function calls that weren't in the GENERIC. So I'm going to revert the
patch now and try again for GCC 11.
gcc/cp/ChangeLog
2020-03-10 Jason Merrill <jason@redhat.com>
PR c++/93922
PR c++/94041
PR c++/52320
PR c++/66139
* cp-gimplify.c (cp_gimplify_init_expr): Partially revert patch for
66139: Don't split_nonconstant_init. Remove pre_p parameter.
Will Schmidt [Tue, 10 Mar 2020 19:38:13 +0000 (14:38 -0500)]
PR90763: PowerPC vec_xl_len should take const argument.
PR target/90763
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
* gcc.target/powerpc/pr90763.c: New.
Jonathan Wakely [Tue, 10 Mar 2020 17:45:45 +0000 (17:45 +0000)]
libstdc++: Fix noexcept guarantees for ranges::split_view
Also introduce the _M_i_current() accessors to solve the problem of
access to the private member of _OuterIter from the iter_move and
iter_swap overloads (which are only friends of _InnerIter not
_OuterIter).
* include/std/ranges (transform_view::_Iterator::__iter_move): Remove.
(transform_view::_Iterator::operator*): Add noexcept-specifier.
(transform_view::_Iterator::iter_move): Inline __iter_move body here.
(split_view::_OuterIter::__current): Add noexcept.
(split_view::_InnerIter::__iter_swap): Remove.
(split_view::_InnerIter::__iter_move): Remove.
(split_view::_InnerIter::_M_i_current): New accessors.
(split_view::_InnerIter::__at_end): Use _M_i_current().
(split_view::_InnerIter::operator*): Likewise.
(split_view::_InnerIter::operator++): Likewise.
(iter_move(const _InnerIter&)): Likewise.
(iter_swap(const _InnerIter&, const _InnerIter&)): Likewise.
* testsuite/std/ranges/adaptors/split.cc: Check noexcept-specifier
for iter_move and iter_swap on split_view's inner iterator.
Roman Zhuykov [Tue, 10 Mar 2020 16:54:50 +0000 (19:54 +0300)]
loop-iv: make find_simple_exit static
Function 'find_simple_exit' is used only from loop-iv.c
In 2004-2006 it was also used in predict.c, but since r118694
(
992c31e62304ed5d34247dbdef2db276d08fac05) it does not.
gcc/ChangeLog:
* loop-iv.c (find_simple_exit): Make it static.
* cfgloop.h: Remove the corresponding prototype.
Roman Zhuykov [Tue, 10 Mar 2020 16:47:53 +0000 (19:47 +0300)]
minor: fix intendation in ddg.c
gcc/ChangeLog:
* ddg.c (create_ddg): Fix intendation.
(set_recurrence_length): Likewise.
(create_ddg_all_sccs): Likewise.
Uros Bizjak [Tue, 10 Mar 2020 16:39:21 +0000 (17:39 +0100)]
testsuite: Scan for SSE reg-reg moves only in pr80481.C
The function needs more than 8 SSE registers, avoid
false positives triggered by SSE spills for 32bit targets.
* g++.dg/pr80481.C (dg-final): Scan for SSE reg-reg moves only.
Jeff Law [Tue, 10 Mar 2020 14:38:14 +0000 (08:38 -0600)]
Revert "Fix regression reported by tester due to recent IRA changes"
This reverts commit
d48e1175279a551bf90aa5b165fc46a1d5a2c07e.
2020-03-10 Jeff Law <law@redhat.com>
Revert:
2020-02-29 Jeff Law <law@redhat.com>
* gcc.target/xstormy16/sfr/06_sfrw_to_var.c: Update expected output.